High Layer Count PCB Technology Trends in KOREA April, 21 2011 Sang Soo LEE ISUPETASYS
Contents 2 Definition of High Layer Count PCB Core Technology Trends High Layer Count PCB Technology Drivers Interconnection Reliability
Next Page 3 Definition of High Layer Count PCB Core Technology Trends High Layer Count PCB Technology Drivers Interconnection Reliability
1. Definition of High Layer Count PCB 4 High Layer Count PCB With the popularization of the Internet, wireless data system and mobile communication, High layer count PCB is required to transmit data rapidly and fulfill the need to process data with high speed Application Line Card, Backplane for Communication Network High-End Router, Server, Storage Workstation, Super Computer. General Specification Layer Count : +18L Thickness : <100mil, Aspect ratio : over12:1 Trace Width/Space : 0.075mm/0.075mm Surface Finish : L/F OSP,ENIG, Electrolytic Ni/Gold, Silver, Tin, L/F HASL Impedance : Single ended/differential Base Material : High Tg FR-4,Low/Ultra Dk/Df & Lead free
2. Market Characteristics & Trends 5 Market Characteristics Relatively conservative purchasing than consumer product PCB Prefer to highly experienced PCB supplier Listing on the OEM Vendor List EMS has no independent authority to select PCB supplier Without almost perfect internal QA sys, Higher Claim charge (Ave USD $4~5,000/pcs) No merit at all, without almost perfect inner layer process yield rate (see the below) 11 of 12 = 91.6% yield, 3~4 cores 0%, 8 + cores
2. Market Characteristics & Trends 6 Changing Traditional Trends Giant industrial OEM rushing toward ASIAN PCB SHOPS. WHY? router. server. supercomputer. Aero space., etc Conventionally strong U.S/ Europe pcb shops Closed local factories since IT Bubble or transit SHOPS in Southeast Asia. Unlike Asian, reluctant to invest aggressively new manufacturing facilities Brought to long term delivery (8~10 weeks) Asia PCB Suppliers surprisingly playing well doing job with Excellent technology and brand new facility Low PPM level of Defect Delivery responsiveness
Next Page 7 Definition of High Layer Count PCB Core Technology Trends High Layer Count PCB Technology Drivers Reliability
1. Top Stage- Core technology Trends 8 Industrial technology driver Increasing traffic density across internet, data storage are need for higher volume data throughput The next generation of back planes will require serial data rates of 10Gbps while the emerging. Intermediate back plane products will employ 6.25 Gbps serial data rates. 5/6.25 Gbps => 10Gbps High volume data throughput & High speed signal requiring pcb To design circuit with total signal integrity such as highly accurate impedance control, time delay, signal loss, skin effect, skew etc. System Roadmap Product Technology 2009 2010 2011 2012 Router Band Width 10Gbps 20Gbps 40Gbps Serial Data Rate 6.25Gbps 10Gbps 20Gbps Server Clock Speed 2Ghz 2.5Ghz 3.5Ghz
2. Middle Stage Core Technology Trends 9 Core technology for High Layer Count PCB Higher Volume data throughput & clock speed put dramatically impact on PCB Design. Manufacturing. Reliability and Environmental issue 1.Routing Density 3.Environment al Regulation Higher Data Rate & Clock Speed 2.SignalInt egrity 4.Interconnectio n Reliability Routing Density - HDI (Blind & Buried Via) - VIP (Via in Pad) - Reduction for Layer Count, Line width High Speed Signal Integrity - Electrical Simulation - Buried Capacitance & Resistance - Material & Design (Ultra Low Dk/Df) Environmental Regulation - Lead Free -ROHS Interconnection Reliability -IST - CAF
Next Page 10 Definition of High Layer Count PCB Core Technology Trends High Layer Count PCB Technology Drivers Reliability
1. High Layer Count PCB Technology Drivers 1 11 Core driver 1. Material What is a market s needs for material? Guaranteed same electrical performance (Dk/Df) with lead free compatible material. Guaranteed thermal reliability after lead free assembly. Supply a low cost lead free compatible material. Market s Needs Low Cost
1. High Layer Count PCB Technology Drivers 1 12 Tier 3~5 laminates are gaining an increasing share of the market for high-speed applications (Low Dk / Low Df) Source by IPC
1. High Layer Count PCB Technology Drivers 1 13 What is a difference? Should use a lead free alloys instead of Sn/Pb alloys. SAC Solder need more higher reflow temperatures. Up to 20 C higher Reflow Type Solder Type Solder Melting Point Peak Reflow Temperature Sn/Pb Reflow Eutectic Solder 183 210 ~240 Lead-Free Reflow SAC (96.5Sn/3.0Ag/0.5Cu) Solder 217 240 ~260 260 JEDEC Profile (J-STD-020C) Upper line: Lead free Reflow Lower line: Sn/Pb Reflow
1. High Layer Count PCB Technology Drivers 1 14 What we are considering Comparison of thermal properties for laminate Test Items Dicy Cured 170 Non-Dicy Cured 170 Low Dk/Df 200 Test Vehicle Laminate (Double Side) Laminate (Double Side) Laminate (Double Side) CTE 3.7% 3.0% 3.5% TMA (Tg) 170.0 170.0 170.0 TGA (Td) 325.0 350.0 365.0 T260 4min ~ 8min Over 60min Over 30min T288 2min Over 10min Over 10min
1. High Layer Count PCB Technology Drivers 1 15 1) Comparison of thermal properties for 16L Board Test Items Dicy Cured 170 Non-Dicy Cured 170 Low Dk/Df 200 Layer Count 16L 16L 16L Overall Thickness 2.38mm (9.4mil) 2.38mm (9.4mil) 2.38mm (9.4mil) CTE BGA Area 3.31% 3.52% 2.88% TMA Tg BGA Area 176.6 176.2 200.6 T260-Clad 3.5 min Over 20 min Over 20 min T288-Clad 0 min 3.58 min 1.63 min 2) Comparison of thermal properties for 28L Board Test Items Dicy Cured170 Non-Dicy Cured 170 Low Dk/Df 200 Layer Count 28L 28L 28L Overall Thickness 3.0mm (118mil) 3.0mm(118mil) 3.0mm(118mil) CTE BGA Area 3.83% 3.65% 3.35% TMATg BGA Area 163.4 161.0 177.4 TGA (Td) 312.5 328.0 338.8 T260-Clad 3.2 min Over 20 min 12.85 min T288-Clad 0 min 2.2 min 0 min Lead-Free Reflow 5X Fail Pass Fail
1. High Layer Count PCB Technology Drivers 1 16 What we are considering Lead Free Reflow Test Lead free reflow test is necessary to confirm the evaluation result. You can find de-lamination in black spot area. Dicy Cured 170 C Non-dicy cured 170 C Low Dk/Df 200 C X-Section Dicy Cured 170 C X-Section Low Dk/Df 200 C Evaluation report shows a little bit difference between raw material and PCBs Evaluation report shows a little bit difference between raw material and PCBs. Basically, Thermal reliability is affected by board design (Layer Count,Thickness)
1. High Layer Count PCB Technology Drivers 2 17 Core driver 2. Routing Density 2-1. Routing Density : Finer line width & Layer Count increasing Required : Layer counts 18~22L 24~30L / Line width 5mil 4mil 3mil Key Point 1. (layer count increasing) Handle thin Coreless 100um in process Registration Control High Aspect Ratio of plating Key Point 2. Finer line width Signal line width tolerance ±10% ±7% Signal line width 3/3 mil will cause drastic Yield drop Road Map Internal Lines & Spaces External Lines & Spaces 2011 2012 3 / 4 mil 3/3mil 3.5/4 mil BGA Ball Pitch (Goal) 1.0mm 3 lines 0.8mm 2 lines
1. High Layer Count PCB Technology Drivers 2 18 2-2. Routing Density : Drill to Metal Required : Ball Pitch of BGA & CCGA are smaller design as 0.4 & 0.5mm from 0.8 &1.0mm pitch Required : Routing Density is higher h between pad to pad What is Drill to Metal? Spacing between drill edge to around signal trace Spacing between drill edge to around Anti-pad edge Key Point Using Smallest Drill size as 6~10mil Keep upgrade Registration Capability Prepreg Pattern ThinCore Prepreg Drill Signal D2M 2011 2012 Signal D2M Annular ring + Spacing 9mil 8mil 7mil Plane D2M Anti pad Size 26mil 24mil 22mil 7mil 6mil 2011 2012 22mil 20mil Plane Anti pad D2M
2. High Layer Count PCB Technology Drivers 2 19 2-3. Routing Density : HDI Required : HDI design is required for Line Card to reduce Layer count Layer Count : 14~26 Board Thickness : 2.0~2.8t Micro Via : 127um, 200um Type : 1-2/2-3 Staggered via, 1-3 Skip via Min. Via : 200um Prepreg used for Micro Via holes Staggered Via (1~3L) Buried Via Core (13~14L) Buried Via Hole (2~25L) Key Point Registration within 3mil - PEP, Registration Validation Coupon Plated inner layer yield control Control copper thickness on plated signal layers Laser drilling - Remove smear with normal prepreg Standard glass Spread glass The fixed energy can not Exactly fit the poor area (arrow1) & the glass rich area (arrow2) at the same time
2. High Layer Count PCB Technology Drivers 2 20 2-4.Routing Density : Via in Pad What is VIP? VIP stands for Via In pad and its structure has plugged with via epoxy and topside is capped with plating It was used to increase routing density and attach the Smaller components <BGA Area> Merits Provides a flat coplanar surface Make routing easier and more traces on PCB Increase component density Potential EMI. SI benefits Help thermal management Al lower cost t& risk of soldering problem <PTH Normal> <VIP>
2. High Layer Count PCB Technology Drivers 2 21 2-4. Routing Density : Via in Pad Application : Surface mounting BGA pad Smallest BGA & CCGA design Layer Count : 14~28 Board Thickness : 2.0~3.2t 2t Type : Plugging for Plated and External MicroVia Min. Via : 200um FHS A/R :15:1 Key Point Pull the wire vertically by using a 50kg load at 10 cm / minute Until the pad is peeled off and record the load percentage. Average force of 250 Newtons/Sq.cm [~360 Pounds-force/Sq] S/N1,Condor #3 @20X Magnification S/N1,Condor #4 S/N2,Condor #6 @20X Magnification @20X Magnification
2. High Layer Count PCB Technology Drivers 2 22 2-4. Routing Density : Via In pad Via Plugging -Criterion Failure Mode Air pocket in MVH Non filling in PTH Dimple Planarization Specification Air Pocket Dimple Note Specification Under 5% (Via Hole Dimension) Under 50um Normal None None Stric (Mil/Areo) Higher Aspect ratio but more strict criterion
2. High Layer Count PCB Technology Drivers 2 23 2-5.Routing Density : Via In pad (Paste- Low CTE, High Peel Strength) A B C D V Type Viscosity Pa s/25 35-45 30-40 30-40 35-45 Shelf Life 10 90days 90days 60days 90days 5 Tg (TMA) 0 141 168 160 170 CTE β1 ppm/ 39 39 32 24 Β2 ppm/ 143 105 83 70 25 MPa 7200 5200 8600 8500 Rate of moisture absorption (DMA) 100 5800 4300 6200 6700 150 820 2600 4300 5300 200 340 870 2600 1300 250 280 660 2100 700 Absorptance JISC6481 % 0.23 0.16 0.15 0.15 Dill Size Avg µm 4~5 2~3 2~3 3 Max 22.5 15 17.5 17.5 Pan-Cake % 100 100 100 100 UL 94V-0 94V-0 94V-0 94V-0 Peel Strength g/cm 400 670 900 400 140 30 Curing Condition min 80 10 110 10 150 30 (PCB) 110 60 150 30 (FCPKG) 110 60 150 30 110 60 150 30
3. High Layer Count PCB Technology Drivers 3 24 Core driver 3. High Aspect Ratio Plating in Acid Copper 3-1. High Aspect Ratio Trend & Plating Core driver Trends : Aspect ratio(dhs) which are Conventional boards will be increased about 13:1 in near term. Request : Increasing Layer counts and Routing Density, It is caused for plating capability to enhances high 21:1 18:1 15:1 12:1 9:1 6:1 3:1 0 2012~2016 2010~2011 2008~2009 2006~2007 10:1 Aspect ratio Board Reliability. 11:1 12:1 13:1 2006~2007 2008~2009 2010~2011 2012~2016 IPC International Technologies Roadmap 2006~2007 State of arts boards may have more high aspect ratio (18:1~24:1) - Use RPP and optimize a RPP parameter for thick Plating copper thickness - Consider a material property for preventing plating void (Activation energy are different among raw materials) - Check the metal ion concentration in the plating Tank for better copper property - Consider full build electroless copper plating. It is easy to control plating rate.
3. High Layer Count PCB Technology Drivers 3 25 3-2. Desmear Trends : The low Dk/Df Material construction challenge and the fluidity challenge of high aspect ratio hole - To improve a Signal integrity, generally use low Dk/Df Material - High Aspect ratio drop the fluidity. Request : Because of low Dk/Df Material use and high aspect ratio, Desmear process must be setup for new material. - Consider plasma machine for de-smear, because gas fluidity is better than liquid and Have a better etch rate (Positive etch back). Positive Etch Back 0.24mil - Keep Improve a swelling process for getting a more etch rate and roughness on hole wall - Consider new basket design for better fluidity
3. High Layer Count PCB Technology Drivers 3 26 3-2. Desmear Trends : As required lead free conditions, a raw material of low Dk/Df need a stronger for heat. Based on this requirements of market, low Dk/Df material added a filler construction ction in resin.
3. High Layer Count PCB Technology Drivers 3 27 3-3. Pulse Plating MVH, PTH Cu plating Capability Test Panel Spec. -Nelco4 000-13SI -Layer Count: 28L -Board Thick.:196mil -DHS:10.8mil -MVH:8mil -DHS A/R:17.8:1 Cu plating thickness in PTH (DHS 10.8mil) <Target:1.1mil, min.avg.1.0mil, min:0.8mil> Min:1.02mil, Max:1.32mil, Avg:1.14mil Cu plating thickness in MVH (size:8mil) il) Min:1.46mil, Max:1.78mil, Avg:1.57mil Reliability Thermal Stress (3X,6X) Item Delamination Wicking(mil) Hole Roughness(mil) Nail Head(%) Smear Resin Recession(%) Pull away Copper Crack 3X PTH 3X MVH 6X PTH 6X MVH None None None None 1.52 0.6 1.41 0.76 0.27-0.29-132.4% - 127.8% - None None None None 3.4% - 4.7% - None None None None None None None None
4. High Layer Count PCB Technology Drivers 4 28 Core driver 4. Signal Integrity 4-1. Ultra Low Dk/Df Required : Low Dk/Df material used for High Speed board Signal Attenuation 1Gbps 5Gbps 10Gbps 20Gbps FR-4 Mid Low loss: 0010 0.01-0.015015 Ultra Low loss <001 0.01 Nelco N4000-6 Isola FR406 Panasonic R-1766 Nelco N4000-13 Isola FR408HR Panasonic Megtron4 Nelco N4000-13SI Isola IS620/IS640 Panasonic Megtron6 - Still cost adder - Well defined hole wall process condition for higher Tg/Td mat l - Higher data rate/faster t rise time /Longer lines of large back planes - Propagation delay. Skin effect. P or S parameter also should be taken into consideration
4. High Layer Count PCB Technology Drivers 4 Confidential 29 4-2.Fiber weave effect (Special Glass weave) Required : Traditional Glass weave caused Dk/Df variation instability for a pair transmission on spread out of glass weave. Normal type Non treatment # 1080 Highly spread out Treatment #1078 Key Point Using the high h density of special glass weave Make Dk/Df variation instability. Thickness is thinner because of yarn is spread out The gap is smaller than normal type #106, #1080 => #1067,1078
4. High Layer Count PCB Technology Drivers 4 Confidential 30 4-3.Back Drilling Required : Capacity launches can act as low-pass filter, the effect of which is top rohibit the transmission of high frequencies (Stub Effect) The capacitance and the stub are both reduced Stub Length MNC: Must Not-Cut Layer Key Point Only incremental improvements on the PCB for Signal speed increasing Yield and quality control for single & multiple depth Depth tolerance is changed from ±254um to ±127um Back drilling positioning Depth tolerance is changed from ±254um to ±127um 1~4L 4~26L Back-Drill : Multiple Depth 4~26L Source: Worldwide High-speed Electronics Tech.& Market Trends For the Years 06~16 Short NG: Drill Position error
4. High Layer Count PCB Technology Drivers 4 Confidential 31 4-3-1.Effect of Back Drilling
4. High Layer Count PCB Technology Drivers 4 32 4-4. Buried Capacitance Required : ultra thin core thickness 50um 24um 12um Process : Hi Pot Test : No failure on I/L cores and finished i boards Key Point How to handle while proceed thinner core between inner to press process Control Hi-pot test t conditions Registration lestvi BC 24um Smal a Large Hole Acid Rinse only (Reverse Treated Foil) Incoming Inspection I/L Prep Max. Delay time is 24hr Dry Film Lamination Ultra Flex DES line (1mil Core Compatible line) Imaging with UV Exp. Post Etch Puncher AOI Hi Pot Test For Inner-layer Boards Horizontal Oxide Lamination & Electrical Test Customer Condition Ultra Flex line (1mil Core Compatible line) DES Line (Cupric Acid) Hi Pot Test For Finished Boards Customer Condition
4. High Layer Count PCB Technology Drivers 4 33 4-5.Signal Integrity Simulation Required : Frequency increasing rapidly, problems of reflection, crosstalk, Power and Ground noise are required signal integrity simulation to reduce time and failure cost Signal impedance matching / Critical Net Return Loss Analysis S parameter Via Hole Return Attenuation Optimized Design for Plating thickness improvement 4-6. Electrical Performance Measurement Required : Real SI testing is one of the Hot Issue! Particularly signal loss value at real circuit board Panel edge placed coupon testing is not fully enough Trace Impedance Insertion Loss S21 / Return Loss S11 Conductor Loss db/ Dielectric Loss in db Propagation velocity & Delay/ SPICE Model (RLGC) Crosstalk, Jitter, Eye-Diagram/ Current Distribution Key Point Port1 Port2 Higher accurate single & differential impedance To reduce time and failure cost - Noise of Crosstalk, Reflection, Power/Ground - EMI Issue / Skew control matters - Group Delay / Jitter control S-parameter in frequency domain
Next Page 34 Definition of High Layer Count PCB Core Technology Trends High Layer Count PCB Technology Drivers Interconnection Reliability
5. High Layer Count PCB Technology Drivers 5 35 Coredriver 5. Interconnection Reliability Interconnection Reliability Required: Highest Interconnection Reliability Concern: Conventional Reliability Test Method has long term and Random selection to verify 5-1. Conventional Thermal stress & Cycling Key Point Conventional Reliability Test Method has long term and Random selection to verify - Thermal Stress - Thermal Shock Needs: Want to guarantee Long term Reliability Conventional Reliability Test Method are changed by electrical test method in easy & high reliability such as - IST - CAF
5. High Layer Count PCB Technology Drivers 5 36 5-2. IST IST : Interconnect Stress Test Monitoring variation of resistance value Inside hole wall in real time Barrel Crack ICD s
5. High Layer Count PCB Technology Drivers5 37 5-4. CAF 5-5. C-SAM CAF : Conductive Anodic Filament Monitoring variation of resistance value in real time ( hole to hole, hole to trace, trace to trace, layer to layer) C-SAM : C-mode Scanning Acoustic Microscope Non destructive Internal Inspection for Detecting De-lamination Possible CAF growth Observed between Hole to Trace.
Conclusion 38 Future Challenges High speed serial link electrical packaging challenges due to Increasing data rates Special Impedance Connectors(±7% ~ ±5%) ) Back drilling of vias at the PTH connectors will be challenge Common mode noise due to phase skew between differential pairs and Connectors Predict Fiber weave effect in simulation Simulate Resin content effect Low loss material Vs. Crosstalk Vs. reflection
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