1 / 23 Comparison of topside contact layouts for power dies embedded in PCB ESTC 2016, Grenoble Chenjiang YU 1, Cyril BUTTAY 2, Éric LABOURÉ 1, Vincent BLEY 3, Céline COMBETTES 3, Gilles BRILLAT 3 1 GEEPS, Paris, France 2 Laboratoire Ampère, Lyon, France 3 LAPLACE, Toulouse, France 14/09/16
Outline 2 / 23 Introduction Proposed Embedding Technique Effect of Contact Area/Layout Summary and Conclusion
Outline 3 / 23 Introduction Proposed Embedding Technique Effect of Contact Area/Layout Summary and Conclusion
Advantages of die embedding 4 / 23 The Printed-Circuit-Board technology (PCB) enables: higher interconnect density multi-layer small pitch (down to 25 µm linewidth) Low inductance [1] small size laminated busbar structure batch-processed manufacturing all interconnects are processed at once E. Hoene, Ultra Low Inductance Package for SiC ECPE workshop on power boards, 2012, [1]
Advantages of die embedding 4 / 23 The Printed-Circuit-Board technology (PCB) enables: higher interconnect density multi-layer small pitch (down to 25 µm linewidth) Low inductance [1] small size laminated busbar structure batch-processed manufacturing all interconnects are processed at once E. Hoene, Ultra Low Inductance Package for SiC ECPE workshop on power boards, 2012, [1]
Advantages of die embedding 4 / 23 The Printed-Circuit-Board technology (PCB) enables: higher interconnect density multi-layer small pitch (down to 25 µm linewidth) Low inductance [1] small size laminated busbar structure batch-processed manufacturing all interconnects are processed at once E. Hoene, Ultra Low Inductance Package for SiC ECPE workshop on power boards, 2012, [1]
5 / 23 Literature Review Die embedding in PCB 1 Patents on chip embedding [2] A. Ostmann, Leistungselektronik in der Leiterplatte AT&S Technologieforum, 2013 Very active area in recent years Many applications to high interconnect density Several industrial developments (AT&S, Schweizer, etc.)
Literature Review Die embedding in PCB 2 Low-inductance packaging for SiC [1] I Half bridge module I 0.8 nh loop inductance I Embedding die using stud bumps E. Hoene, Ultra Low Inductance Package for SiC ECPE workshop on power boards, 2012 [1] 6 / 23
Literature Review Die embedding in PCB 2 Low-inductance packaging for SiC [1] I Half bridge module I 0.8 nh loop inductance I Embedding die using stud bumps E. Hoene, Ultra Low Inductance Package for SiC ECPE workshop on power boards, 2012 [1] I Power module development through german project Hi-LEVEL [3] I 10 kw and 50 kw demonstrators I Thick copper or DBC for thermal management http://www.pcdandf.com/pcdesign/index.php/editorial/menu-features/9257-component-packaging-1405 6 / 23
Outline 7 / 23 Introduction Proposed Embedding Technique Effect of Contact Area/Layout Summary and Conclusion
8 / 23 Overview of the process Start with a DBC substrate Die attach (silver sintering) PCB stacking PCB lamination Topside copper etching Laser ablation Copper electroplating
8 / 23 Overview of the process Start with a DBC substrate Die attach (silver sintering) PCB stacking PCB lamination Topside copper etching Laser ablation Copper electroplating
8 / 23 Overview of the process Start with a DBC substrate Die attach (silver sintering) PCB stacking PCB lamination Topside copper etching Laser ablation Copper electroplating
8 / 23 Overview of the process Start with a DBC substrate Die attach (silver sintering) PCB stacking PCB lamination Topside copper etching Laser ablation Copper electroplating
8 / 23 Overview of the process Start with a DBC substrate Die attach (silver sintering) PCB stacking PCB lamination Topside copper etching Laser ablation Copper electroplating
8 / 23 Overview of the process Start with a DBC substrate Die attach (silver sintering) PCB stacking PCB lamination Topside copper etching Laser ablation Copper electroplating
8 / 23 Overview of the process Start with a DBC substrate Die attach (silver sintering) PCB stacking PCB lamination Topside copper etching Laser ablation Copper electroplating
Overview of the process significant points 9 / 23 Backside die attach with silver sintering: The die does not move during assembly Accurate positioning Ablation using a CO 2 laser Very good selectivity (metal layers insensitive to laser light) Use of the copper layer as an alignment mask Prototype-scale equipment used Can manufacture prototypes from 4x4 cm 2 up to 21x28 cm 2 Affordable, useful for process development.
Overview of the process significant points 9 / 23 Backside die attach with silver sintering: The die does not move during assembly Accurate positioning Ablation using a CO 2 laser Very good selectivity (metal layers insensitive to laser light) Use of the copper layer as an alignment mask Prototype-scale equipment used Can manufacture prototypes from 4x4 cm 2 up to 21x28 cm 2 Affordable, useful for process development.
Overview of the process significant points 9 / 23 Backside die attach with silver sintering: The die does not move during assembly Accurate positioning Ablation using a CO 2 laser Very good selectivity (metal layers insensitive to laser light) Use of the copper layer as an alignment mask Prototype-scale equipment used Can manufacture prototypes from 4x4 cm 2 up to 21x28 cm 2 Affordable, useful for process development.
10 / 23 Die Preparation Lab-scale process Standard Al topside Unsuitable Ti/Cu PVD with a shadow mask (50/500 nm) Simple process for singulated dies
Die Preparation Lab-scale process Mask I Standard Al topside Unsuitable I Ti/Cu PVD with a shadow mask (50/500 nm) I Simple process for singulated dies 10 / 23
Die Preparation Lab-scale process Mask Die I Standard Al topside Unsuitable I Ti/Cu PVD with a shadow mask (50/500 nm) I Simple process for singulated dies 10 / 23
Die Preparation Lab-scale process Mask Die PVD I Standard Al topside Unsuitable I Ti/Cu PVD with a shadow mask (50/500 nm) I Simple process for singulated dies 10 / 23
Die Preparation Lab-scale process Mask Die PVD I Standard Al topside Unsuitable I Ti/Cu PVD with a shadow mask (50/500 nm) I Simple process for singulated dies 5 5 mm2 IGBT die 10 / 23
11 / 23 Cross section Vertical walls in epoxy layers Good self-alignment No degradation of die topside metal due to CO 2 laser Die contact not yet perfect
Outline 12 / 23 Introduction Proposed Embedding Technique Effect of Contact Area/Layout Summary and Conclusion
Effect of Contact Area/Layout 13 / 23 R Topside copper Wells Die opper foil Electroplated copper Thick topside copper foil (35 µm) Thin electroplated copper (10 µm) Many wells: More copper section on walls Large well(s): Thicker die contact metallization reduction of topside copper section Die fiber-resin composite Die topside métallization
Effect of Contact Area/Layout 13 / 23 R Topside copper Wells Die opper foil Electroplated copper Thick topside copper foil (35 µm) Thin electroplated copper (10 µm) Many wells: More copper section on walls Large well(s): Thicker die contact metallization reduction of topside copper section Die fiber-resin composite Die topside métallization
Effect of Contact Area/Layout 13 / 23 R Topside copper Wells Die opper foil Electroplated copper Thick topside copper foil (35 µm) Thin electroplated copper (10 µm) Many wells: More copper section on walls Large well(s): Thicker die contact metallization reduction of topside copper section Die fiber-resin composite Die topside métallization
14 / 23 Modelling R access R Topside copper Wells R top R wall Die R cont R Al V in R die Structure divided into 100 100µm cells 2-D current flow assumed Generation of a meshed circuit of resistors Solving using Modified Nodal Analysis.
Modelling Results 15 / 23 1 mm 2 4 mm 2 9 mm 2 16 mm 2 4 mm 2 9 mm 2 9 mm 2 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Voltage [V]
16 / 23 Modelling Results (2) # of Surface Resistance contacts (mm 2 ) (mω) 1 1 3.80 1 4 2.16 1 9 1.55 1 16 1.32 4 4 1.40 4 9 1.26 9 9 1.13 Resistance decreases with: Contact area Contact distribution Well spread contacts are more efficient split 4 mm 2 contact comparable to single 16 mm 2
17 / 23 Experimental Validation Test Vehicles 6 6 mm 2 diodes embedded in PCB 4-point connexions for accurate resistance measurement high current (up to 100 A), pulsed measurement
18 / 23 Experimental Validation Test Results Current [A] 100 80 60 40 20 1 mm² contact 4 mm² contact 9 mm² contact 16 mm² contact 4. 83mΩ 5. 43mΩ 6. 62mΩ 13. 60mΩ 0 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Voltage [V] # of Surface Resistance contacts (mm 2 ) (mω) 1 1 16.5 1 4 5.6 1 9 4.9 1 16 4.7 4 4 5.4 4 9 4.4 9 9 5.2 Resistance value extracted from I(V) characteristic of diode Large scattering of experimental data (±20%) Same die in standard TO-247 package: 4.4 mω
Contact Resistance conclusions 19 / 23 Contact distribution is important, contact area not so much Experimental results show same trend as simulation Resistance 4 times higher! Poor quality of die/electroplated copper interface Model also probably too optimistic (diode modelled as a resistance) Resistance equivalent to that of (commercial) wirebonded dies
Contact Resistance conclusions 19 / 23 Contact distribution is important, contact area not so much Experimental results show same trend as simulation Resistance 4 times higher! Poor quality of die/electroplated copper interface Model also probably too optimistic (diode modelled as a resistance) Resistance equivalent to that of (commercial) wirebonded dies
Contact Resistance conclusions 19 / 23 Contact distribution is important, contact area not so much Experimental results show same trend as simulation Resistance 4 times higher! Poor quality of die/electroplated copper interface Model also probably too optimistic (diode modelled as a resistance) Resistance equivalent to that of (commercial) wirebonded dies
Contact Resistance conclusions 19 / 23 Contact distribution is important, contact area not so much Experimental results show same trend as simulation Resistance 4 times higher! Poor quality of die/electroplated copper interface Model also probably too optimistic (diode modelled as a resistance) Resistance equivalent to that of (commercial) wirebonded dies
Outline 20 / 23 Introduction Proposed Embedding Technique Effect of Contact Area/Layout Summary and Conclusion
Summary and Conclusion 21 / 23 Embedding of power devices Custom design at die level Attractive for fast, wide-bandgap devices Contact layout allows for better current spreading Simple process Lab-scale process presented Low contact resistance achieved Main issue: die topside finish Developments to come: Half-bridge with gate drivers Embedding of passive components Work on thermal design
Summary and Conclusion 21 / 23 Embedding of power devices Custom design at die level Attractive for fast, wide-bandgap devices Contact layout allows for better current spreading Simple process Lab-scale process presented Low contact resistance achieved Main issue: die topside finish Developments to come: Half-bridge with gate drivers Embedding of passive components Work on thermal design
Summary and Conclusion 21 / 23 Embedding of power devices Custom design at die level Attractive for fast, wide-bandgap devices Contact layout allows for better current spreading Simple process Lab-scale process presented Low contact resistance achieved Main issue: die topside finish Developments to come: Half-bridge with gate drivers Embedding of passive components Work on thermal design
Bibliography I 22 / 23 E. Hoene, Ultra Low Inductance Package for SiC, in ECPE workshop on power boards, ECPE, 2012. A. Ostmann, Leistungselektronik in der Leiterplatte, in AT&S Technologieforum, 2013. A. Ostmann, L. Boettcher, D. Manessis, S. Karaszkiewicz, and K.-D. Lang, Power modules with embedded components, in Microelectronics Packaging Conference (EMPC), 2013 European, pp. 1 4, Sept. 2013.
23 / 23 Thank you for your attention contact: cyril.buttay@insa-lyon.fr This work was funded by the French National Research Agency (ANR) under the grant name ETHAER.