Introduction to CMOS VLSI Design Lecture 1A: Manufacturing& Layout David Harris Harvey Mudd College Spring 2004 Steven Levitan Fall 2008 1
The Manufacturing Process For a great tour through the IC manufacturing process and its different steps, check http://www.fullman.com/semiconductors/semiconductors.html 2 Digital EE141 Integrated Circuits 2nd Manufacturing 2
CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process Slide 3 3
Photo-Lithographic Process oxidation optical mask photoresist removal (ashing) photoresist coating stepper exposure process step Typical operations in a single photolithographic cycle (from [Fullman]). spin, rinse, dry acid etch photoresist development 4 Digital EE141 Integrated Circuits 2nd Manufacturing 4
CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers 5 Digital EE141 Integrated Circuits 2nd Manufacturing 5
Patterning of SiO2 Si-substrate (a) Silicon base material Si-substrate (b) After oxidation and deposition of negative photoresist Si-substrate (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist Si-substrate Si-substrate Si-substrate Hardened resist SiO 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching Chemical or plasma etch Hardened resist SiO 2 SiO 2 (f) Final result after removal of resist 6 Digital EE141 Integrated Circuits 2nd Manufacturing 6
N Well Process 7 Digital EE141 Integrated Circuits 2nd Manufacturing Copyright 2005 Pearson Addison-Wesley. All rights reserved. 7
Well and Substrate Taps Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps A GND Y V DD p+ n+ n+ p+ p+ n+ p substrate n well substrate tap well tap Slide 8 8
Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line A Y GND V DD substrate tap nmos transistor pmos transistor well tap Slide 9 9
Detailed Mask Views Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal n well Polysilicon n+ Diffusion p+ Diffusion Contact Metal Slide 10 10
11 Digital EE141 Integrated Circuits 2nd Manufacturing Copyright 2005 Pearson Addison-Wesley. All rights reserved. 11
Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO 2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO 2 p substrate Slide 12 12
Oxidation Grow SiO 2 on top of Si wafer 900 1200 C with H 2 O or O 2 in oxidation furnace SiO 2 p substrate Slide 13 13
Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light Photoresist SiO 2 p substrate Slide 14 14
Lithography Expose photoresist through n-well mask Strip off exposed photoresist Photoresist SiO 2 p substrate Slide 15 15
Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed Photoresist SiO 2 p substrate Slide 16 16
Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn t melt in next step SiO 2 p substrate Slide 17 17
n-well n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO 2, only enter exposed Si SiO 2 n well Slide 18 18
Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps p substrate n well Slide 19 19
Self Aligned Gate: Poly masks the channel 20 Digital EE141 Integrated Circuits 2nd Manufacturing Copyright 2005 Pearson Addison-Wesley. All rights reserved. 20
Polysilicon Deposit very thin layer of gate oxide < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH 4 ) Forms many small crystals called polysilicon Heavily doped to be good conductor Polysilicon Thin gate oxide p substrate n well Slide 21 21
Polysilicon Patterning Use same lithography process to pattern polysilicon Polysilicon Polysilicon Thin gate oxide p substrate n well Slide 22 22
Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nmos source, drain, and n-well contact p substrate n well Slide 23 23
N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn t melt during later processing n+ Diffusion p substrate n well Slide 24 24
N-diffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusion n+ n+ n+ p substrate n well Slide 25 25
N-diffusion cont. Strip off oxide to complete patterning step n+ n+ n+ p substrate n well Slide 26 26
P substrate contact N well contact 27 Digital EE141 Integrated Circuits 2nd Manufacturing Copyright 2005 Pearson Addison-Wesley. All rights reserved. 27
P-Diffusion Similar set of steps form p+ diffusion regions for pmos source and drain and substrate contact p+ Diffusion p+ n+ n+ p+ p+ n+ p substrate n well Slide 28 28
Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed Contact p+ n+ n+ p+ p+ n+ Thick field oxide p substrate n well Slide 29 29
Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires Metal p+ n+ n+ p+ p+ n+ Metal Thick field oxide p substrate n well Slide 30 30
CMOS Process Walk-Through Al (j) After deposition and patterning of first Al layer. Al SiO 2 (k) After deposition of SiO 2 insulator, etching of via s, deposition and patterning of second layer of Al. 31 Digital EE141 Integrated Circuits 2nd Manufacturing 31
Advanced Metallization 32 Digital EE141 Integrated Circuits 2nd Manufacturing 32
Advanced Metallization 33 Digital EE141 Integrated Circuits 2nd Manufacturing 33
Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of λ = f/2 E.g. λ = 0.3 μm in 0.6 μm process Slide 34 34
Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules) Rules from Manufacturing process (antenna rules) Final result (shorts/opens) Could be Electrical maximum current Mechanical surface planarity Thermal - overheating Optical mask requirements Characterization only some size transistors well characterized Rules used to be 3 pages, now a book, soon worse 35 Digital EE141 Integrated Circuits 2nd Manufacturing 35
Simplified Design Rules Conservative rules to get you started Slide 36 36
Inverter Layout Transistor dimensions specified as Width / Length Minimum size is 4λ / 2λ, sometimes called 1 unit In f = 0.6 μm process, this is 1.2 μm wide, 0.6 μm long Slide 37 37
CMOS Process Layers Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation 38 Digital EE141 Integrated Circuits 2nd Manufacturing 38
Layers in 0.25 μm m CMOS process 39 Digital EE141 Integrated Circuits 2nd Manufacturing 39
Intra-Layer Design Rules Same Potential Different Potential Well 10 0 or 6 9 Polysilicon 2 2 Active Select 3 3 2 Contact or Via Hole 2 2 Metal1 Metal2 3 3 4 Minimum size, spacing rules 3 40 Digital EE141 Integrated Circuits 2nd Manufacturing 40
Transistor Layout (inter layer rules) Transistor 1 3 2 5 41 Digital EE141 Integrated Circuits 2nd Manufacturing 41
Vias and Contacts 2 1 Via 1 4 5 Metal to Active Contact 1 Metal to Poly Contact 3 2 2 2 42 Digital EE141 Integrated Circuits 2nd Manufacturing 42
Select Layer substrate contact 3 2 well contact Select 2 1 3 3 2 5 Substrate Well 43 Digital EE141 Integrated Circuits 2nd Manufacturing 43
CMOS Inverter Layout P substrate contact GND In V DD N well contact A A Out (a) Layout A A n p-substrate Field n + p + Oxide P substrate contact (b) Cross-Section along A-A N well contact 44 Digital EE141 Integrated Circuits 2nd Manufacturing 44
Layout Editor (what is missing?) 45 Digital EE141 Integrated Circuits 2nd Manufacturing 45
Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um. 46 Digital EE141 Integrated Circuits 2nd Manufacturing 46
Sticks Diagram V DD 3 In 1 Out Dimensionless layout entities Only topology is important Final layout generated by compaction program GND Stick diagram of inverter 47 Digital EE141 Integrated Circuits 2nd Manufacturing 47
Gate Layout Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology V DD and GND should abut (standard height) Adjacent gates should satisfy design rules nmos at bottom and pmos at top All gates include well and substrate contacts Slide 48 48
Example: Inverter Slide 49 49
Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 V DD rail at top Metal1 GND rail at bottom 32 λ by 40 λ Slide 50 50
Stick Diagrams Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers Slide 51 51
Wiring Tracks A wiring track is the space required for a wire 4 λ width, 4 λ spacing from neighbor = 8 λ pitch Transistors also consume one wiring track Slide 52 52
Well spacing Wells must surround transistors by 6 λ Implies 12 λ between opposite transistor flavors Leaves room for one wire track Slide 53 53
Area Estimation Estimate area by counting wiring tracks Multiply by 8 to express in λ Slide 54 54
Example: O3AI Sketch a stick diagram for O3AI and estimate area Y = ( A+ B+ C) D Slide 55 55
Example: O3AI Sketch a stick diagram for O3AI and estimate area Y = ( A+ B+ C) D Slide 56 56
Example: O3AI Sketch a stick diagram for O3AI and estimate area Y = ( A+ B+ C) D Slide 57 57