VLSI PROCESS TECHNOLOGY y ER. HIMNSHU SHRM
Fabrication Masks Chips Wafers Processing Processed Wafer
Traditional CMOS Process
Modern CMOS Process Dual-Well Trench-Isolated CMOS gate oxide field oxide l (Cu) TiSi 2 SiO 2 tungsten n+ p well p-epi p- n well p+ SiO 2 Epi-layer is a high quality crystal grown on the polished surface of pre-doped silicon wafers for making CMOS nano devices.
Photo-Lithographic Process oxidation optical mask photoresist removal (ashing) photoresist coating stepper exposure process step Typical operations in a single photolithographic cycle (from [Fullman]). spin, rinse, dry acid etch photoresist development
Growing the Silicon Ingot From Smithsonian, 2000
E-eam Lithography s the miniaturization of IC devices continues, electron beam exposure technology is gaining prominence as a technology for nextgeneration design rules From: DVNTEST CORPORTION
Silicon Oxidation The oxide is grown by exposing the silicon surface to high temperature steam. s the oxide grows, the silicon is consumed. The arrows represent the direction of motion of each surface of the oxide. Underneath the nitride mask, the growth is suppressed, and these areas will become the active transistor area. Source: ell Laboratories
Patterning - Photolithography 1. Oxidation 2. Photoresist (PR) coating 3. Stepper exposure SiO 2 4. Photoresist development and bake 5. cid etching Unexposed (negative PR) Exposed (positive PR) 6. Spin, rinse, and dry 7. Processing step Ion implantation Plasma etching Metal deposition 8. Photoresist removal (ashing) mask UV light PR
CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers One full photolithography sequence per layer (mask) uilt (roughly) from the bottom up 5 metal 2 4 metal 1 2 polysilicon 3 source and drain diffusions 1 tubs (aka wells, active areas) exception!
Example of Patterning of SiO2 Si-substrate Silicon base material Si-substrate 1&2. fter oxidation and deposition of negative photoresist Si-substrate 3. Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist Si-substrate Si-substrate 5. fter etching Si-substrate 8. Final result after removal of resist Chemical or plasma etch Hardened resist SiO 2 4. fter development and etching of resist, chemical or plasma etch of SiO 2 Hardened resist SiO 2 SiO 2
Diffusion and Ion Implantation 1. rea to be doped is exposed (photolithography) 2. Diffusion or Ion implantation
Ion Implantation 1. Dopant atoms are ionized and then accelerated by an electric field until they impinge on the silicon surface, where they embed themselves. 2. polysilicon line crosses the active area in the upper left and forms the gate of a transistor. Source: ell Laboratories
Deposition and Etching 1. Pattern masking (photolithography) 2. Deposit material over entire wafer CVD (Si 3 N 4 ) chemical deposition (polysilicon) sputtering (l) 3. Etch away unwanted material wet etching dry (plasma) etching
Metallization 1. First an insulating glass layer is deposited to cover the silicon, then contact holes are cut into the glass layer down to the silicon. 2. Metal is deposited on top of the glass, connecting to the devices through the contact holes. 3. The graphic shows a snapshot during the filling of a contact hole with aluminum. Source: ell Laboratories
F5112 E-eam Lithography Single-Column System Minimum Feature Size: 100nm Overlay ccuracy: mean +3 sigma<=40nm 3 sigma<=15nm lock Exposure Method: Max. No. of lock Patterns: 70
Planarization: Polishing the Wafers From Smithsonian, 2000
Self-ligned Gates 1. Create thin oxide in the active regions, thick elsewhere 2. Deposit polysilicon 3. Etch thin oxide from active region (poly acts as a mask for the diffusion) 4. Implant dopant
Simplified CMOS Inverter P-well Process cut line p well
P-Well Mask
ctive Mask
Poly Mask
P+ Select Mask
N+ Select Mask
Contact Mask
Metal Mask
VLSI Fabrication: The Cycle
CMOS N-well Process (cont d) The n-well CMOS process starts with a moderately doped (impurity concentration less than 10 15 cm -3 ) p-type silicon substrate. Then, an oxide layer is grown on the entire surface. The first lithographic mask defines the n-well region. Donor atoms, usually phosphorus, are implanted through this window in the oxide. This defines, the active areas of the nmos and pmos transistors. Thin gate oxide is grown on top of the active regions. The thickness and the quality of the gate oxide are critical fabrication parameters, since they affect the characteristics of the MOS transistor, and its reliability.
CMOS N-well Process (cont d) The polysilicon layer is deposited using chemical vapor deposition (CVD) and patterned by dry (plasma) etching. The created polysilicon lines will function as the gate electrodes of the nmos and the pmos transistors and their interconnects. lso, the polysilicon gates act as self-aligned masks for the source and drain implantations that follow this step.
CMOS N-well Process (cont d) Using a set of two masks, the n+ and p+ regions are implanted into the substrate and into the n- well, respectively. The ohmic contacts to the substrate and to the n-well are implanted in this process step.
CMOS N-well Process (cont d) n insulating silicon dioxide layer is deposited over the entire wafer using CVD. Then, the contacts are defined and etched away to expose the silicon or polysilicon contact windows.
CMOS N-well Process (cont d) Metal is deposited over the entire chip surface using metal evaporation, and the metal lines are patterned through etching. Since the wafer surface is nonplanar, the quality and the integrity of the metal lines created in this step are very critical and are essential for circuit reliability.
CMOS N-well Process (cont d) The composite layout and the resulting cross-sectional view of the chip, showing one nmos and one pmos transistor (builtin n-well), the polysilicon and metal interconnections. The final step is to deposit the passivation layer (overglass - for protection) over the chip, except for wire-bonding pad areas.
dvanced Metallization
From Design to Reality
Design Rules
CMOS Process Layers Layer Well (p,n) ctive rea (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red lue Magenta lack lack lack Representation
Layers in 0.25 mm CMOS process
Design Rules Interface between the circuit designer and process engineer Guidelines for constructing process masks Unit dimension: minimum line width» scalable design rules: lambda parameter» absolute dimensions: micron rules Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur complete set includes» set of layers» intra-layer: relations between objects in the same layer» inter-layer: relations between objects on different layers
3D Perspective Polysilicon luminum
Why Have Design Rules? To be able to tolerate some level of fabrication errors such as 1. Mask misalignment 2. Dust 3. Process parameters (e.g., lateral diffusion) 4. Rough surfaces
Intra-Layer Design Rule Origins Minimum dimensions (e.g., widths) of objects on each layer to maintain that object after fab» minimum line width is set by the resolution of the patterning process (photolithography) Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab 0.3 micron 0.15 0.15 0.3 micron
Inter-Layer Design Rule Origins 1. Transistor rules transistor formed by overlap of active and poly layers Transistors Catastrophic error Unrelated Poly & Diffusion Thinner diffusion, but still working
Inter-Layer Design Rule Origins, Con t 2. Contact and via rules M1 contact to p-diffusion M1 contact to n-diffusion M1 contact to poly Mx contact to My Contact Mask Via Masks both materials 0.3 Contact: 0.44 x 0.44 mask misaligned 0.14
Intra-Layer Design Rules Same Potential Different Potential Well 10 0 or 6 9 Polysilicon 2 2 ctive Select 3 3 2 Contact or Via Hole 2 2 Metal1 Metal2 3 3 4 3
Transistor Layout Transistor 1 3 2 5
Vias and Contacts 2 1 Via 1 4 5 Metal to ctive Contact 1 Metal to Poly Contact 3 2 2 2
Select Layer 3 2 2 Select 1 3 3 2 5 Substrate Well
IC Layout
CMOS Inverter Sticks Diagram V DD 3 In 1 Out Dimensionless layout entities Only topology is important Final layout generated by compaction program GND Stick diagram of inverter
CMOS Inverter max Layout metal1 metal2 Out In metal1-poly via polysilicon V DD pfet pdif metal1-diff via GND PMOS (4/.24 = 16/1) NMOS (2/.24 = 8/1) ndif nfet metal2-metal1 via
Layout Editor
Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um.
CMOS Inverters PMOS V DD In Out 1.2 mm =2l Metal1 Polysilicon NMOS GND
Layout Design Rule Violation Well-well spacing = 9 M1width = 4 M1- M1 spacing = 3 ctive to well edge = 5 Min active width = 3 Poly overlap of active = 2 M2 - M2 spacing = 4 ll distances in l
uilding an Inverter Step 1 Step 2 Step 3 Step 4 VCC P VCC Output P diffusion N diffusion Output N VSS Output VSS With permission of William radbury
uilding a 2 Input NOR Gate Out P Output Shared node P N N Step 1 Step 3 O u t p u t O u t p u t S h a r e d n o d e V S S V C C V S S Step 2 P N Step 4 V S S O u t p u t V C C With permission of William radbury
uilding a 2 Input NND Gate With permission of William radbury Step 1 Step 3 O u t p u t O u t p u t S h a r e d n o d e V S S V C C V S S Step 2 P N Step 4 V S S O u t p u t V C C Shared node Output P P N N Out
Combining Logic Functions Out VCC VCC VCC P P Out Out N Out VSS VSS N VSS With permission of William radbury
Cell Symbol to Logic to Transistor Schematic to Layout LD LD SRM IT TRNSISTOR SCHEMTIC INPUT SRM OUTPUT INPUT LD P2, 1.8 P4, 2.0 OUTPUT P1, 1.4 N1, 1.4 LD N2, 2.0 N4, 2.0 SRM IT LOGIC P3,.5/1.0 INPUT LD P 1.8 N 2.0 OUTPUT N3,.6/1.0 P 1.4 N 1.4 LD P 2.0 N 2.0 P.5/1.0 N.6/1.0 Minimum poly width L = 0.20 Note the listing of the L dimension which is not the minimum defined by the process With permission of William radbury
Schematic to Transistor LD OUTPUT P1 INPUT P2 VCC P4 VCC N1 INPUT N2 OUTPUT VSS N4 VSS LD N3 VSS P3 VCC With permission of William radbury
ssembling the Transistors by Type and Node Name INPUT LD VCC OUTPUT VCC VC C INPUT VSS OUTPUT LD VSS VSS With permission of William radbury
Connecting the Nodes INPUT LD VCC OUTPUT VCC VC C INPUT VSS OUTPUT LD VSS VSS With permission of William radbury
Connecting the Dotes VC C I N P U T LD V C C V C C O U T P U T UNMERGED DT: INPUT Notice the addition of contacts where necessary and also the use of redundant contacts to improve reliability I N P U T LD V S S VSS V SS O U T P U T With permission of William radbury
Cleaning Connections and Completing the layout. dded: 1.Taps 2.Implants 3.Cell boundry N-WELL P-IMPLNT LD DD IN P U T P1 P 3 P2 V C C V C C VC C P4 N-TP O U T P U T INPUT IN PU T LD N-IMPLNT VS S VS S VS S N1 N3 N4 N2 OUTPUT OU TP UT With permission of William radbury P-TP
. Using sticks VCC Metal1 P diffusion Output N diffusion Poly Contact VSS With permission of William radbury
Same cell, different shape. VCC VCC Output VCC VCC Out VSS Out VSS VSS With permission of William radbury
Cells Designed for Sharing. Sense Ckt. for One Row Memory Row 1 Reference Voltage Compare Row 1 Height of 1 Memory it 1 it 1 it Dual Sense mp Cell Height Memory Row 1 Reference Voltage Compare Row 1 Compare Row 2 Reference Voltage Memory Row 2 1 it 1 it Dual Sense mps Dual Write Line Ckts Courtesy Mentor Graphics Corp. Layout created using IC-Station. With permission of William radbury
Cells Designed for Sharing. With permission of William radbury
Packaging
Packaging Requirements Desired package properties Electrical: Low parasitics Mechanical: Reliable and robust Thermal: Efficient heat removal Economical: Cheap Wire bonding Only periphery of chip available for IO connections Mechanical bonding of one pin at a time (sequential) Cooling from back of chip High inductance (~1nH) More about packaging: http://www.embeddedlinks.com/chipdir/package.htm
Chip to package connection Flip-chip Whole chip area available for IO connections utomatic alignment One step process (parallel) Cooling via balls (front) and back if required Thermal matching between chip and substrate required Low inductance (~0.1nH)
onding Techniques Wire onding Substrate Die Pad Lead Frame
Tape-utomated onding (T) Sprocket hole Film + Pattern Solder ump Test pads Die Lead frame Substrate (b) Die attachment using solder bumps. (a) Polymer Tape with imprinted wiring pattern. Polymer film
New package types G (all Grid rray) Small solder balls to connect to board small High pin count Cheap Low inductance CSP (Chip scale Packaging) Similar to G Very small packages Package inductance: 1-5 nh
Flip-Chip onding Die Solder bumps Interconnect layers Substrate
Package-to-oard Interconnect (a) Through-Hole Mounting (b) Surface Mount
Package Types Through-hole vs. surface mount From dnan ziz http://www.ece.utexas.edu/~adnan/vlsi-05/
Chip-to-Package onding Traditionally, chip is surrounded by pad frame» Metal pads on 100 200 mm pitch» Gold bond wires attach pads to package» Lead frame distributes signals in package» Metal heat spreader helps with cooling From dnan ziz http://www.ece.utexas.edu/~adnan/vlsi-05/
dvanced Packages ond wires contribute parasitic inductance Fancy packages have many signal, power layers» Like tiny printed circuit boards Flip-chip places connections across surface of die rather than around periphery» Top level metal pads covered with solder balls» Chip flips upside down» Carefully aligned to package (done blind!)» Heated to melt balls» lso called C4 (Controlled Collapse Chip Connection) From dnan ziz http://www.ece.utexas.edu/~adnan/vlsi-05/
Signal Pads Signal Pins Package Parasitics Use many V DD, GND in parallel» Inductance, I DD Package Chip V DD ond Wire Lead Frame oard V DD Chip Package Capacitor Chip GND oard GND From dnan ziz http://www.ece.utexas.edu/~adnan/vlsi-05/
Signal Interface Transfer of IC signals to PC» Package inductance.» PC wire capacitance.» L - C resonator circuit generating oscillations.» Transmission line effects may generate reflections» Cross-talk via mutual inductance L-C Oscillation Chip L PC trace Z f =1/(2p(LC) 1/2 ) L = 10 nh C = 10 pf f = ~500MHz C R Transmission line reflections Package
Package Parameters
Package Parameters
Package Parameters 2000 Summary of Intel s Package I/O Lead Electrical Parasitics for Multilayer Packages
Packaging Faults Small all Chip Scale Packages (CSP) Open
Packaging Faults CSP ssembly on 6 mil Via in 12 mil pad Void over via structure
Miniaturisation of Electronic Systems Enabling Technologies :»SOC»High Density Interconnection technologies SIP System-in-a-package From ECE 407/507 University of rizona http://www.ece.arizona.edu/mailman/listinfo/ece407
The Interconnection gap Improvement in density of standard interconnection and packaging technologies is much slower than the IC trends PC scaling dvanced PC Laser via IC scaling Interconnect Gap Time From ECE 407/507 University of rizona http://www.ece.arizona.edu/mailman/listinfo/ece407
The Interconnection gap Requires new high density Interconnect technologies PC scaling dvanced PC IC scaling Thin film lithography based Interconnect technology Reduced Gap Time From ECE 407/507 University of rizona http://www.ece.arizona.edu/mailman/listinfo/ece407
SoC has to overcome» Technical Challenges: Increased System Complexity. Integration of heterogeneous IC technologies. Lack of design and test methodologies.» usiness Challenges:» Solution Long Design and test cycles High risk investment Hence time to market. System-in-a-Package From ECE 407/507 University of rizona http://www.ece.arizona.edu/mailman/listinfo/ece407
Multi-Chip Modules
Multiple Chip Module (MCM) Increase integration level of system (smaller size) Decrease loading of external signals > higher performance No packaging of individual chips Problems with known good die:» Single chip fault coverage: 95%» MCM yield with 10 chips: (0.95) 10 = 60% Problems with cooling Still expensive
Complete PC in MCM