Chapter 2 Crystal Growth and Wafer Preparation

Similar documents
Physics and Material Science of Semiconductor Nanostructures

EE CRYSTAL GROWTH, WAFER FABRICATION AND BASIC PROPERTIES OF Si WAFERS- Chapter 3. Crystal Structure z a

Lecture 2 Silicon Properties and Growth

PY2N20 Material Properties and Phase Diagrams

CRYSTAL GROWTH, WAFER FABRICATION AND BASIC PROPERTIES OF Si WAFERS- Chapter 3. Crystal Structure z a

Crystal Growth and Wafer Fabrication. K.Sivasankaran, Assistant Professor (Senior), VLSI Division, School of Electronics Engineering, VIT

Fabrication Technology

The lowest quality of silicon is the so- called metallurgical silicon. The source material of making metallurgical silicon is quartzite.

KOREA UNIVERSITY. Ch. 4 Basics of device fabrication Reference: S. M. Sze, Semiconductor Devices, ISBN Photonics Laboratory

From sand to silicon wafer

Section 4: Thermal Oxidation. Jaeger Chapter 3. EE143 - Ali Javey

VLSI Digital Systems Design

Defects and crystal growth

CHAPTER 4: Oxidation. Chapter 4 1. Oxidation of silicon is an important process in VLSI. The typical roles of SiO 2 are:

Silicon VLSI Technology. Fundamentals, Practice and Modeling

Microelettronica. Planar Technology for Silicon Integrated Circuits Fabrication. 26/02/2017 A. Neviani - Microelettronica

Fabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB

Section 4: Thermal Oxidation. Jaeger Chapter 3

CL 240: Materials Technology

LANDOLT-BÖRNSTEIN. Zahlenwerte und Funktionen aus Naturwissenschaften und Technik. Neue Serie. Gesamtherausgabe: K.-H. Hellwege O.

The Physical Structure (NMOS)

Silicon for Wafer production

VLSI Technology. By: Ajay Kumar Gautam

Chapter 3 CMOS processing technology

Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation.

Agenda o Semiconductor Materials o Crystal Growth o Intrinsic Semiconductors o Extrinsic Semiconductors

Ajay Kumar Gautam [VLSI TECHNOLOGY] VLSI Technology for 3RD Year ECE/EEE Uttarakhand Technical University

Silicon Wafers: Basic unit Silicon Wafers Basic processing unit 100, 150, 200, 300, 450 mm disk, mm thick Current industrial standard 300 mm

Materials: Structures and Synthesis

Crystalline Silicon Solar Cells

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing

Monocrystalline Silicon Wafer Specification (Off-spec)

SiC crystal growth from vapor

CHAPTER 8: Diffusion. Chapter 8

How to Make Micro/Nano Devices?

Monocrystalline Silicon Wafer Specification (Off-spec)

Microstructure of Electronic Materials. Amorphous materials. Single-Crystal Material. Professor N Cheung, U.C. Berkeley

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras

HOMEWORK 4 and 5. March 15, Homework is due on Monday March 30, 2009 in Class. Answer the following questions from the Course Textbook:

Imperfections, Defects and Diffusion

Czochralski Crystal Growth

Doping and Oxidation

Learning Objectives. Chapter Outline. Solidification of Metals. Solidification of Metals

Fused-Salt Electrodeposition of Thin-Layer Silicon

Silicon Manufacturing

Solar Photovoltaic Technologies

Chapter Outline Dislocations and Strengthening Mechanisms. Introduction

Chapter 7 Dislocations and Strengthening Mechanisms. Dr. Feras Fraige

Instructor: Dr. M. Razaghi. Silicon Oxidation

Dept.of BME Materials Science Dr.Jenan S.Kashan 1st semester 2nd level. Imperfections in Solids

CHAPTER - 4 CMOS PROCESSING TECHNOLOGY

Basics of Solar Photovoltaics. Photovoltaics (PV) Lecture-21

AN ABSTRACT OF THE THESIS OF. Peter M. Burke. defects in epitaxial silicon wafers were investigated. Low temperature

Silver Diffusion Bonding and Layer Transfer of Lithium Niobate to Silicon

Solid. Imperfection in solids. Examples of Imperfections #2. Examples of Imperfections #1. Solid

Chapter 2 MOS Fabrication Technology

Contents. Abbreviations and Symbols... 1 Introduction... 1

Photovoltaics: BASICS

Chapter Outline How do atoms arrange themselves to form solids?

Lab IV: Electrical Properties

Chapter 5 Epitaxial Growth of Si 1-y C y Alloys

CHAPTER INTRODUCTION

Chapter Outline. How do atoms arrange themselves to form solids?

Defects and Diffusion

MATERIALS. Silicon Wafers... J 04 J 01. MATERIALS / Inorganics & thin films guide

CHAPTER 3 SELECTION AND PROCESSING OF THE SPECIMEN MATERIAL

CHAPTER 5 IMPERFECTIONS IN SOLIDS PROBLEM SOLUTIONS

Chapter 4: Imperfections (Defects) in Solids

EE 5611 Introduction to Microelectronic Technologies Fall Tuesday, September 02, 2014 Lecture 01

Processing of Semiconducting Materials Prof. Pallab Banerjee Department of Material Science Indian Institute of Technology, Kharagpur

Structural changes of polycrystalline silicon layers during high temperature annealing

A great many properties of crystals are determined by imperfections.

3. Solidification & Crystalline Imperfections

Imperfections: Good or Bad? Structural imperfections (defects) Compositional imperfections (impurities)

PDS Products PRODUCT DATA SHEET. BN-975 Wafers. Low Defect Boron Diffusion Systems. Features/Benefits BORON NITRIDE

INTEGRATED-CIRCUIT TECHNOLOGY

Module 29. Precipitation from solid solution I. Lecture 29. Precipitation from solid solution I

1. Introduction. What is implantation? Advantages

EE 5611 Introduction to Microelectronic Technologies Fall Tuesday, September 04, 2012 Lecture 01

Structural Scheme of Information System for Defect Engineering of Dislocation-free Silicon Single Crystals

Semiconductor device fabrication

A discussion of crystal growth, lithography, etching, doping, and device structures is presented in

Fabrication and Layout

Point Defects. Vacancies are the most important form. Vacancies Self-interstitials

EE 143 FINAL EXAM NAME C. Nguyen May 10, Signature:

Comparative studies of EFG poly-si grown by different procedures

ELEC 7364 Lecture Notes Summer Si Oxidation. by STELLA W. PANG. from The University of Michigan, Ann Arbor, MI, USA

SPI Supplies Brand MgO Magnesium Oxide Single Crystal Substrates, Blocks, and Optical Components

Materials Science and Engineering: An Introduction

Chapter 5. UEEP2613 Microelectronic Fabrication. Diffusion

INFLUENCE OF PREANNEALING ON PERFECTION OF CZOCHRALSKI GROWN SILICON CRYSTALS SUBJECTED TO HIGH PRESSURE TREATMENT

MICROSTRUCTURE AND PROPERTIES OD RAPID SOLIDIFIED AL-SI-FE AND AL-SI-FE-CR ALLOYS PREPARED BY CENTRIFUGAL ATOMIZATION. Filip PRŮŠA*, Dalibor VOJTĚCH

FABRICATION ENGINEERING MICRO- NANOSCALE ATTHE AND. Fourth Edition STEPHEN A. CAMPBELL. of Minnesota. University OXFORD UNIVERSITY PRESS

RUNNING HOT. Sub-topics. Fuel cells Casting Solidification

Reduction of Micro-Cracks in Large Diameter In x Ga 1-x Sb Bulk Crystals

Microelectronics Devices

MICROCHIP MANUFACTURING by S. Wolf

Citation for the original published paper (version of record):

Effect of external gettering with porous silicon on the electrical properties of Metal-Oxide-Silicon devices

METALLURGICAL SILICON REFINING BY TRANSIENT DIRECTIONAL SOLIDIFICATION

Transcription:

Chapter 2 Crystal Growth and Wafer Preparation Professor Paul K. Chu

Advantages of Si over Ge Si has a larger bandgap (1.1 ev for Si versus 0.66 ev for Ge) Si devices can operate at a higher temperature (150 o C vs 100 o C) Intrinsic resistivity is higher (2.3 x 10 5 Ω-cm vs 47 Ω- cm) SiO 2 is more stable than GeO 2 which is also water soluble Si is less costly

The processing characteristics and some material properties of silicon wafers depend on its orientation. The <111> planes have the highest density of atoms on the surface, so crystals grow most easily on these planes and oxidation occurs at a higher pace when compared to other crystal planes. Traditionally, bipolar devices are fabricated in <111> oriented crystals whereas <100> materials are preferred for MOS devices.

Defects Any non-silicon atoms incorporated into the lattice at either a substitutional or interstitial site are considered point defects Point defects are important in the kinetics of diffusion and oxidation. Moreover, to be electrically active, dopants must occupy substitutional sites in order to introduce an energy level in the bandgap.

Dislocations are line defects. Dislocations in a lattice are dynamic defects. That is, they can diffuse under applied stress, dissociate into two or more dislocations, or combine with other dislocations. Dislocations in devices are generally undesirable, because they act as sinks for metallic impurities and alter diffusion profiles.

Defects Two typical area or planar defects are twins and grain boundaries Twinning represents a change in the crystal orientation across a twin plane, such that a mirror image exists across that plane Grain boundaries are more disordered than twins and separate grains of single crystals in polycrystalline silicon Planar defects appear during crystal growth, and crystals having such defects are not considered usable for IC manufacture and are discarded

Precipitates of impurity or dopant atoms constitute the fourth class of defects. The solubility of dopants varies with temperature, and so if an impurity is introduced at the maximum concentration allowed by its solubility, a supersaturated condition will exist upon cooling. The crystal achieves an equilibrium state by precipitating the impurity atoms in excess of the solubility level as a second phase. Precipitates are generally undesirable as they act as sites for dislocation generation. Dislocations result from the volume mismatch between the precipitate and the lattice, inducing a strain that is relieved by the formation of dislocations.

Electronic Grade Silicon Electronic-grade silicon (EGS), a polycrystalline material of high purity, is the starting material for the preparation of single crystal silicon. EGS is made from metallurgical-grade silicon (MGS) which in turn is made from quartzite, which is a relatively pure form of sand. MGS is purified by the following reaction: Si (solid) + 3HCl (gas) SiHCl 3 (gas) + H 2 (gas) + heat The boiling point of trichlorosilane (SiHCl 3 ) is 32 o C and can be readily purified using fractional distillation. EGS is formed by reacting trichlorosilane with hydrogen: 2SiHCl 3 (gas) + 2H 2 (gas) 2Si (solid) + 6HCl (gas)

Czochralski Crystal Growth The Czochralski (CZ) process, which accounts for 80% to 90% of worldwide silicon consumption, consists of dipping a small single-crystal seed into molten silicon and slowly withdrawing the seed while rotating it simultaneously. The crucible is usually made of quartz or graphite with a fused silica lining. After the seed is dipped into the EGS melt, the crystal is pulled at a rate that minimizes defects and yields a constant ingot diameter.

Impurity Segregation Impurities, both intentional and unintentional, are introduced into the silicon ingot. Intentional dopants are mixed into the melt during crystal growth, while unintentional impurities originate fromthe crucible, ambient, etc. All common impurities have different solubilities in the solid and in the melt. An equilibrium segregation coefficient k o can be defined to be the ratio of the equilibrium concentration of the impurity in the solid to that in the liquid at the interface, i.e. k o = C s /C l. Note that all the values shown in the table are below unity, implying that the impurities preferentially segregate to the melt and the melt becomes progressively enriched with these impurities as the crystal is being pulled. Impurity Al As B C Cu Fe O P Sb k o 0.002 0.3 0.8 0.07 4x10-6 8x10-6 0.25 0.35 0.023

Impurity Distribution The distribution of an impurity in the grown crystal can be described mathematically by the normal freezing relation: C s k o C o (1 X ) k o 1 X is the fraction of the melt solidified C o is the initial melt concentration C s is the solid concentration k o is the segregation coefficient

Ingot Weight = M Weight = dm Dopant conc. = C s Consider a crystal being grown from a melt having an initial weight M o with an initial dopant concentration C o in the melt (i.e., the weight of the dopant per 1 gram melt). Melt S = dopant remaining in melt At a given point of growth when a crystal of weight M has been grown, the amount of the dopant remaining in the melt (by weight) is S. For an incremental amount of the crystal with weight dm, the corresponding reduction of the dopant (-ds) from the melt is C s dm, where C s is the dopant concentration in the crystal (by weight): -ds = C s dm

The remaining weight of the melt is M o the liquid (by weight), C l, is given by C l - M, and the dopant concentration in S M M o Combining the two equations and substituting ds S k o dm M o M C C k s l o Given the initial weight of the dopant, S C M o o ds S k o o M dm M M o C o M o, we can integrate and obtain Solving the equation gives C k C s o o 1 M M o k o 1

Impurity concentration profiles along the silicon ingot (axially) for different k o with C o = 1

CZ-Si crystals are grown from a silicon melt contained in a fused silica (SiO 2 ) crucible. Fused silica reacts with hot silicon and releases oxygen into the melt giving CZ-Si an indigenous oxygen concentration of about 10 18 atoms/cm 3. Although the segregation coefficient of oxygen is <1, the axial distribution of oxygen is governed by the amount of oxygen in the melt. Less dissolution of the crucible material occurs as the melt volume diminishes, and less oxygen is available for incorporation.

Oxygen in Silicon Oxygen forms a thermal donor in silicon Oxygen increases the mechanical strength of silicon Oxygen precipitates provide gettering sites for unintentional impurities

Thermal Donors Thermal donors are formed by the polymerization of Si and O into complexes such as SiO 4 in interstitial sites at 400 o C to 500 o C Careful quenching of the crystal annihilates these donors

Internal Gettering Under certain annealing cycles, oxygen atoms in the bulk of the crystal can be precipitated as SiO x clusters that act as trapping sites to impurities. This process is called internal gettering and is one of the most effective means to remove unintentional impurities from the near surface region where devices are fabricated.

Float-Zone Process The float-zone process has some advantages over the Czochralski process for the growth of certain types of silicon crystals. The molten silicon in the float-zone apparatus is not contained in a crucible, and is thus not subject to the oxygen contamination present in CZ-Si crystals. The float-zone process is also necessary to obtain crystals with a high resistivity (>> 25 W-cm).

Characterization Routine evaluation of ingots or boules involves measuring the resistivity, evaluating their crystal perfection, and examining their mechanical properties, such as size and mass Other tests include the measurement of carbon, oxygen, and heavy metals

Resistivity Measurement Resistivity measurements are made on the flat ends of the crystal by the four-point probe technique. A current, I, is passed through the outer probes and the voltage, V, is measured between the inner probes. The measured resistance (V/I) is converted to resistivity (W-cm) using the relationship: ρ = (V/I)2πS

The calculated resistivity can be correlated with dopant concentration using a dopant concentration versus resisitivity chart

Wafer Preparation Gross crystalline imperfections are detected visually and defective crystals are cut from the boule. More subtle defects such as dislocations can be disclosed by preferential chemical etching Chemical information can be acquired employing wet analytical techniques or more sophisticated solid-state and surface analytical methods Silicon, albeit brittle, is a hard material. The most suitable material for shaping and cutting silicon is industrial-grade diamond. Conversion of silicon ingots into polished wafers requires several machining, chemical, and polishing operations

Grinding

After grinding to fix the diameter, one or more flats are grounded along the length of the ingot. The largest flat, called the "major" or "primary" flat, is usually relative to a specific crystal orientation. The flat is located by x-ray diffraction techniques. The primary flat serves as a mechanical locator in automated processing equipment to position the wafer, and also serves to orient the IC device relative to the crystal. Other smaller flats are called "secondary" flats that serve to identify the orientation and conductivity type of the wafer. The drawback of these flats is the reduction of the usable area on the wafer. For some 200 mm and 300 mm diameter wafers, only a small notch is cut from the wafer to enable lithographic alignment but no dopant type or crystal orientation information is conveyed.

Slicing determines four wafer parameters: Surface orientation (e.g., <111> or <100>) Thickness (e.g., 0.5 0.7 mm, depending on wafer diameter) Taper, which is the wafer thickness variations from one end to another Bow, which is the surface curvature of the wafer measured from the center of the wafer to its edge

Finished Wafers The wafer as cut varies enough in thickness to warrant an additional lapping operation that is performed under pressure using a mixture of Al 2 O 3 and glycerine. Subsequent chemical etching removes any remaining damaged and contaminated regions. Polishing is the final step. Its purpose is to provide a smooth, specular surface on which device features can be photoengraved.

Typical Specifications for Silicon Wafers Parameter 125 mm 150 mm 200 mm 300 mm Diameter (mm) 125+1 150+1 200+1 300+1 Thickness (mm) 0.6-0.65 0.65-0.7 0.715-0.735 0.755-0.775 Bow (μm) 70 60 30 <30 Total thickness variation (μm) 65 50 10 <10 Surface orientation +1 o +1 o +1 o +1 o