Because of equipment availability, cost, and time, we will use aluminum as the top side conductor

Similar documents
micro resist technology

Lecture 19 Microfabrication 4/1/03 Prof. Andy Neureuther

Microelectronic Device Instructional Laboratory. Table of Contents

Low-temperature, Simple and Fast Integration Technique of Microfluidic Chips by using a UV-curable Adhesive

CS/ECE 5710/6710. N-type Transistor. N-type from the top. Diffusion Mask. Polysilicon Mask. CMOS Processing

Complexity of IC Metallization. Early 21 st Century IC Technology

Fabrication Technology

Photolithography I ( Part 2 )

micro resist technology

Microfabrication of Integrated Circuits

Chapter 3 Silicon Device Fabrication Technology

Processing guidelines. Negative Tone Photoresist Series ma-n 2400

Mostafa Soliman, Ph.D. May 5 th 2014

Introduction to Nanoscience and Nanotechnology

Schematic creation of MOS field effect transistor.

Making of a Chip Illustrations

Photolithography Process Technology

Fabrication and Layout

!"#$#%&#'(() ) **+,-./01)2-,-.3)456,1) /0! **)

4. Thermal Oxidation. a) Equipment Atmospheric Furnace

Surface micromachining and Process flow part 1

Photoresist Coat, Expose and Develop Laboratory Dr. Lynn Fuller

Major Fabrication Steps in MOS Process Flow

Bulk MEMS Fabrication Details Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu

Wafer (1A) Young Won Lim 4/30/13

Fabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB

Dr. Priyabrat Dash Office: BM-406, Mob: Webpage: MB: 205

Czochralski Crystal Growth

EE 330 Lecture 9. IC Fabrication Technology Part 2

Semiconductor device fabrication

conductor - gate insulator source gate n substrate conductor - gate insulator gate substrate n open switch closed switch however: closed however:

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing

Temperature Scales. Questions. Temperature Conversions 7/21/2010. EE580 Solar Cells Todd J. Kaiser. Thermally Activated Processes

All fabrication was performed on Si wafers with 285 nm of thermally grown oxide to

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009

Supporting Information: Model Based Design of a Microfluidic. Mixer Driven by Induced Charge Electroosmosis

Dow Corning WL-5150 Photodefinable Spin-On Silicone

Most semiconductor devices contain at least one junction between p-type and n-type material. These p-n junctions are fundamental to the performance

Lecture #18 Fabrication OUTLINE

EECS130 Integrated Circuit Devices

EE 5344 Introduction to MEMS. CHAPTER 3 Conventional Si Processing

Electronic Supplementary Information

Chapter 2 MOS Fabrication Technology

Fabrication of Nanoscale Silicon Membranes on SOI Wafers Using Photolithography and Selective Etching Techniques:

Report 1. B. Starting Wafer Specs Number: 10 Total, 6 Device and 4 Test wafers

IC/MEMS Fabrication - Outline. Fabrication

UV15: For Fabrication of Polymer Optical Waveguides

The Physical Structure (NMOS)

Technology process. It s very small world. Electronics and Microelectronics AE4B34EM. Why is the integration so beneficial?

MCC. PMGI Resists NANO PMGI RESISTS OFFER RANGE OF PRODUCTS

Lab #2 Wafer Cleaning (RCA cleaning)

EELE408 Photovoltaics Lecture 02: Silicon Processing

Review of CMOS Processing Technology

Fabrication Technology, Part I

Micro & nanofabrica,on

Physical Vapor Deposition (PVD) Zheng Yang

Solid State Sensors. Microfabrication 8/22/08 and 8/25/08

Basic&Laboratory& Materials&Science&and&Engineering& Micro&Electromechanical&Systems&& (MEMS)&

Introduction to Nanofabrication: Top Down to Bottom Up

Metallization deposition and etching. Material mainly taken from Campbell, UCCS

Technology. Semiconductor Manufacturing. Hong Xiao INTRODUCTION TO SECOND EDITION SPIE PRESS

Lecture 5: Micromachining

Chapter 3 CMOS processing technology

Semiconductor Manufacturing Technology. IC Fabrication Process Overview

PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS

Processing guidelines. Negative Tone Photoresists mr-ebl 6000

Fabrication and Layout

Photolithography. Dong-Il Dan Cho. Seoul National University Nano/Micro Systems & Controls Laboratory

Lect. 2: Basics of Si Technology

Eco-Friendly Photolithography Using Water- Developable Pure Silk Fibroin

EE 527 MICROFABRICATION. Lecture 15 Tai-Chang Chen University of Washington EE-527 M4 MASK SET: NPN BJT. C (sub) A E = 40 µm x 40 µm

4/10/2012. Introduction to Microfabrication. Fabrication

9-11 April 2008 Micro-electroforming Metallic Bipolar Electrodes for Mini-DMFC Stacks

Lecture 10: MultiUser MEMS Process (MUMPS)

Introduction to Micro/Nano Fabrication Techniques. Date: 2015/05/22 Dr. Yi-Chung Tung. Fabrication of Nanomaterials

Lecture 1A: Manufacturing& Layout

DuPont MX5000 Series

Cu Wiring Process for TFTs - Improved Hydrogen Plasma Resistance with a New Cu Alloy -

Welcome MNT Conference 1 Albuquerque, NM - May 2010

EE 432/532 CyMOS process PWELL Lithography & Diffusion Feb 24, 2016

The Hummer VI. Brian Thomas Lithography. October 29, Hummer VI THE UNIVERSITY OF TEXAS AT DALLAS ERIK JOHNSON SCHOOL OF ENGINEERING

PHYSICAL ELECTRONICS(ECE3540) Brook Abegaz, Tennessee Technological University, Fall 2013

Process Flow in Cross Sections

CHAPTER - 4 CMOS PROCESSING TECHNOLOGY

CMOS Technology. Flow varies with process types & company. Start with substrate selection. N-Well CMOS Twin-Well CMOS STI

Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate

Be careful what you wish for

Via Fill in Small Trenches using Hot Aluminum Process. By Alice Wong

FABRICATION of MOSFETs

Nanoelectronics Fabrication Facility

Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate

Screen Printing of Highly Loaded Silver Inks on. Plastic Substrates Using Silicon Stencils

Thomas M. Adams Richard A. Layton. Introductory MEMS. Fabrication and Applications. Springer

A discussion of crystal growth, lithography, etching, doping, and device structures is presented in

Dr. Lynn Fuller, Motorola Professor Steven Sudirgo, Graduate Student

Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate

Thermal Nanoimprinting Basics

SUPPORTING INFORMATION: Collateral Advantages of a Gel Electrolyte for. Higher Voltage; Reduced Volume

Transcription:

Because of equipment availability, cost, and time, we will use aluminum as the top side conductor

Top Side Conductor vacuum deposition Aluminum sputter deposit in Argon plasma CVC 601-sputter deposition tool

A conductor metal is vacuum deposited on to the wafer Aluminum will be used instead of silver Sputtered aluminum

Photolithography Photolithography is the transfer of patterns, circuits, device structures, etc. to a substrate or wafer using light and a mask or stencil to stop the light. Photolithography is used extensively in the progression of microelectronics. Today, because of the sizes involved in current computer microprocessor devices, other methods like direct patterning using electron beams are used. Photolithography is still used for dimensions down to about 0.5um. The wavelength of UV light is.35-.45 um.

Top side conductor grid is created using a transparency mask The top side conductor grid is created on a transparency sheet to keep cost low Once top side conductor grid design is finalized, a chrome on glass professional mask can be made to go into mass production

Top side conductor Because of Cameron tester limitations (1.0A) cell size is limited to about 65mm x 65mm max

UV light sensitive material called photoresist is spin coated on to the aluminum conductor on the top side of the wafer (polished side) Positive photoresist - 1813 Aluminum Silicon wafer

Wafers are spin coated with Shipley 1813 UV sensitive photoresist spin coating produces a uniform coating Run a test spin without the photoresist to verify operation Spin speed is set here. Spin speed is 4K rpm Close lid and apply photoresist through the lid opening A vacuum chuck holds the wafer Light sensitive material is stored in amber dropper bottles Use 1813

Transparency is used as a photomask. Cells can be designed to various sizes Cells can be of various sizes but must line up for saw cutting

The transparency is called a photo mask. Production photo masks would be made on glass plates with high precision patterns. Transparency mask A glass plate is placed on top of transparency mask to keep it flat and prevent light to leak under the transparency Glass plate Positive photoresist - 1813 Aluminum Silicon wafer

HTG mask aligner is used to provide the UV Clear glass plates are used to make sure the transparency lays flat to the wafer light source The UV light source is a mercury vapor lamp at 436nm wavelength UV light with filter surrounding it Exposure time set on timer Wafer is held by vacuum, mask is placed on top and brought into contact with wafer

Ultraviolet light is projected down on to the photoresist coated wafer UV light Glass plate Aluminum Silicon wafer Exposed photoresist

The wafer is developed, leaving photoresist where no UV light has penetrated the mask Aluminum Silicon wafer Unexposed photoresist

Solitec automatic developer vacuum chuck holds wafer, tool develops, rinses, and dries the wafer Minimum vacuum level is 15 on vacuum gauge Vacuum switch Start switch hold down until tool starts

The wafer is immersed in the aluminum etch and the top side aluminum conductor is dissolved (etched away) Because it is a liquid etch and can undercut the photoresist it is important to remove the wafer from the etchant as soon as the pattern clears Liquid aluminum etchant PR Al PR PR PR Al Al Al Silicon wafer

Unwanted aluminum is etched away using the aluminum etchant at about 80 0 C Aluminum etch @ 80 o C Aluminum etch contains strong acids and all safety precautions are needed

After etching, the top conductor grid pattern will be left on the wafer. The photoresist is removed leaving the top side aluminum grid Completed topside conductor Al Al Al Al N- region P type silicon wafer

Once the top side conductor grid is complete, the back side conductor can be deposited, again aluminum sputtered with the CVC 601 will be used Al Al Al Al N- region P type silicon wafer Backside aluminum

Assignment Complete the photolithography worksheet