Exam 1 Friday Sept 22 Students may bring 1 page of notes Next weeks HW assignment due on Wed Sept 20 at beginning of class No 5:00 p.m extension so solutions can be posted Those with special accommodation needs, please send me an email message or contact me so arrangements can be made Review session - time to be announced
EE 330 Lecture 10 IC Fabrication Technology Part III Metalization and Interconnects Parasitic Capacitances Back-end Processes Devices in Semiconductor Processes Resistors Diodes
Review from Last Lecture IC Fabrication Technology Crystal Preparation Masking Photolithographic Process Deposition Etching Diffusion Ion Implantation Oxidation Epitaxy Polysilicon Planarization Contacts, Interconnect and Metalization
Review from Last Lecture Contacts A A B B Acceptable Contact Unacceptable Contact Vulnerable to pin holes (usually all contacts are same size)
Review from Last Lecture Contacts B B Acceptable Contact
Contacts 2λ 2λ 1.5λ 1.5λ 2λ Dog Bone Contact Design Rule Violation
Contacts Common Circuit Connection Standard Interconnection Buried Contact Can save area but not allowed in many processes
Metalization Aluminum widely used for interconnect Copper often replacing aluminum in recent processes Must not exceed maximum current density around 1ma/u for aluminum and copper Ohmic Drop must be managed Parasitic Capacitances must be managed Interconnects from high to low level metals require connections to each level of metal Stacked vias permissible in some processes
Metalization Aluminum Aluminum is usually deposited uniformly over entire surface and etched to remove unwanted aluminum Mask is used to define area in photoresist where aluminum is to be removed Copper Plasma etches not effective at removing copper because of absence of volatile copper compounds Barrier metal layers needed to isolate silicon from migration of copper atoms Damascene or Dual-Damascene processes used to pattern copper
Patterning of Aluminum Contact Opening from Mask Photoresist
Patterning of Aluminum Contact Opening after SiO 2 etch Photoresist
Patterning of Aluminum Contact Opening after SiO 2 etch Photoresist
Patterning of Aluminum Metal Applied to Entire Surface
Patterning of Aluminum Photoresist Patterned with Metal Mask
Patterning of Aluminum Aluminum After Metal Etch (photoresist still showing)
Copper Interconnects Limitations of Aluminum Interconnects Electromigration Conductivity not real high Relevant Key Properties of Copper Reduced electromigration problems at given current level Better conductivity Challenges of Copper Interconnects Absence of volatile copper compounds (does not etch) Copper diffuses into surrounding materials (barrier metal required)
Source: Sept 13, 2017
Copper Interconnects Practical methods of realizing copper interconnects took many years to develop Copper interconnects widely used in some processes today
Damascene Process Patterning of Copper Contact Opening after SiO 2 etch Photoresist
Damascene Process Patterning of Copper Tungsten (W) CMP Target W has excellent conformality when formed from WF6
Chemical-Mechanical Planarization (CMP) Polishing Pad and Wafer Rotate in non-concentric pattern to thin, polish, and planarize surface Abrasive/Chemical polishing Depth and planarity are critical Acknowledgement: http://en.wikipedia.org/wiki/chemical-mechanical_planarization
Patterning of Copper Damascene Process After first CMP Step CMP Target W-plug
Damascene Process Patterning of Copper After first CMP Step Oxidation
Damascene Process Patterning of Copper Photoresist Patterned with Metal Mask Defines Trench
Patterning of Copper Damascene Process Shallow Trench after Etch W-plug
Damascene Process Patterning of Copper Barrier Metal (Barrier metal added before copper to contain the copper atoms)
Damascene Process Patterning of Copper W-plug Copper Deposition
Patterning of Copper Damascene Process W-plug CMP Target Copper Deposition Copper is deposited or electroplated (Barrier Metal Used for Electroplating Seed)
Patterning of Copper Damascene Process After Second CMP Step W-plug Copper CMP Target
Dual-Damascene Process Patterning of Copper Shallow Trench Defined in PR with Metal Mask Photoresist
Dual-Damascene Process Patterning of Copper Shallow Trench After Etch Photoresist
Dual-Damascene Process Patterning of Copper Via Defined in PR with Via Mask Photoresist
Dual-Damascene Process Patterning of Copper Via Etch Defines Contact Region Photoresist (Barrier Metal added before copper but not shown)
Dual-Damascene Process Patterning of Copper Copper Deposited on Surface Copper is deposited or electroplated (Barrier Metal Used for Electroplating Seed)
Dual-Damascene Process Patterning of Copper Copper Deposited on Surface CMP Target
Dual-Damascene Process Patterning of Copper Copper Via Copper Interconnect CMP Target
Patterning of Copper Both Damascene Processes Realize Same Structure Damascene Process Two Dielectric Deposition Steps Two CMP Steps Two Metal Deposition Steps Two Dielectric Etches W-Plug Dual-Damascene Process One Dielectric Deposition Steps One CMP Steps One Metal Deposition Steps Two Dielectric Etches Via formed with metal step
Multiple Level Interconnects 3-rd level metal connection to n-active without stacked vias
Multiple Level Interconnects 3-rd level metal connection to n-active with stacked vias
Interconnect Layers May Vary in Thickness or Be Mostly Uniform Metalization 12.5μ
Interconnects Metal is preferred interconnect Because conductivity is high Parasitic capacitances and resistances of concern in all interconnects Polysilicon used for short interconnects Silicided to reduce resistance Unsilicided when used as resistors Diffusion used for short interconnects Parasitic capacitances are high
Interconnects Metal is preferred interconnect Because conductivity is high Parasitic capacitances and resistances of concern in all interconnects Polysilicon used for short interconnects Silicided to reduce resistance Unsilicided when used as resistors Diffusion used for short interconnects Parasitic capacitances are high
Resistance in Interconnects B W A L H A R B
Resistance in Interconnects B W D A H L R L A ρ D R B A=HW ρ independent of geometry and characteristic of the process
Resistance in Interconnects B W D A H H << W and H << L in most processes Interconnect behaves as a thin film Sheet resistance often used instead of conductivity to characterize film R =ρ/h R=R [L / W] R L L A ρ L W ρ H
Resistance in Interconnects W L R=R [L / W] The Number of Squares approach to resistance determination in thin films 1 2 3 21 N S = 21 L / W=21 R=R N S
Resistance in Interconnects Fractional Squares Can Be Represented By Their Fraction Corners Contribute about.55 Squares The squares approach is not exact but is good enough for calculating resistance in almost all applications In this example: N S =12+.55+.7=13.25 R=R 13.25
Example: The layout of a film resistor with electrodes A and B is shown. If the sheet resistance of the film is 40 Ω/, determine the resistance between nodes A and B. 10u A 3u 1u B
Solution 10u A 3u 1u B N S =9+9+3+2(.55)=22.1 R AB =R N S =40x22.1=884Ω
Resistance in Interconnects (can be used to build resistors!) Serpentine often used when large resistance required Polysilicon or diffusion often used for resistor creation Effective at managing the aspect ratio of large resistors May include hundreds or even thousands of squares
Resistance in Interconnects (can be used to build resistors!) d 2 2 d 1 Area requirements determined by both minimum width and minimum spacing design rules
Capacitance in Interconnects C=C D A C D is the capacitance density and A is the area of the overlap
Capacitance in Interconnects Metal 2 A 3 Metal 1 A 1 A 5 A 2 A 4 Substrate M 2 M 1 SUB C 12 C 2S C 1S Equivalent Circuit C 12 =CD 12 A 5 C 1S =CD 1S (A 1 +A 2 +A 5 ) C 2S =CD 2S (A 3 +A 4 )
Example Two metal layers, Metal 1 and Metal 2, are shown. Both are above field oxide. Determine the capacitance between Metal 1 and Metal 2. Assume the process has capacitance densities from M 1 to substrate of.05ff/u 2, from M 1 to M 2 of.07ff/u 2 and from M 2 to substrate of.025ff/u 2. 30µ 10µ Metal 1 Metal 2 30µ 30µ 10µ 30µ
Example Solution 30µ 10µ 30µ 30µ 10µ 30µ A C1C2 2 2 20μ 400μ 30µ The capacitance density from M 1 to M 2 is.07ff/u 2 2 2 C12 AC1C2 CD12 400 0.07fF/ 28fF
Capacitance and Resistance in Interconnects See MOSIS WEB site for process parameters that characterize parasitic resistances and capacitances www.mosis.org
Example Determine the resistance and capacitance of a Poly interconnect that is 0.6u wide and 800u long and compare that with the same interconnect if M 1 were used. 0.6µ POLY 800µ R =n R POLY SQ SH C P-SUB =A C R SH =? R DPS =? DPS
R SH =23.5Ω/ C DPS =84 af/µ 2
Example Determine the resistance and capacitance of a Poly interconnect that is 0.6u wide and 800u long and compare that with the same interconnect if M 1 were used. 0.6µ POLY n SQ 800 06. 1333 800µ A= 0. 6 800 480 2 R =n R =23.5 1333=31.3KΩ POLY SQ SH 2-2 C =A C =480μ 84aFμ =40.3fF P-SUB DPS
Example Determine the resistance and capacitance of a Poly interconnect that is 0.6u wide and 800u long and compare that with the same interconnect if M 1 were used. 0.6µ Metal 1 800µ
R SH =0.09Ω/ C DPS =27 af/µ 2
Example Determine the resistance and capacitance of a Poly interconnect that is 0.6u wide and 800u long and compare that with the same interconnect if M 1 were used. 0.6µ Metal 1 n SQ 800 06. 1333 800µ A= 0. 6 800 480 2 R =n R =0.09 1333=120Ω M1 SQ SH 2-2 C =A C =480μ 27aFμ =13.0fF M1-SUB DM1S
End of Lecture 10