CMOS Manufacturing Process CMOS Process 1
A Modern CMOS Process gate-oxide TiSi AlCu Tungsten SiO n+ p-well p-epi poly n-well p+ SiO p+ Dual-Well Trench-Isolated CMOS Process Circuit Under Design V DD V DD M M4 V in V out V out M1 M This two-inverter circuit (of Figure.5 in the text) will be manufactured in a twin-well process.
Circuit Layout The For a great tour through the process and its different steps, check http://www.fullman.com/semiconductors/semiconductors.html For a complete walk-through of the process (64 steps), check the Book web-page http://bwrc.eecs.berkeley.edu/classes/icbook
Photo-Lithographic Process oxidation optical mask photoresist removal (ashing) photoresist coating stepper exposure process step Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch spin, rinse, dry Patterning of SiO Si-substrate (a) Silicon base material Si-substrate (b) After oxidation and deposition of negative photoresist Si-substrate (c) Stepper exposure Photoresist SiO UV-light Patterned optical mask Exposed resist Si-substrate Si-substrate Chemical or plasma etch Hardened resist SiO (d) After development and etching of resist, chemical or plasma etch of SiO Si-substrate (e) After etching Hardened resist SiO SiO (f) Final result after removal of resist 4
CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers CMOS Process Walk-Through p-epi p+ (a) Base material: p+ substrate with p-epi layer p-epi p+ SiN 4 SiO (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer) p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask 5
CMOS Process Walk-Through SiO (d) After trench filling, CMP planarization, and removal of sacrificial nitride n (e) After n-well and V Tp adjust implants p (f) After p-well and V Tn adjust implants CMOS Process Walk-Through poly(silicon) (g) After polysilicon deposition and etch n+ p+ (h) After n+ source/drain and p+source/drain implants. These steps also dope the polysilicon. SiO (i) After deposition of SiO insulator and contact hole etch. 6
CMOS Process Walk-Through Al (j) After deposition and patterning of first Al layer. Al SiO (k) After deposition of SiO insulator, etching of via s, deposition and patterning of second layer of Al. Advanced Metalization 7
Advanced Metalization Design Rules Jan M. Rabaey 8
D Perspective Polysilicon Aluminum Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width» scalable design rules: lambda parameter» absolute dimensions (micron rules) 9
CMOS Process Layers Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation Layers in 0.5 µm CMOS process 10
Intra-Layer Design Rules Same Potential Different Potential Well Active Select 10 0 or 6 9 Contact or Via Hole Polysilicon Metal1 Metal 4 Transistor Layout Transistor 1 5 11
Via s and Contacts 1 Via 1 4 5 Metal to Active Contact 1 Metal to Poly Contact Select Layer Select 1 5 Substrate Well 1
CMOS Inverter Layout GND In V DD A A Out (a) Layout A A n p-substrate Field n + p + Oxide (b) Cross-Section along A-A Layout Editor 1
Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um. Sticks Diagram V DD In 1 Out Dimensionless layout entities Only topology is important Final layout generated by compaction program GND Stick diagram of inverter 14