Digital Integrated Circuits A Design Perspective Chapter 2 Manufacturing Process 1
CMOS Process 2
CMOS Process (n-well) Both NMOS and PMOS must be built in the same silicon material. PMOS in n-well NMOS in p-substrate 3
A Modern CMOS Process PMOS in n-well NMOS in p-well gate-oxide TiSi 2 AlCu Tungsten SiO 2 n+ p-well p-epi poly n-well p+ SiO 2 p+ Dual-Well Trench-Isolated CMOS Process 4
Circuit Under Design V DD V DD M2 M4 V in V out V out2 M1 M3 5
Its Layout View 6
The Manufacturing Process For a great tour through the IC manufacturing process and its different steps, check http://www.fullman.com/semiconductors/semiconductors.html 7
Silicon Wafer A single crystal ingot cut into thin slices. Diameters: 4-12 inches 8
Photo-Lithographic Process oxidation optical mask photoresist removal (ashing) photoresist coating stepper exposure process step Typical operations in a single photolithographic cycle (from [Fullman]). spin, rinse, dry acid etch photoresist development 9
Photo-Lithographic Process (2) Oxidation layering this optional step deposits a thin layer of SiO2 over the complete wafer by exposing it to a mixture of high-purity oxygen and hydrogen at approximately 1000 C. The oxide is used as an insulation layer and also forms transistor gates. Photoresist coating a light sensitive polymer is evenly applied to a thickness of approximately 1µm by spinning the wafer. Positive photoresist Negative photoresist Stepper exposure a glass mask containing the patterns that we want to transfer to the silicon is brought in close proximity to the wafer. Photoresist development and bake the wafer are developed in either an acid or base solution to remove the nonexposed areas of photoresist. Once the exposed photoresist is removed, the wafer is soft baked at a low temperature to harden the remaining photoresist. 10
Photo-Lithographic Process (3) Acid etching material is selectively removed from areas of the wafer that are not covered by photoresist. Spin, rinse, and dry a special tool (called SRD) cleans the wafer with deionized water and dries it with nitrogen. Various process steps ion implantation, plasma etching, metal deposition, and so on. Photoresist removal (or ashing) a high-temperature plasma is used to selectively remove the remaining photoresist without damaging device layers. 11
Patterning of SiO2 Si-substrate (a) Silicon base material Si-substrate Photoresist SiO 2 Si-substrate Chemical or plasma etch Hardened resist SiO 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (b) After oxidation and deposition of negative photoresist Hardened resist SiO 2 UV-light Patterned optical mask Si-substrate (e) After etching Exposed resist SiO 2 Si-substrate (c) Stepper exposure Si-substrate (f) Final result after removal of resist 12
Recurring Process Steps (1) Diffusion and Ion Implantation Diffusion implantation: The wafers are placed in a quartz tube embedded in a heated furnace. A gas containing the dopant is introduced in the tube. The dopants diffuse into the exposed surface both vertically and horizontally. Ion implantation: Dopants are introduced as ions into the material. The ion implantation system directs and sweeps a beam of purified ions over the semiconductor surface. Advantage: It allows for an independent control of depth and dosage. Disadvantage: it damages the lattice of the semiconductor. The annealing step, in which the wafer is heated to around 1000 C for 15 to 30 minutes, and then allowed to cool slowly, is needed. 13
Recurring Process Steps (2) Deposition CMOS process requires the repetitive deposition of layers of a material over the complete wafer, to either act as buffers for a processing step, or as insulating or conducting layers. Etching: Once a material has been deposited, etching is used selectively to form patterns such as wires, contact hole, and etc. Wet etching method etches material both vertically and horizontally, and dry etching method etches material only vertically. Planarization: To reliably deposit a layer of material onto the semiconductor surface, it is essential that the surface be approximately flat. 14
CMOS Process Flow Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers 15
CMOS Process Walk-Through (1) p-epi p+ (a) Base material: p+ substrate with p-epi layer p-epi p+ Si 3 N 4 SiO 2 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer) p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask 16
CMOS Process Walk-Through (2) SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride n (e) After n-well and V Tp adjust implants p (f) After p-well and V Tn adjust implants 17
CMOS Process Walk-Through (3) poly(silicon) (g) After polysilicon deposition and etch n+ p+ (h) After n+ source/drain and p+ source/drain implants. These steps also dope the polysilicon. SiO 2 (i) After deposition of SiO 2 insulator and contact hole etch. 18
CMOS Process Walk-Through (4) Al (j) After deposition and patterning of first Al layer. Al SiO 2 (k) After deposition of SiO 2 insulator, etching of via s, deposition and patterning of second layer of Al. 19
Advanced Metallization 20
Advanced Metallization 21
Layout and Design Rules 22
3D Perspective Polysilicon Aluminum 23
Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width Design rules: Width, Space, Clearance, Extension, and Overlap 24
Design Rules Width and Space Width Space 25
Design Rules Clearance Unrelated Related 26
Design Rules Extension and Overlap Extension Overlap 27
CMOS Process Layers Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation 28
Layers in 0.25 µm m CMOS process 29
Intra-Layer Design Rules Same Potential Different Potential Well 10 0 or 6 9 Polysilicon 2 2 Active Select 3 3 2 Contact or Via Hole 2 2 Metal1 Metal2 3 3 4 3 30
Transistor Layout Transistor 1 3 2 5 31
Vias and Contacts 2 1 Via 1 4 5 Metal to Active Contact 1 Metal to Poly Contact 3 2 2 2 32
Select Layer 3 2 2 Select 1 3 3 2 5 Substrate Well 33
CMOS Inverter Layout GND In V DD A A Out (a) Layout A A p-substrate n Field Oxide n + (b) Cross-Section along A-A 34 p +
Layout Editor - max It is developed at the University of California at Berkeley. 35
Layout Editor - Virtuoso 36
Layout Editor - Laker 37
Design Rule Checker DRC (Design Rule Check) Using CAD tools to verify the layout On-line DRC: Diva (Virtuoso) Off-line DRC: Dracula 38
Symbolic Layout Full-custom VS Cell-Based Symbolic Layout The designer only draw a shorthand notation for the layout structure (transistors, contacts, wires). Advantage: designers don t care design rules Disadvantages: The density is unpredictable. 39
Sticks Diagram V DD 3 In 1 Out Dimensionless layout entities Only topology is important Final layout generated by compaction program GND Stick diagram of inverter 40
Layout Example - Inverter 41
Design Example - NAND (1) 42
Design Example NAND (2) 43
Packaging 44
Packaging Requirements Requirements Electrical: Low parasitics Mechanical: Reliable and robust Thermal: Efficient heat removal Commercial: 0~75 C Military: -55~125 C Economical: Cheap Materials Plastics Up to 2 W Ceramic Al 2 O 3 (Alumina) Up to 20 W Disadvantage: High dielectric constant => Large interconnect capacitance 45
Wire Bonding Substrate Die Pad Lead Frame Wires materials: Aluminum or gold Disadvantages: Longer manufacturing Wire distance Hard to predict parasitics 46
Tape-Automated Bonding (TAB) Sprocket hole Film + Pattern Solder Bump Test pads Lead frame Polymer film Die Substrate (b) Die attachment using solder bumps. (a) Polymer Tape with imprinted wiring pattern. 47
Flip-Chip Bonding Die Solder bumps Interconnect layers Substrate 48
Package-to to-board Interconnect (a) Through-Hole Mounting (b) Surface Mount 49
Package Types 1. Bare die 2. DIP 3. PGA 4. Small-outline IC 5. Quad flat pack 6. PLCC 7. Leadless carrier 50
Package Parameters 51
Multi-Chip Modules 52
Trend in Process Now: LDD (Lightly Doped Drain) Silicide Short-Term Copper and Low-k Dilectric SOI (Silicon on Insulator) Long-Term 3-D integrated circuits 53