Test-Yield Improvement of High-Density Probing Technology Using Optimized Metal Backer with Plastic Patch

Test-Yield Improvement of High-Density Probing Technology Using Optimized Metal Backer with Plastic Patch Sen-Kuei Hsu, Hao Chen, Chung-Han Huang, Der-Jiann Liu, Wei-Hsun Lin, Hung-Chih Lin, Ching-Nen Peng, and Min-Jer Wang Taiwan Semiconductor Manufacturing Company, Ltd. No. 6, Creation Rd. 2, Hsinchu Science Park, Hsinchu, Taiwan 300-77, R. O. C. Abstract High-density probing is a main trend of the test technology. The warping issues of probe card are caused by the highdensity test. The metal backer and patches are applied to solve this problem and the optimized sizes of backer and patches are decided by the proposed flow. Using the probe card with optimized backer and patches, the stability of test can be ensured and the test yields are increased. 26.56% test-yield improvement can be obtained. 1. Introduction Along with a great progress in semiconductor manufacturing, several circuits can be merged together for the performance enhancements and cost reductions. However the pin counts are also increased with the progress of manufacturing. As shown in Figure1, the pin counts of the two microprocessor units (MPUs) in next decade, MPU with cost and high performance, are demonstrated [1]. It is clear that the pin counts of both are increased monotonically with the year increasing and pin counts are more than 9000 pins counts finally. Although pin counts in recent years are only approached to 4000 pins, pin counts are approached or more than 10000 pin counts in the multi-site test (8000 and 16000 pin counts for two-site and four-site tests). Besides the cases of MPUs, the pin counts of central processing unit (CPU) and graphic processing unit (GPU) for single-site test nowadays have been more than 11000 pins generally. From Figure 1, the high-density probing technique is the main trend in the near future, but the high-density tests are usually encountered nowadays. The warping issues are the common phenomena in the design of wafer, package, and PCB. Warping issues are usually occurred due to the thermal expansions and stress imbalance [2], [3]. Several methodologies are proposed to alleviate the warping issues by changing the positions, shapes, and materials of the structures. For the highdensity probing, warping phenomena of test interfaces are caused because of the larger vertical forces (For example: 120 kilogram rising force is estimated in this work) created by the contacts between tips and wafers. In the past, the pin counts of most of chips are smaller than 5000, so the test yields of single-site test are not significantly affected by the warping issues. However, the phenomena are getting worse with the pin counts increasing. Then the test yields are Figure 1 The predictions of MPUs pin counts in ITRS. Wafer Bumps Bumps Bumps Probing tips ATE Test head Load board Pogo Tower Hollow Space Probe card PCB Platform With Components Without Components 1 st Part of Interface Rising for test Figure 2 Typical test interface and the detail stacking of the first part of interface with components interface without components. Paper 1.2 INTERNATIONAL TEST CONFERENCE 1

Test Force Test Force Probe Card PCB Test Force Test Force Figure 3 Four deformations of probe card are flat type, basin type, mountain type, and (d) irregular wave type. decreased due to the open fail caused by warping phenomena. In this paper, a design and optimized flow is proposed for backer which is a metal cube placed between PCB and stiffener for warping suppression. To obtain the optimized backer design for the wafer test [4], a model of the test interface is constructed and analyzed by finite element method (ANSYS) [5]. In addition, a fine tuning methodology is also demonstrated to compensate the nonideal characteristics of practical test interface by adding overdrive and using patches. Finally, the practical tests (probe card with backer) are shown and the test yields of wafer are significantly increased. 2. Problem and Design Concept Description 2.1 Problem Description A typical test interface is shown in Figure 2 and it is composed of the load board, pogo tower, probe card, and substrate. The top of the interface is connected to automatic test equipment (ATE), and the probing tips are created at the bottom. In test process, wafer is put on the platform and then the platform rises gradually to make contacts with the probing tips. In general, all the tips are contact perfectly to the pads or bumps for test, and the performances of chips can be obtained easily. However, it is not easy for the high-density probe card to have perfect contacts on pads or bumps because of the warping phenomenon. The main reason is that the vertical force is too large for the first part of test interface (includes substrate, bumps, and probe card), so the deformations are formed. To realize the deformations of the first part of test interface, the analytical simulations are necessary and two common types of first test interfaces are shown in Figure 2 and, respectively. In Figure 2, some components are mounted on the back of probe card for the performance improvements, but the space for the backer design is limited due to these components. In contrast to (d) Figure 2, the probe card in Figure 2 is designed without components and it has a larger design space for backer. In this work, the structure shown in Figure 2 is our prototype and the simulations are constructed based on it. 2.2 Design Concept for Warpage Suppression In general, the deformation of the first interface can be categorized into four types which are shown respectively in Figure 3,,, and (d). The flat deformation of PCB shown in Figure 3 is caused as the test forces are almost equal in all aspects. If the test forces are unequal, the deformations of PCB shown in Figure 3 and are looked like basin and mountain, respectively. When the unequal test forces are getting serious, irregular deformations of probe card in Figure 3(d) is caused. To alleviate the warping phenomenon, an intuitive method is to put some object into the hollow space [4]. The backer is designed with metal therefore it can protect the PCB from the deformations. Thus the warping phenomenon is mitigated or eliminated. 2.3 Backer Design and Optimized Flow for Test- Yield Improvements The backer design and optimized flow is shown in Figure 4, and it is composed of two main parts (simulations and measurements). In the simulation part, this procedure also called general tuning is used to define the geometry and size of metal backer by numerical analyses. After the backer information is known, the probe card with backer can be implemented for the practical wafer test. When the probe card with metal backer is completed, it will be pretest before the practical wafer test. Ideally the warping issue is suppressed by the backer however some non-ideal characteristics are caused in the PCB manufacturing. Therefore the measurement step is used to compensate the non-ideal characteristics. In the measurement part, we will do the wafer contacts, and observe the variations of fail Paper 1.2 INTERNATIONAL TEST CONFERENCE 2

Simulations Part (for Backer Design and General Tuning) Measurements Part (for Fine Tuning) Adjust the Size of Backer Add Overdrive (50 or 100 um) Instable Fail Pins Start Model Construction & Numerical Analysis Deformation Observation (Simulation) Probe Card Implementation (with Backer) Wafer Sort Fail Pins Observation (Measurement) All Pins are Passed Add Patches between PCB & Backer Stable Fail Pins Figure 4 Design and optimized flow of Backer. Probe Card Top View Top View Bumps Hollow Space BGA Top View 1764 Bumps Top View.. Figure 5 The detail information and top views of four main parts are demonstrated. Table I. The material characteristics and dimensions of four main parts of simulated interface. Material Dimensions Thickness Young's Modulus Poisson's Ratio Epoxy Laminate [6] Square 42 x 42 (mm 2 ) 1.8 (mm) 3.2 (GPa) 0.39 Solder Ball SnPb [7] Ball Radius 0.2 (mm) N/A 30.6 (GPa) 0.35 Probe Card Epoxy Laminate [6] Circle Radius 120 (mm) 6.4 (mm) 22.4 (GPa) 0.11 Stainless Steel [5] Circle Radius 120 (mm) 10 (mm) 200 (GPa) 0.31 pins. Then the perfect contacts of all pins are achieved by adding the overdrive and patches. The detail operations of designs and optimizations will be described in the next section. 3. Simulations of High-Density Probing Technology 3.1 Description of Simulated Structure Based on the simulated prototype shown in Figure 2, the detail information of four parts (substrate, bumps, probe card, and stiffener) are described in Figure 5 and Table I. From the top view of stiffener, it is composed of two metal rings and eight rectangular steels with the thickness 10mm. The dimensions of outer and inner rings are designed with the width 20 mm and 10 mm, respectively. The length and width of rectangular steel are 65 mm and 10 mm, respectively. For the probe card in Figure 5, it is a circular plate with the thickness 6.4 mm and radius 120 mm. The ball grid array consists of 1764 bumps, and the radius of each bump is 0.2 mm. The substrate is formed with square shape, and the length of square substrate is 42 mm. Besides the dimensions of simulated structure, the detail datum, such as material, Young s modulus and Poisson s ratio, are described in Table I [5-7]. Due to the information, the simulated structure can be constructed. Paper 1.2 INTERNATIONAL TEST CONFERENCE 3

PCB BGA Figure 6 A quarter of simulated structure. Outer Part includes 5209 Pins Inner Part includes 3076 Pins Outer Part: 2.9 MPa Inner Part: 1.254 MPa Number of Elements 88720 75000 50000 25000 0 0.15 0.25 0.38 0.50 0.63 0.75 0.88 1.00 Element Metrics Figure 7 The detail pins arrangement. 3.2 Structures and Sources Approximations in the Simulations The information of the simulated structure has been explicitly described in the section 3.1. From section 3.1, the simulated structure can be constructed successfully. However, in order to reduce the simulation time, a quarter of structure can be used due to the axis-symmetry characteristics of the simulated structure. Actually, the simulated structure is a quasi-symmetric, but it can be seen as a symmetric structure for convenience. Using this method, the simulation time can be decreased, especially for the ball grid array. In the original structure, 1764 bumps should be meshed and calculated. From axissymmetry method, a quarter of structure is demonstrated in Figure 6 and only 441 bumps have to be analyzed. Thus the memory and simulation time are largely reduced. Besides the structure analysis, the source is also a complicate part in the simulation. The pin arrangements are shown in the left of Figure 7, and two obvious parts, outer and inner parts, can be observed. The outer part includes 5209 pins and the inner part has 3076 pins. The 15 grams force on each tip is added. However it is complicate for us to set the forces (15 grams) on 8285 tips because of too many pin counts. To simplify the settings of sources, the distribution of non-uniform sources is replaced Figure 8 The meshes of bumps and probe card quality. by the distribution of uniform sources. For example, the total force in the outer part is calculated as 78.135 kg and the area of outer part is 264 mm 2. Then the average pressure in the outer part is obtained as 2.9 MPa (also called uniform-sources distribution). For the inner part, 1.254 MPa can be obtained (the force is 78.135 kg and the area is 264 mm 2 ). Using above two simplifications for structure and source, the deformations of structures can be observed and some innovations can be verified. 3.3 Stress Distributions and Deformations To clearly observe the stress distributions and deformations, the mesh arrangement is an important step, especially for the ball grid array and the central part of probe card. The mesh arrangements of them are shown in Figure 8 and, respectively. The mesh quality shown in Figure 8 is higher than the level of 75% (0.75), and it is good for numerical analysis. Then the solved stress distributions of the simulated structure without metal backer are obtained and shown in Figure 9. Two distinct zones, weak and strong zones, can be clearly seen. The weak zone is marked by the blue and the stress is smaller than 3 MPa in this region because of the stress cancellation Paper 1.2 INTERNATIONAL TEST CONFERENCE 4

Shear force Shear force Shear force Weak zone Strong zone stress concentration Figure 9 The stress distributions of a quarter of simulated structure and the central part of probe card. Deformation (mm) 1.10E-01 1.00E-01 9.00E-02 8.00E-02 7.00E-02 6.00E-02 5.00E-02 4.00E-02 3.00E-02 2.00E-02 1.00E-02 Flat Region 0.00E+00 0 10 20 30 40 50 60 70 80 90 100 110 120 Edge Length (mm) Bending Stress concentration Sharp Region Corresponding side view of quarter structure Hollow Space Figure 10 The deformations of probe cards without backer. PCB Backer Figure 11 A quarter of probe card with metal backer. by the stiffener. The stress in the strong zone is higher than 4 MPa basically, and the maximum stress zone marked by red is higher than 13 MPa (13.524 MPa) at the center of PCB because of the stress concentration phenomenon. The detail stress distribution of strong zone is demonstrated in Figure 9. Maximum stresses are still concentrated at the center of structure and the horizontal forces, shear forces, are distributed at the edge of strong zone. It is worth noting that several shapes of the backers, such as square, cuboid, and cylinder, might be designed to suppress the warping phenomenon of PCB, but the preferred backer shape is designed based on the stress distribution. For example, the maximum stress at the center of structure is distributed as a circle in Figure 9, and the backer can be designed with a cylinder. There are two main reasons to select this shape. First, the PCB deformation can be suppressed efficiently by the selected backer. Second, based on the stress distribution, additional metal can be saved in the backer design so the cost can be reduced. The deformation of PCB without backer is shown in Figure 10. As shown in Figure 10, the edge length from 0 to 120 mm also means the radius of PCB, and location of 120 mm represents the center of PCB. Two distinct regions in Figure 10, flat and sharp regions, are observed. In flat region, the deformation is increased from 0 to 0.04 mm gradually, and it has a significant increasing after the edge length of 85 mm. The deformation within the edge length from 0 to 20 mm is smaller than 0.003 mm, and this condition can be mapped to stiffener structure shown in Figure 5. The outer ring of stiffener are situated on PCB during this range, therefore the deformation of PCB can be totally suppressed. After the edge length of 20 mm, the Paper 1.2 INTERNATIONAL TEST CONFERENCE 5

Deformation (mm) 1.10E-01 1.00E-01 9.00E-02 8.00E-02 7.00E-02 6.00E-02 5.00E-02 4.00E-02 3.00E-02 2.00E-02 1.00E-02 0.00E+00 Deformation : 0.1057 mm 0.0677 mm 64% Deformation Deformation : 0.038 mm Sharp Region Flat Region 0 10 20 30 40 50 60 70 80 90 100 110 120 Edge Length (mm) Probe card without backer Probe card with backer Deformation (mm) Sharp Region Flat Region Corresponding side view of quarter structure Edge Length (mm) Backer Figure 12 The deformations of two cases (probe cards with and without backer) detail performance of probe card with backer. curve of deformation is monotonically increased, and the end of increasing is estimated about 0.04 mm at the edge length of 85 mm. Unlike the suppressed ability within the edge length of 20 mm, the suppressed ability from 20 to 85 mm is not good because merely eight rectangular steels are used to prevent PCB from being bent. Therefore around 0.04 mm deformation is caused within this region. After the edge length of 85 mm, the deformation is significantly increased. From Figure 5, no corresponding frames are designed during this range (from the edge length of 85 to 120 mm), so the vertical force caused by wafer test is not counteracted. In addition, the positions of probe tips are located from 108 to 120 mm, so the maximum deformation is caused. As shown in Figure 10, the deformation within the sharp region is increased from 0.04 mm and it has the maximum value of deformation is 0.1057 mm at the edge length of 120 mm. In this work, the variations of probe tips are estimated 0.05 mm therefore the open failure situation is caused in the wafer test. In order to alleviate the open failure problem, a metal backer is added on the PCB and the whole structure is shown in Figure 11. The thickness and optimized radius of backer are designed with 10 mm and the 20 mm respectively and the material of backer is also the stainless steel. The optimized backer design will be introduced in section 3.5. The deformation of the PCB with metal backer is shown in Figure 12 and the deformation of PCB without backer is also included for comparison. As shown in Figure 12, the deformation of PCB with backer is increased gradually and has the maximum deformation 0.038 mm at the edge length of 120 mm. Compared to the result of PCB without backer, the deformation of PCB with backer is largely reduced and the suppressed value is 0.0677 mm (around 64 % suppression). The detail deformation of PCB with backer is shown in Paper 1.2 INTERNATIONAL TEST CONFERENCE 6

5.00E-02 0.004mm Deformation (mm) 4.00E-02 3.00E-02 2.00E-02 1.00E-02 0.0015mm 12MPa 5.2MPa 2.6MPa 2.0MPa Case A with radius 5 mm Case B with radius 10 mm Case C with radius 15 mm Case D with radius 20 mm 10mm 20mm 30mm 40mm 0.00E+00 0 10 20 30 40 50 60 70 80 90 100 110 120 Edge Length (mm) Figure 13 The deformations of the probe cards with four smaller backers. 4.00E-02 3.50E-02 0.005mm Deformation (mm) 3.00E-02 2.50E-02 2.00E-02 1.50E-02 1.00E-02 5.00E-03 16mm Case D with radius 20 mm Case E with radius 25 mm Case F with radius 30 mm Case G with radius 35 mm 40mm 50mm 60mm 70mm 0.00E+00 0 10 20 30 40 50 60 70 80 90 100 110 120 Edge Length (mm) Figure 14 The deformations of the probe cards with four larger backers. Figure 12. As shown in Figure 12, two regions, sharp and flat region are clearly observed. In the sharp region, the edge length smaller than 20 mm is also fixed by the outer ring of the stiffener, so the variation is very slight. After the edge length of 20 mm, the deformation of PCB is increased from 0.002 to 0.038 mm gradually. After the edge length of 100 mm, the deformation is kept at the same level of 0.038 mm because a metal backer is added on the PCB. Although the small deformation of 0.038 mm is caused on PCB, an edge range from 100 to 120 mm is flat enough (the variation is lower than 0.002 mm). Thus the open failure situations can be alleviated due to the better contact in the wafer test. 3.5 Variable Analyses and Discussions The deformations of probe card with smaller backers are shown in Figure 13. As shown in Figure 13, four cases, Case A, B, C, and D, are demonstrated and the radiuses of backers are 5, 10, 15, and 20 mm, respectively. Case D has been introduced in the previous section. The performance of case C is similar to case D, but the flat region and suppression of case D is better than case C due to the larger backer (The Flat regions of case C and D are 15 and 20 mm, respectively. The deformations of case C and D are 0.042 and 0.038 mm, respectively.) Something interesting is observed in case A and B. In Case A, a 5 mm flat region caused at the central part by backer is observed at the center and a fold is formed from 80 to 115 mm. The maximum deformation of fold in case A is 0.051 mm and the peak difference between flat region and fold is estimated 0.004 mm. This phenomenon is caused because the backer is not big enough (the force source is located from 107 to 120 mm), so the PCB during this range (from 107 to 115 mm) is deformed based on the stress concentration. The same situation is happened in case B and the slight peak difference is 0.0015 mm. The simulated vertical forces at the edge of backer in these four cases are 12, 5.2, 2.6 and 2MPa from the Case A to D. As the vertical force is larger than 4.4 MPa, the fold will be caused in the PCB, such as Case A and B. The analyses of bigger backers are shown in Figure 14. As shown in Figure 14, four cases, Case D, E, F, and G, are also demonstrated, and they correspond to the backer radius of 20, 25, 30, and 35 mm, respectively. As different from the results in Paper 1.2 INTERNATIONAL TEST CONFERENCE 7

Patch Backer Figure 16 The fine tuning of backer enhancement by using plastic patches. (d) Figure 15 The variations of fail pins with overdrive 100um 200um 300um (d) 400um. Figure 13, the fold is not happened in the Figure 14 because the sizes of backers are much larger than the area of forced source. In Figure 14, the deformations of four cases are reduced with the radius increasing of backers. About 16 mm of the flat region is improved as the radius of backer is altered from 20 to 35 mm. About 0.005 mm deformation is suppressed as the radius of backer is gradually increased. From the variable analyses shown in Figure 13 and Figure 14, Case D is the better choices. Not only the warping deformations can be suppressed but also the areas are economized. 3.6 Fine Tuning by Using Patches Ideally, the warping issue can be significantly suppressed by the metal backer. It is difficult for the implementations to approach the perfect situations therefore the fine tuning (fine compensation) is necessary. As shown in Figure 4, the wafer contact must be done to find the fail pins out and Figure 17 The decomposition of probe card and backer and the composition of probe card and backer. then the overdrive is added gradually to alleviate the problems of fail pins. The fail-pin variations in part of chip are demonstrated in Figure 15,,, and (d). In the figures, the green pins mean the pass pins, but the red pins represent the fail pins. It is obvious that the numbers of fail pins are decreased with the increasing of overdrive from these four pictures. However seldom fail pins cannot be eliminated by adding overdrive (such as the results in Figure 15(d)). In order to solve this problem, the plastic patches are utilized. As shown in Figure 16, the patches are added between the probe card and backer, and the thickness of patch is 0.025 mm in average. The space formed by warping issue can be filled by patches, so the open fails can be eliminated. After the fine tuning by patch, the perfect contacts of all pins can be achieved and then the real wafer test can be started. 4. Measurements and Discussions 4.1 Probing Results The photos of probe card with optimized backer are shown in Figure 17 and. The contact situations of probe card with backer are shown in Figure 18 and the radius of backer is 5 mm. Three corresponding positions of contact situations on chip, A1, A2 and A3, are shown in Figure 18 and two pictures are included in each area. The contact situation in A1 is shown in Figure 18. It is clear that the probe marks on the C4 bumps are very large and all of them are contacted with the same sizes. It means that the probes within this region are received with the equal forces. The contact situation in A2 is shown in Figure 18. Different from the probe marks in A1, the probe marks in A2 can contacted with unequal sizes. It means that the unbalanced forces are put on the bumps within the Paper 1.2 INTERNATIONAL TEST CONFERENCE 8

A 1 A 2 Picture1 in A2 Picture2 in A2 Yield : 71.88 % Yield : 78.13 % A 3 Picture1 in A1 Picture2 in A1 Picture1 in A3 Picture2 in A3 Good Die Bad Die Good Die Bad Die Yield : 90.63% Yield : 98.44 % Good Die Bad Die Good Die Bad Die (d) Figure 19 The test-yield improvements without backer with backer of radius 5mm with backer of radius 15mm, and (d) with backer of radius 20 mm. (d) Figure 18 The corresponding positions of contact situations on chip the contact situations in A1 the contact situations in A2 (d) the contact situation in A3. A2. The contact situation in the area of A3 is shown in Figure 18(d). The slight probe marks with almost equal sizes are observed. The probe marks shown in Figure 18,, and (d) can be mapped to the Case A in Figure 13. Figure 18 and correspond to the fold region in Figure 13, so the probe marks are clear due to the larger vertical forces. Figure 18(d) can correspond to the flat region in Figure 13. Compared to the fold region, the vertical forces in flat region are relatively low, so the sizes of the probe marks are smaller than fold region. Generally, the probe marks with equal sizes on the same wafer are the better test contacts, but the demonstrated example in Figure 18 is tested with unequal sizes probe marks due to the deformations. Therefore, the open fail will be happened in test due to the contact situations in Figure 18. After processing (increase backer size, overdrive, and patches), the warping and contact problems are solved, and the perfect contacts (with equal-size probe marks) are obtained for wafer tests. 4.2 Test Yield Improvements in Wafer Test The yields of wafer test are shown in Figure 19, and 64 dies are fabricated on the wafer. The green part means the good die and red part means the fail die. The test result of the probe card without backer is shown in Figure 19, and 71.88% test yield is measured (46 good dies and 18 failure dies). As a backer with the radius of 5 mm is added, the test result is shown in Figure 19 and 78.13% test yield is obtained (50 good dies and 14 failure dies). As the radius of backer is enlarged to 15 mm, the result with 90.63 % is tested (58 good dies and 6 failure dies) and shown in Figure 19. Finally, the backer with 20 mm radius is added and 98.44% test yield (63 good dies and 1 failure dies) is calculated in Figure 19(d). It is worth noting that the only one bad die in Figure 19(d) is failed because of the manufacture not test methodology. From Figure 19,,, and (d), the yields are gradually Paper 1.2 INTERNATIONAL TEST CONFERENCE 9

enhanced with the increasing of backer radius. It also corresponds to the results in Figure 13. The flatness is getting better and then the performance of wafer test is also enhanced. 5. Conclusions In order to promote the test yield, the metal backer designed on the back of probe card is introduced and proposed. First, a backer design and optimized flow included two parts (simulations and measurements) is established. In the simulations, the deformation of probe card can be known and the optimized backer size is also obtained from the numerical analyses. In the measurements, the implementation of probe card is calibrated to the situations of perfect contacts by adjusting overdrive and patches and the wafer-map tool provides a fast way to find the fail pins out in each test. Using this flow, the warping issues of the high-density probe card can be alleviated and the wafer contacts are also good. Then the pictures of probe marks in chip probing are also provided to validate the corrections of simulations and describe the corresponding physical phenomena in test. Finally, the practical test results are demonstrated and the test yields of wafers are increased gradually as our predictions by simulations. 26.56% test- yield improvement is obtained as the optimized backer is used. It is worth mentioning that the backer can be used not only on the original probe but also the applied on the directdocking probe card. Even the backer enhancement in 3DIC test still plays an important role. 6. References [1] International Technology Roadmap for Semiconductor (ITRS), The Roadmap in Assembly & Packaging. [online]. Available: www.itrs.net [2] S. Raghavan, K. Klein, S. Yoon, J.-D. Kim, K.-S. Moon, C.-P.Wong, and S. K. Sitaraman, "Methodology to Predict Structure Warpage and Different Techniques to Achieve Warpage Targets", IEEE Trans. Compon. Packag. Manuf. Technol., vol. 2, no. 7, pp. 1064-1074, Jul. 2011. [3] P. Yang, Z. Chen,"Experiment Approach and Evaluation on Dynamic Reliability of PBGA Assembly," IEEE Trans on electron devices, vol.56, no.10, pp. 2243-2249, Oct. 2009. [4] L. Dibattista and D. Lam, Verigy V93000 direct probe TM evaluation of the Verigy V93000 SOC tester in wafer probing, Advantest, Inc. [5] Ansys Workbench, Ansys, Inc. [online]. Available: www.ansys.com [6] Mitsui Kinzoku ACT Corporation. [online]. Available: www.oakmitsui.com/uploads/news_43342mrg%20s eries.pdf [7] Profound material technology., ltd. [online]. Available: www.pmtc.com.tw/c/prod_sbn.php Paper 1.2 INTERNATIONAL TEST CONFERENCE 10