NANOMANUFACTURING TECHNOLOGY NAS/SSSC Spring Meeting April 2, 2009
Moore's Law and Transistor Scaling Bits/Chip 1T 45nm 90nm 1G 0.25um 1um 1M 1K 1975 1985 1995 2005 2015 DSP AA Battery Hours 100 50 0 0 Speech Video 0.2 0.4 0.6 0.8 Year Technology (um) Decrease transistor dimensions by k, drop voltage by k Circuit area reduced by 1/k2, speed increased by k Power per circuit reduced by 1/k2, power per area constant 2
Moore's Law and Transistor Cost 1B Number of Transistors (x Billions) 1M 1K 1 Cost per Transistor (Nano $) 1968 1973 1978 1983 1988 1993 1998 2003 2008 (Source: G. Moore, ISSCC 2003) 3
A Recent Product Enabled by Nanoelectronics x ~ 1000 IBM 370/195 1975 = $1B 2006 ~ $200 2020 = 5 * Memory cost only * Extrapolating memory cost reduction factor over last 30 years and display cost/area over last 10 years 4
Cost Per Function Process Cost Cost Area Area Cost Cost Function (Good) (Good) Function Area Area 5
Cost Per Function: VLSI Technology Process Cost Cost Area Area Cost Cost Function 193nm SADP (Good) (Good) Function Area Area Scaling has been the primary cost driver for ICs but not at an overcompensating increase in process cost/area 6
Patterning Is More Than Printing PRODUCTIVITY Automation ediagnostics Material Handling Reticle Management PREPARATION Patterning Films CVD Hardmask CVD ARC/Spin-on ARC PVD Hardmask Planarity Enhancement Ecmp Real-Time Profile Ctrl Fixed-Abrasive CMP PRINTING Scanner Track Mask/Mask Etch Photoresist K1 reduction PATTERN T RANSFER Etch High Aspect Ratio Etch Critical Etch Damascene Etch Trimming PROCESS CONTROL/DFM CD SEM OPC Qualification APC 7 Defect Inspection and Review Overlay
Self Aligned Double Patterning LER = 3.1nm (3s) LER = 1.5nm (3s) 8
Progress Through Materials Innovation Source: Intel ISTAC Meeting 2-2004 9
Integrated Hi-k/Metal Gate CMOS Metal Gates for nmos and pmos Hi-K layer for low leakage Graded transition layer High mobility interface layer 10
Require Nanoscale Resolution and Throughput 35nm void 30nm defect 18000 16000 14000 12000 10000 8000 6000 4000 2000 0 Defects Reviewed Per Day at a Leading Fab 1996 1998 2000 2002 2004 Throughput (300mm WPH) New Tool Existing Tool Pixel = 80nm 120nm 160nm 220nm 270nm 11
Two Key Semiconductor Market Trends Semiconductor content in electronics, units and transistors all continue to increase but: Accelerated consolidation of wafer manufacturers Foundries vs. IDMs Memory oversupply Process R&D costs Fewer product families aggressively follow Moore's law Application drivers Developing economies Performance compromises Design costs Feature Size Industry: Scaling Trends Analog Consumer Logic DRAM NAND, DSPs, µprocessors, GPUs Year 12
Promise of Nanotechnology European Commission, Nanotechnology Innovation for Tomorrow s World, Research DG, 2004. 13
Nanomanufacturing Technology Small features on a large production scale Scale Up? Additional Innovation Placing a nanotube? More Than Nanofabrication Repeatable, Robust, Reliable, Controllable and Cost Effective 14
Flat Panel Display (LCD) Manufacturing LCD Industry Revenue ($B) Production Cost per Area (k$/m 2 ) 120 100 80 100 10 2011 60 ~$1000 60 40 20 1 2004 20 ~$1000 2008 42 ~$1000 0 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 0.1 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 > 20% Bigger (HD)TV Every Year for the Same Price 15
Cost Per Function: Flat Panel Displays Process Cost Cost Area Area Applied PECVD 5.7 Cost Cost Function AKT-PIVOT 55KV PVD (Good) (Good) Function Area Area Courtesy Sharp Cost per area tends to be an equivalent or predominant factor in applications other than VLSI 16
Flat Panel Display Equipment PECVD Gen 10 AKT-90K PECVD 1st Release Gen 2 Gen 3 / 3.5 Gen 4 Gen 5 Gen 5 Gen 5.5 Gen 6 Gen 7 / 7.5 2/ '93~ 4/ '95~ 1/ '00~ 8/ '01~ 6/ '02~ 8/ '04~ 5/ '03~ 7/ '04~ Gen 8 2006 System Layout ACLS ACLS ACLS ACLS ACLS Model Substrate Size (mm) Substrate Area 1600 370x470 400x500 2,000 cm2 (1.00) 3500 / 4300 / 4300A 550x650 600x720 620x750 4,650 cm2 (2.33 from 1600) 5500/5500A 680x880 730x920 6,716 cm2 (1.44 from 4300) 10K 1000x1200 12,000 cm2 (1.79 from 5500) 15K / 15KA 1100x1250 1200x1300 15,600 cm2 (1.30 from 10K) 20K 1300x1500 19,500 cm2 (1.25 from 15 K) 25K / 25KA 1500x1800 1500x1850 Gen 10 = 60nm uniformity over ~ 10 19 27,750 cm2 (1.78 from 15 K) 40K / 40KA 1870x2200 1950x2250 41,140 cm2 (1.52 from 25 K) 50K 2160x2460 nm 2 area at 50sph 19 nm 53,136 cm2 (1.21 from 40 KA) 17
Nanotechnology Opportunities In Energy Energy Conservation Energy Conversion Energy Storage Technology to improve performance, form and cost 18
Architectural Coated Glass Cost Reductions Achieved with Low-e Coatings San Antonio Phoenix 700 600 500 400 300 Annual Energy Expenditures ($) Low-e Coatings 2000 ft2 house with 300 ft2 of windows 19
Increasing Adoption of Coated Glass Bird s Nest Stadium (Beijing) Shanghai SYP Engineering Glass Co. 10,000m 2 of high performance Low-E glass Burj Dubai (UAE) Guardian Industries 100,000m 2 SunGuard Solar Control and Low-E coated glass Main Triangle Building (Frankfurt) Guardian Industries 15,000m 2 SunGuard Solar Control and Low-E coated glass House of Sweden (Washington DC) AGC Flat Glass 5500m 2 Stopray Elite and Stopray Carat glass Savings from 2007 Global Output ~ 36,000 Bbl/day Equivalent to 12 oil wells or 18Mt CO 2 20
Large Area Glass Coating Systems Glass Substrate is ~ 2.6 m x 3.6 m Uniformity Spec of +/- 1% on 275 nm film (10 layer Triple Low e stack) 18 Chamber System ~ 90m: one panel every 20 sec Output per month ~ 7Mft2 21
Electrochromic "Smart Glass" Key Requirements for Market Adoption: Performance: Energy efficiency, lifetime Form: Color selection, match non-ec panes, pane-to-pane consistency, large size panes, on-off Cost: At least comparable to Low-e glass + shades Typical Structure ~ 10 metal/dielectric layers, most < 100nm thick (up to ~ 500nm) 22 Images courtesy of Sage Electrochromics
Primary Commercial Solar PV Markets Residential Commercial Rooftop Utility Scale Today s Installed Base 5.4 GW Market Drivers High utility bills Availability of incentives Green choice Today s Installed Base 4.2 GW Market Drivers High utility bills Unpredictable cost Under-utilized urban space Today s Installed Base 5.4 GW Market Drivers Solar economics Favorable tax policy Unpredictable fuel and carbon costs Total new PV installations in 2008 ~4.1 GW Source: Navigant 2007, 2008, Marketbuzz 2008 23
Mainstream PV Technologies Crystalline Silicon Preferred for residential applications Thin Film Preferred for large scale applications Common focus to drive down cost per watt 24
Solar Learning Curve: Module Cost/Watt Module Price (2006 $/Wp) $100 $10 Historical Prices (csi dominated) 1980 c-si Polysilicon shortage 2007 $1 1 10 100 1,000 10,000 100,000 1,000,000 Production line size (Megawatts per Year) Lines Per Factory 0.5 (1980) 2 > $1 per kwh equivalent PV electricity cost Thin Film 2007 $1.00/W @ <20 GW Cumulative Production (MWp) 5 (2000) 3 50 (2005) 4 100 (2010) 10 Cost Watt = Cost / m 2 Watt / m 2 $1.00/W @ >100 GW 25 Source: Adapted from NREL
Crystalline Silicon PV Value Chain Poly-Si Poly-Si Feedstock Feedstock Ingot Production Wafer or Sheet Production Cell Production Module Assembly Distribution, Integration & Installation MC Cz 26
Improve Material Efficiency: Thin Wafers $0.52 / Wp* $0.46 / Wp* $0.42 / Wp* $0.34 / Wp* Kerf Loss Cost / m 2 Wafer Thickness Watt / m 2 27 * Cost assumes fixed silicon costs at $55/kg and constant efficiency
High Productivity ARC/Passivation Cost / m 2 Watt / m 2 Applied ATON PVD Yield Thruput Uptime Thin wafers COC Lifetime (µsec) 4000 3000 2000 1000 0 Nitride Composite Stack Efficiency Uniformity Low Interface State Density Optically Transparent Stable After Contact Firing 28
Thin Wafer Processing 29
Thin Film PV Value Chain Wafer or Sheet Production Cell Production (Si, CdTe, CIS) Module Assembly Distribution, Integration & Installation FOV: 200.0 µm 10.000 kev 50.0 µm 139 flexi-solar 11/29/2007 30