CHAPTER 2 CMOS Processing Technology
Outline 2 1. CMOS Technologies 2. Layout Design Rules 3. CMOS Process Enhancements 4. Technology-related CAD Issues 5. Manufacturing Issues
CMOS Technologies 3 n-well Process : p-substrate p-well Process : n-substrate Twin-well Process Optimized for each transistor type Triple-well Process (deep n-well) Good isolation between analog & digital blocks BiCMOS Process (SiGe) Silicon-on-insulator (SOI) Process
Process Steps 4 Wafer formation Photolithography Well and Channel formation Isolation Gate oxide Gate & Source/Drain formation Contacts & Metalization Passivation
Photolithography 5 Greek: Photo(light)+lithos(stone)+graphe(picture) Resolution enhancement techniques Optical proximity correction (OPC) : local distortion, Phase shift masks (PSM): light diffraction, Off-axis illumination (OAI): contrast enhancement of repetitive pattern. Carving pictures in stone using light http://nano.nchc.org.tw/dictionary/optical_lithography.html
Well and Channel Formation 6 Vary portions of donor(n) & acceptor(p) Epitaxy: single-crystal film growth Deposition: Chemical Vapor Deposition (CVD) + Drive-in Implantation: ion implantation + diffusion + anneal (standard well and source/drain definition)
Schematic and Layout of CMOS Inverter 7
Cross Section of CMOS Inverter 8
Photomasks of n-well CMOS Inverter 9
n-well CMOS Process - 1 10 (a) Define n-well diffusion (mask #1) (b) Define active regions thin oxide (mask #2) (c) LOCOS oxidation field oxide (d) Polysilicon gate (mask #3)
n-well CMOS Process - 2 11 (e) n+ diffusion (mask #4) (f) p+ diffusion (mask #5) (g) Contact holes (mask #6) (h) Metallization (mask #7)
Cross-Sectional Diagram of MOSFET 12
Silicon Dioxide (SiO 2 ) 13 Wet oxidation Oxidizing atmosphere contains water vapor, Temp: 900~1000 o C, quick for thick oxides. Dry oxidation Oxidizing atmosphere is pure oxygen, Temp: ~1200 o C, highly controlled thin oxides. Atomic layer deposition Thin chemical layer deposition for various requirement (SiO 2, metal, dielectrics)
Isolation : LOCOS 14 LOCOS : Local Oxidation of Silicon Low density, high electrical field : bird s beak
Isolation : STI 15 STI : Shallow Trench Isolation High density & better isolation, need Chemical Mechanical Polishing (CMP) to planarize the structure.
Gate Oxide 16 Shorter gate L thinner gate oxide EOT : Effective Oxide Thickness Use stack gate structure with high-k dielectric to decrease EOT. Dual gate oxide for core and I/O.
Gate & Source/Drain Formation 17 Self-aligned polysilicon (poly) gate Lightly doped drain (LDD) structure
LDD & Salicide 18 LDD Reduce electrical field of drain junction & hot-electron damage High sheet resistance Salicide : self-aligned silicide Refractory metal to reduce the interconnection resistance of gate, source/drain. CMP : Structure planarization for further stack process.
Chemical Mechanical Polishing (CMP) 19
Contacts & Metallization 20 Contact VIA Metal Poly, Metal Diffusion Metal Metal CMP : Structure planarization for further stack process.
Outline 21 1. CMOS Technologies 2. Layout Design Rules 3. CMOS Process Enhancements 4. Technology-related CAD Issues 5. Manufacturing Issues
Layout Design Rule 22 Design rule: geometric constraint and tolerance for high probability of correct fabrication. Feature size, separations and overlaps. Well rule : isolation Transistor rule : channel quality Poly, active region, n+/p+ implant. Contact : single size for precisely process control Metal & Via rule: productivity & conductivity Top metal with loser size, space and via rules.
N-well Process Transistor 23
Design Rule 24
Micron Design Rule 25
Outline 26 1. CMOS Technologies 2. Layout Design Rules 3. CMOS Process Enhancements 4. Technology-related CAD Issues 5. Manufacturing Issues
CMOS Process Enhancement 27 Multiple threshold voltage & oxide thickness Low core voltage for low power High I/O voltage for interface compatibility Silicon on Insulator : higher speed High-K gate dielectrics : thinner EOT Higher mobility : SiGe BJT, strained silicon Low-leakage transistor : finfet, gate-all-around (GAA) FET Plastic Transistors : flexible electronic paper High-voltage transistor : LCD driver, power electronics Copper interconnection : high conductivity Low-K dielectrics : low wire capacitance
Silicon on Insulator 28 Pros. No capacitance between source/drain and body higher speed device. No Latch-up. Cons. Floating body history effect Self heating effect. Parasitic BJT pass-gate leakage
High-K & Higher Mobility 29 SiGe bipolar transistor Strained Silicon High-K + Metal Gate Mark Bohr, The New Era of Scaling in an SoC World, Plenary session, ISSCC 2009
FinFET & GAA Structure 30 Mark Bohr, The New Era of Scaling in an SoC World, Plenary session, ISSCC 2009
Transistor Scaling 31 http://isscc.org/media/2012/plenary/david_perlmutter/silverlightloader.html
Intel Technology Trend 32
Plastic Transistor 33 Electronic Paper Plastic transistor structure & process flow
Copper Interconnect 34 Copper atoms diffuse into the silicon and dielectrics, destroying transistors Barrier layers are necessary The processing required to etch copper wires is tricky. Copper oxide forms readily and interferes with good contacts. Care has to be taken not to introduce copper into the environment as a pollutant
Copper Damascene Process 35 Pros. : High conductivity Cons. :Complex process
Capacitors 36 MiM Capacitor Fringe Capacitor
MIM vs. MOM 37 Metal-Insulator-Metal Need extra layer More routing capability Metal-Oxide-Metal Free with modern process More layers : higher density
Resistor & Conductor 38 Non-silicide high-resistivity Poly resistor Planar spiral Inductor
Memory Category 39
Non-Volatile Memory (NVM) 40 Mask-programmed ROM (Read-Only Memory) NOT programmable after manufacture. One-Time Programmable (OTP) memory Fuse constructed programming flow EPROM: Electrically Programmable ROM Electrical Programming, UV Erase EEPROM: Electrically Erasable PROM Electrical Programming & Erase, Byte-level programming. Flash Block-level programming, faster & cheaper than EEPROM
Flash Memory 41
BJT in CMOS Process 42 Usage : bandgap voltage reference
MEMS 43 Micro Electro Mechanical Systems (MEMS) Comb drive Actuator
Carbon Nanotube (CNT) Transistor 44 IBM CNTFET Smaller channel length Higher speed Lower power Better electrical performance than Si but complex process
Outline 45 1. CMOS Technologies 2. Layout Design Rules 3. CMOS Process Enhancements 4. Technology-related CAD Issues 5. Manufacturing Issues
Design Rule Check (DRC) 46 Tolerate nonideal effects and guarantee device successful fabrication: Mask alignment error Shift SiO 2 PMOS Region SiO 2 SiO 2 PMOS Region SiO 2 n well n well p substrate p substrate SiO 2 p+ Poly SiO 2 SiO 2 p+ Poly SiO 2 p+ p+ n+ p+ p+ n+ n well p substrate Short n well p substrate Ex: alignment of N well and active region masks
Design Rule Check (DRC) 47 Exposure and etching variation Ex: different contact windows different contact resistance Contact widows SiO 2 SiO 2 P+ P+ N+ N well P substrate Two types of design rules Poly overlap Resolution Minimum width Minimum spacing Contact overlap Poly-diff. spacing Alignment Poly-contact spacing Contact overlap
Design Rule Check (DRC) 48 Minimum channel width CO.W.1 + 2 CO.E.1 Minimize S/D diffusion width (x d ) CO.W.1 + CO.E.1 + CO.C.1 x d x d
Layout v.s. Schematic (LVS) 49 Guarantee the layout is the same as the simulated netlist Check device parameters, interconnections and i/o ports. Model name Channel width Channel length VDD VDD VI VO VI VO GND GND
Parasitic Extraction (PEX) 50 Evaluate interconnection RC effects VDD VDD VDD VDD VI VO VI VO VI VO VI VO GND GND GND GND Only C effect Only R effect
Gate Layout Slide 51 Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology V DD and GND should abut (standard height) Adjacent gates should satisfy design rules nmos at bottom and pmos at top All gates include well and substrate contacts
Example: Inverter Slide 52
Simplified λ-based Design Rules 53
Example: NAND3 54 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 V DD rail at top Metal1 GND rail at bottom 32 l by 40 l
Stick Diagrams 55 Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers
Wiring Tracks 56 A wiring track is the space required for a wire 4 l width, 4 l spacing from neighbor = 8 l pitch Transistors also consume one wiring track
Well spacing 57 Wells must surround transistors by 6 l Implies 12 l between opposite transistor flavors Leaves room for one wire track
Area Estimation 58 Estimate area by counting wiring tracks Multiply by 8 to express in l
Example: O3AI 59 Sketch a stick diagram for O3AI and estimate area Y A B C D
Example: O3AI 60 Sketch a stick diagram for O3AI and estimate area Y A B C D
Outline 61 1. CMOS Technologies 2. Layout Design Rules 3. CMOS Process Enhancements 4. Technology-related CAD Issues 5. Manufacturing Issues
Antenna Rules 62 Maximum area of metal connected to gate without discharge element
Layer Density Rule 63 CMP & Uniform etch process requirement : Planarization Solution : Pattern Fill (by CAD) Reference: http://www.edadesignline.com/howto/198100760;jsessionid=ewgkeu5kzkdcvqe1ghpskh4atmy32jvn?pgno=2