ELEC 6740 Electronics Manufacturing Chapter 5: Surface Mount Design Considerations R. Wayne Johnson Alumni Professor 334-844-1880 johnson@eng.auburn. @eng.auburn.eduedu
Outline System Design Issues Package Drivers Real Estate Considerations Manufacturing Considerations Cost Considerations Thermal Considerations Package Reliability Considerations Solder Joint Reliability Considerations Interconnect Considerations CAD Layout Considerations
System Design Form, fit and function! Form! Fit! Relates to the physical size, shape, and weight of the product! Factor constraints: MULTIBUS I, MULTIBUS II, PC BUS! Slot spacings,, connectors, etc.! Relationship with other functions or products within the system! Function! Products basic mission in life
System Design Application environment Cost constraints
Package Drivers High End Performance Driven Mid-Range Cost/Performance Driven High Electrical & Thermal Performance High performance & Lower cost packages SMT Technology, Cheaper Assembly cost to OEM Package Requirements Narrow pad pitches Decoupling capacitors PGA, BGA, Flip Chip, MCM Thermally enhanced Plastic packages SMT, CPGA, PQFP, PPGA, BGA Entry Level Cost Driven Cheap! Packages Thin and small outline packages For notebooks & chipset applications Low cost plastic QFPs, TSOP, BGA
Microprocessor I/O
Cost Package Drivers! Cost per I/O Thermal! Plastic vs. Ceramic! Heat sinks, slugs Electrical! Parasitics! Propagation delay! Signal distortion! Electrical noise Real Estate! Perimeter vs. area array
PGA Area array Through hole Robust leads Sockets Known reliability
Fine Pitch Packages QFP Real estate Lower cost vs PGA 2-4 watts with heat slug
BGA Area array real estate Robust manufacturing process No repair, only rework Inspection, X-ray only
Real Estate Type of SMT Assembly Type III SMT Functional Density Increase 1.05x 1.10x Type II SMT 1.20x 1.40x Type I SMT 2.00x 4.6x
Real Estate A = {(a 1 + I 1 )n 1 +(a 2 + I 2 )n 2 +(a 3 + I 3 )n 3 + } K+M A = real estate area requirement a 1, a 2, = land pattern areas of different components I 1, I 2, = interpackage spacing requirements n 1, n 2, = total number of each component K = packing efficiency constant! 1.10 for memory board! 1.30 for logic board M = reserved area required for miscellaneous purposes such as clearance for edge card guide, automated test assess, etc.
Land pattern/package and interpackage spacing
Land pattern/package and interpackage spacing
Manufacturing Ease of manufacturing! Inspection, test, repair Manufacturing capability Component compatibility with assembly process
PWB Cost
PWB Cost Pitch Ball Dia. Pad Dia. 6/6 5/5 (mil) 60 30 30 2 2 50 30 25 1 2 40 25 25 0 1 20 4 4 0 1
Blind & Buried Vias
PWB Cost
Board Area & Layer Count
PWB Hole Costs
Component Cost CSP more expensive PGAs more expensive Ceramic more expensive
Assembly Cost Type of Assembly Through Hole Type III SMT Type II SMT Type I SMT Savings in Placement Cost 0 0 19% 30%
Thermal Design T j = (Θ( ja x P d ) +T a T j = junction temperature ( o C) Θ ja ja = thermal resistance, junction to ambient ( o C/W) P d = power dissipation at T j (W) T a = ambient temperature
Thermal Design
Ceramic Packages
Thermal Performance
Air Flow
Thermal Resistance (Θ ( ja ja) Type of Package DIP 20 pin Lead Frame Material Kovar Thermal Resistance ( o C/W) 68 SOIC 20 pin Copper 97 PLCC 20 pin Copper 72
Max Power Rating
Package Reliability IPC Electronics trade association! www.ipc.org EIA Electronic Industries Association! www.eia.org JEDEC Joint Electron Device Engineering Council! www.jedec jedec.org
Package Cracking During Reflow Assembly Ratio of paddle size to minimum plastic thickness Quantity and distribution of moisture absorbed by the package prior to surface mounting Maximum package temperature during solder reflow/rework Adhesion of molding compound to die, lead frame, and other internal elements Mold or potting compound material properties CTE mismatch between different materials used in the package Component assembly mold process Die Fabrication and wire bonding process (cratering only)
Pop Corning
During Reflow
Moisture Absorption
Moisture Absorption & Desorption
JEDEC Classification
JEDEC Moisture Sensitivity Level Floor Life Soak Conditions Time Time (hrs) Conditions 1 <30 o C 85%RH 2 <30 o C 60%RH 2a <30 o C 60%RH Unlimited 168 85 o C 85%RH 1 year 168 85 o C 60%RH 4 weeks 696 30 o C 60%RH 3 <30 o C 60%RH 168hrs 192 30 o C 60%RH Joint IPC/JEDEC Standard J-STD-020A
JEDEC Moisture Sensitivity Following soak, parts are subjected to 3 reflow cycles Issue! Eutectic Sn/Pb or Lead Free Inspected:! Electrical! Visual for cracks! Acoustic microscopy for delamination
Inspection Cracks are not allowed to intersect the wire bond, ball bond, or wedge bond. Cracks are not allowed to extend from any lead finger to any other internal feature (lead finger, chip, die attach paddle). Cracks are not allowed to extend more than 2/3 the distance from any internal feature to the outside package
Packages & Humidity & Temperature
Packages & Humidity & Temperature
Plastic Thickness & Die Attach Pad Area
Handling Shipped in Dry Bags Desiccant materials Humidity indicator card 6 month shelf-life if unopened
Packaging
Bake Out
Bake Out Temperature! 125 (+5)( o C Duration! 24-25 hours Chamber RH! <50% Limited re-bake! 15-20µin Cu-Sn intermetallic Temperature! 40 (+5, -0) o C Duration! 192 hours (min.) Chamber RH! <5% Unlimited re-bake
Solder Joint Reliability Solder Joint Failure! CTE mismatch between PWB and component! Compliance of lead Corrosion
Solder Joint Reliability Type III Type I Type II Random Vibration Pass Pass Pass Mechanical Shock N/A Pass Pass Humiodity Storage Pass Pass Pass Temperature Cycling (operating) N/a Pass Pass Temperature Cycling (non-operating) Pass Pass Pass Life Test Pass Pass Pass Total Solder Joint Cycles 210,000 580,000 1.3 million
Environmental Test Conditions Random Vibration! 0.01g 2 /Hz sloping to 0.01g 2 /Hz from 20Hz to 1kHz Mechanical Shock! 50g sine for 11ms Humidity Storage! 5 days at 55 o C, 95%RH Temperature Cycling (operational)! -15 to 70 o C for 5 days Temperature Cycling (non-operational)! -40 to 125 o C; 2500 cycles Life Test! 3000 hours at 60 o C
Environmental Test Conditions www.jedec jedec.org
Thermal Cycling & Thermal Shock Dwell times and ramp rates are important Fatigue: cycling strain loading Creep: constant stress loading Solder joint failure includes both fatigue and creep! The degree of each is a function of the cycle conditions Cycles to failure in the field are always less than in laboratory tests! Less hold time at hign temperature! Less stress relaxation
Stress Strain No Dwell Time
Stress Strain Complete Stress Relaxation
Number of Cycles to Failure The area of the hysteresis loop is a measure of the fatigue damage per cycle Cyclic fatigue damage is cumulative The larger the hysteresis loop, the fewer cycles to failure
Thermal Cycle Profile
Interconnect Connection to Power and Ground Planes Propagation Delay Cross-talk! Line width and spacing! Line length! Dielectric constant! Distance from ground plane
Cross Talk
CAD Parts library Automated layout Design rule checking