LTCC SYSTEMS and LTCC DESIGN RULES Low Temperature Co-fired Ceramic revision status: G page 1 of 19
Table of Contents: 1 General page 3 2 Commercial LTCC tape systems page 4 3 Design possibilities page 6 4 Specific design rules Du Pont 951 page 7 4.1 Design rules in detail page 8 4.2 Materials guide for vias and conductors page 11 4.3 Parameters of the finished products page 12 5 Specific design rules Du Pont 9K7 page 14 5.1 Design rules in detail page 15 5.2 Materials guide for vias and conductors page 18 5.3 Parameters of the finished products page 19 revision status: G page 2 of 19
1 General From available material systems in the market, VIA has qualified and released the following systems: DuPont 951 DuPont 943 DuPont 9K7 Ceramtape GC Heraeus CT 700 These are lifted out in the overview. For these systems, the necessary materials are usually in stock. As a standard material, DuPont 951 is used due to the extensive experience with it. The following design rules are not applicable to all systems, in particular to distinguish the available strengths of the green sheet, shrinkage and process characteristics, and the availability of different metallizations and functional materials (resistors, capacitors). These design rules are referring to above mentioned material system. revision status: G page 3 of 19
2 Commercial LTCC tape systems Table 2.1: Commercial LTCC systems overview Commercial LTCC materials Parameter unit DuPont 951 DuPont 943 DuPont 9K7 ESL 41110 permittivity 7.8 @ 3GHz 7.4 @ 40GHz 7.1 @ 40GHz 4.7 @ 1GHz tan δ 10-3 6 @ 3GHz 2 @ 40GHz 1.5 @ 40GHz < 4 insulation resistance @ Ω > 10 12 > 10 12 > 10 12 > 10 12 100VDC breakdown voltage V/µm 1000/25 1100/25 1100/25 >1500/25 insertion loss 1-20 GHz db in -1 < 1.4 < 0.3 < 0.3 < 0.4 unfired thickness µm 50 ± 3 114 ± 8 51 ± 4 127 ± 9 127 ± 9 100-130 165 ± 11 254 ± 13 254 ± 13 254 ± 14 X,Y shrinkage % 12.7 ± 0.3 9.5 ± 0.3 9.1 ± 0.3 15 ± 1 Z shrinkage % 15.0 ± 0.5 10.3 ± 0.5 11.8 ± 0.5 16 ± 2 conductor metal Ag Ag Ag Ag TEC K -1 5.8 6.0 4.4 6.4 fired density g/cm 3 3.1 3.2 3.1 2.3 thermal conductivity W/m K 3.3 4.4 4.6 2.5-3 flexural strength MPa 320 230 230 NG young modulus GPa 120 150 145 NG Table 2.2: Commercial LTCC systems overview, Ferro. Commercial LTCC materials Parameter unit Ferro A6M-E Ferro A6-S Ferro L8 Ferro A6 permittivity 5.9 @ 100 GHz 5.9 @ 100 GHz 7.3 ± 0.2 @ 5.9 @ 20GHz 3GHz tangent (tan δ) 10-3 <2 <2 1.6 @ 3GHz <2 bulk resistivity Ω/m 3 > 10 12 > 10 12 > 10 12 > 10 12 breakdown voltage > 5000 V/Layer NG > 1250 V/mil NG unfired thickness µm 127 NG 62.5 NG 254 250 X,Y shrinkage % 15.4 ± 0.3 15.7 13.6 ± 0.3 5.5 ± 0.15 Z shrinkage % 24.0 ± 0.3 26 17 ± 0.3 27 conductor metal Ag Ag Ag, Au Ag TEC K -1 7 >8 5.8 7 fired density g/cm 3 >2.45 2.45 3.1 2.45 thermal conductivity W/m K 2.0 2.0 3 NG flexural strength MPa 170 >160 >275 NG young modulus GPa 92 NG 113 NG revision status: G page 4 of 19
Table 2.3: Commercial LTCC systems overview, Ceramtec, Heraeus. Parameter unit Ceramtape GC Commercial LTCC materials Heraeus CT700 Heraeus CT707 Heraeus CT765 Heraeus CT2000 Heraeus CT800 permittivity 7.9 @ 1GHz 7.5-7.9@ 1GHz 6.45 @ 64GHz 68.7 @ 20GHz 9.1 @ 20GHz 5.2 ± 0.2 @ 20-100GHz tangent (tan δ) 10-3 < 2 @ 1GHz < 2.1 @ 1-20GHz 4 @ 64GHz 1.7 @ 20GHz < 2 @ 20GHz < 0.2 @ 100GHz bulk resistivity Ω/m 3 10 14 > 10 12 NG NG > 10 12 - unfired thickness µm 40-60 100 125 127 ± 9 200 125 324-396 320 200 254 ± 14 conductor metal no inks Ag Ag Ag Ag TEC (20-300 C) K -1 4.9-5.7 6.7 7.6 12.9 5.6 5.5 thermal W/m K 1.2 3.2 3-5 NG NG 2 3 - conductivity fired density g/cm 3 2.87 2.97 NG 3 NG NG 3.26 shrinkage X,Y % 21.4 ± 0.5 14.4 17 ± 0.5 19.3 ± 0.5 NG 14.1 ± 0.5 shrinkage Z % 18 ± 0.5 14.9 28 ± 4 28.9 ± 4 NG 30.0 ± 4.0 flexural strength MPa 170 NG NG NG NG > 160 NG: not given in the data sheet. revision status: G page 5 of 19
3 Design possibilities Figure 3.1: Integration possibilities of the LTCC process and indication of naming and parameters for design rules. revision status: G page 6 of 19
4 Specific Design Rules DuPont 951 Table 4.1: Overview of substrate sizes and shrinkage Standard 6 x 6 Special 8,375 x 8,375 substrate size for registration holes etc. enlarged usable for test structures etc. usable area for circuits green 152,4 mm fired 132,6 mm - - - - green 138 mm fired 120 mm Theoretical shrinkage in x, y = 12,7 ± 0,3 % Theoretical shrinkage in z = 15,0 ± 0,5 % green 222,3 mm fired 194,2 mm green 198,4 mm fired 173,3 mm green 175,4 mm fired 153,2 mm Figure 4.2: Sheets showing usable area and alignment and post processing structures revision status: G page 7 of 19
4.1 Design rules in detail Du Pont 951 (values in µm except otherwise defined) Table 4.1.1: Design rules for LTCC process at VIA: BASIC DESIGN RULES Standard (sintered) Special (sintered) line width in µm > 100 > 80 line spacing in µm > 100 > 70 line pitch in µm > 250 > 150 outer edge to feature > 200 < 200 nach Vereinbarung cavity edge to feature > 200 > 100 via diameter in µm 150 100 via cover pad / catch pad in µm 250 150 Cover pad spacing in µm 100 70 (dependent on ink and density) via spacing in µm 1) 175 150 via/cover pad pitch in µm 275 220 via geometry Round Round via center to edge in µm 1) 325 225 via type staggered stacked < 3 Stacked > 3 thermal via diameter in µm < 440 600 thermal via pitch in µm 640 800 thermal via coverage in % 30 50 ground/power plane coverage in % 75 100, size limited opening for feed through in µm 1) 500 400 (spacing cover pad to mesh) post fired resistors min. resistor dimension in mm 1 x 1 0,3 x 0,3 min. resistor overlap in µm 300 150 min. width after trimming, in µm 300 200 resistor geometry form of trim cut Shaving value in Ω/ 10-1 M in decades tolerance after trimming in % ± 3 ± 1 TCR in ppm/ K ± 150 ± 100 co-fired resistors buried resistors buried capacitors available on request, limited technical properties available on request, limited technical properties available on request, limited technical properties revision status: G page 8 of 19
1) for Via diameter: 175 µm Table 4.1.2: Design rules for LTCC process at VIA: Standard (sintered) Special (sintered) dimensions, accuracy and alignment position tolerance (green/fired) ± 0,2 % ± 0.05 % singulation tolerance laser scribing singularized laser cutting bricketting (cutter blade) dicing saw- Milling + 150 µm / -50 µm + 50 µm ± 100 µm ± 50 µm ± 50 µm max. number of layers 15 >15 min. number of layers 4 < 4 combinations of tape thickness 200 135 100 lot to lot thickness tolerance 3% 200 135 100 35 circuit shapes rectangular, square circular, others thickness in µm 400 1200 < 400 > 1200 revision status: G page 9 of 19
Chip or pre-sintered component Table 4.1.3: Design rules for LTCC process at VIA: cavities, windows and assembly features. BASIC DESIGN RULES Standard Special On request cavity/windows shape rectangular, square circular, others 1- cavity floor thickness in µm > 400 < 400 2- inner conductor-cavity spacing in µm 200 125 3- min. cavity/windows/ size in µm 400 < 400 min. channel width and height in µm max channel width and height in µm 100*100 600*400 Others Others 4- min. distance between cavities in mm > 2.0 < 2.0 5- via center-cavity spacing in µm 325 225 6- cavity depth in µm 800 > 800 7- cavity shelve edge-conductor spacing in µm 200 100 8- inner cavity width and height tbd tbd 9- top conductor-cavity spacing in µm 200 100 max. cavity/windows size unlimited note: symmetric layer construction desired assembly and interconnection wire bonding pitch in µm 250 < 250 solder pad pitch in µm 400 < 400 Lid/frames/heat sink attachment Solder, epoxy, glass bond, AuSn Flip Chip bonding pitch in µm 250 < 250 Pitch of BGA/LGA I/Os in mm (1) 1,27 < 1,27 Peripheral lead frames in mm 1,27 < 1,27 Brazed lead frames in mm - 2,54 0,635 Corner radius in µm 250 < 250 (1) BGA: Ball grid array LGA: Land grid array tbd: to be defined buried resistor revision status: G page 10 of 19
4.2 MATERIAL GUIDE FOR VIAS and CONDUCTORS Du Pont 951 Table 4.2.1: Material Gold System Mixed Metal System Silver System Internal or External Conductor signal lines Au Ag signal lines Au Ag ground planes Au Ag Via Conductor via fill Au Ag outer via fill Au AuAg Ag Wire Bondable or Solderable Conductor co-fired Au wire bonding Au -- Al wire bonding Au AgPd soldering AuPdPt AgPd Wire Bondable or Solderable Conductor post-fired Au wire bonding Au Au Al wire bonding Au Au soldering AuPdPt AgPt AgPt Brazing adhesion layer Au AgPt barrier conductor Au AgPt braze alloy AuSnCuAg postfire buried buried tape layer Resistors Capacitors available available 951 C2 Overglaze 500 C glaze available cofire glaze available revision status: G page 11 of 19
4.3 Parameters of the finished product Table 4.3.1: Electrical characteristics parameter value remarks electrical resistance between different tape layers: > 10 12 Ohm at 100 V DC min, layer thickness 94 µm in sintered stage electrical resistance between different > 10 12 Ohm at - traces on the substrate surface 100 V DC breakdown voltage: > 40 kv/mm - resistivity of inner layer conductors: 5 mω/ Au, thickness 7 µm 5 mω/ Ag, thickness 8 µm 20 mω/ AgPd, thickness 8 µm 80 mω/ PtAu, thickness 15 µm resistivity of outer layer conductors 4 mω/ Au, thickness 8 µm 2 mω/ Ag, thickness 15 µm 20 mω/ AgPd, thickness 15 µm 80 mω/ PtAu, thickness 15 µm resistivity of via connection between layers 6-7 mω / Via Au (via diameter 220 µm, thickness 140 µm) 3-5 mω / Via Ag Appx.15 mω / Via AgPd current density of inner Ag- conductor max. 1 A conductor thickness 8µm, conductor width 100 µm dielectric constant: 7,85 7,85 7,82 1Mhz 1 GHz 15 GHz dissipation factor < 0,15% (1Mhz) 1 MHz tan δ 0,005 0,010 1 GHz 15 GHz micro strip structure characteristic impedance 35-75 Ω characteristic impedance 35-75 Ω - line capacitance (examples), 10 layers 2nF/mm 2 conductor 220µm 1 tape 95 µm 1 nf/mm 2 1 tape 210 µm conductor 130µm line inductance (examples), 10 layers 10 nh/mm 2 conductor 220µm normal dielectric, 1 tape 95 µm 0,1 µh/mm 2 dielectric+ ferrite dielectric + ferrite+ core, 0,5 µh/m conductor 130µm 1 tape 210 µm propagation delay: 7.2 ns/m - printed resistors - resistivity 10 Ω/ -100 - kω/ decadic (post fired) temp. coefficient of resistivity + 100 K -1 - tolerance 1 % after trimming stability < 1% - revision status: G page 12 of 19
Table 4.3.2: Mechanical and physical characteristics of the sintered product parameter unit value Comp. to Al 2O 3 value material composition: glass ceramic, 50 % Alumina surface roughness: µm (R a) < 0.34 <0,89 camber: µm / mm < 200µm <0,3%/<0,2% surface ripple: µm < 50 <50µm/25mm density g/cm -3 3.1 3.78 percentage of theoretical density % 96 96 flexural strength: MPa 320 400 tensile strength: GPa 20-25 340 young modulus of elasticity: GPa 120 331 Hardness (Rockwell): - 45-82 82 Table 4.3.3: Thermal and thermomechanical characteristics parameter unit value Thermal coefficient of expansion: (25 C to 300 C) K -1 5,8 Thermal conductivity (at 25 C): (tape structure) W/m K 3 (with thermal vias) W/m K ca. 20 Specific heat: (100 C) J/g K 0,825 (150 C) J/g K 0,879 (300 C) J/g K 0,989 Max. working temperature: (Ceramic with thick film) C 400 revision status: G page 13 of 19
5 Specific Design Rules Du Pont 9K7 Table 5.1: Typical shrinkage values and sheet thickness shrinkage green to fired in % standard with cavities standard without cavities specific without cavities shrinkage x y DuPont 9K7 9.1 ± 0.3 9.1 ± 0.3 9.1 ± 0.5 shrinkage of cavities and windows 9.1 ± 0.4 shrinkage z DuPont 9K7 11.8 ± 0.5 11.8 ± 0.5 11.8 ± 0.5 0-shrinkage process not available not available not qualified sheet thickness in µm standard specific 127 ± 9 254 ± 14 revision status: G page 14 of 19
5.1 Design rules in detail Du Pont 9K7 Table 5.1.1: Design rules for LTCC process at VIA: BASIC DESIGN RULES Standard Special On request line width in µm internal, external Au 150 100 line spacing in µm internal, external Au 100 80 line pitch in µm internal, external Au 250 150 line width in µm internal, external Ag 150 100 line spacing in µm internal, external Ag 100 100 line pitch in µm internal, external Ag 250 200 edge to feature 350 200 via diameter in µm 175 100 via cover pad / catch pad 250 150 cover pad spacing in µm 100 100 via spacing in µm ² ) 175 150 via/cover pad pitch 350 250 via geometry round round via center to part edge ² ) 475 250 via types staggered stacked stacked Vias < 3 layers > 3 layers thermal via diameter in µm < 440 1000 thermal via pitch in µm 640 1300 thermal via coverage in % 30 50 ground/power plane coverage 75 % 100% size limited opening for feed through in µm ² ) 500 400 post fired resistors ground/power plane coverage 75 % 100% size limited opening for feed through in µm ² ) 500 400 co-fired resistors buried resistors buried capacitors to be tested 20 Ohm, 200 Ohm, available on request limited technical properties available on request, limited technical properties 2) for Via diameter: 175 µm revision status: G page 15 of 19
Table 5.1.2: Design rules for LTCC process at VIA: BASIC DESIGN RULES Standard Special On request dimensions, accuracy and alignment pattern/via position tolerance ± 0,2 % ± 0.05 % punching tolerance ± 10 µm ± 10 µm tape layer stability ± 35 µm < ± 35 µm alignment pattern to via/pattern ± 25 µm ± 25µm alignment layer to layer ± 35 µm ± 25µm singulation tolerance laser scribing singularized bricketting (cutter blade) dicing saw milling + 150 µm / -50 µm ± 100µm ± 50µm ± 50µm max. number of layers 15 > 15 min. number of layers 4 < 4 220 220 combinations of tape thickness 100 100 lot to lot thickness tolerance 3 % 3 % circuit shapes rectangular, square circular, free shaped usual circuit's thickness in µm 400 1200 < 400 > 1200 revision status: G page 16 of 19
Table 5.1.3: Design rules for LTCC process at VIA: cavities, windows and assembly features. BASIC DESIGN RULES Standard Special On request cavity/windows shape rectangular, square circular, others 1- cavity floor thickness in µm > 400 < 400 2- inner conductor-cavity spacing in µm 200 125 3- min. cavity/windows/ size in µm 400 < 400 min. channel width and height in µm max channel width and height in µm 100*100 600*400 Others Others 4- min. distance between cavities in mm >2.0 < 2.0 5- via center-cavity spacing in µm 325 225 6- cavity depth in µm 800 > 800 7- cavity shelve edge-conductor spacing in µm 200 100 8- inner cavity width and height tbd tbd 9- top conductor-cavity spacing in µm 200 100 max. cavity/windows size unlimited note: symmetric layer construction desired assembly and interconnection wire bonding pitch in µm 250 < 250 solder pad pitch in µm 400 < 400 Lid/frames/heat sink attachment Solder, epoxy, glass bond, AuSn Flip Chip bonding pitch in µm 250 < 250 Pitch of BGA/LGA I/Os in mm (1) 1,27 < 1,27 Peripheral lead frames in mm 1,27 < 1,27 Brazed lead frames in mm - 2,54 0,635 Corner radius in µm 250 < 250 revision status: G page 17 of 19
5.2 MATERIAL GUIDE FOR VIAS and CONDUCTORS Du Pont 9K7 Table 5.2.1: Material Gold System Silver System Via Conductor via fill standard Au Ag via fill, faster pront speeds - Ag Internal or External Conductor internal signal Au Ag internal ground plane Au Ag external signal line Au AgPd / Ag external ground plane Au AgPd / Ag Wire Bondable or Solderable Conductor co-fired wire bonding 1mil; internal Au - transition to cavity ledge wire bonding 1 & 2 mil Au Au - soldering - AgPd Solderable Conductor post-fired AuPtPd AgPd / AgPd Brazing adhesion layer Au AgPt barrier layer Au AgPt braze solder alloy AuSnCuAg AuSnCuAg revision status: G page 18 of 19
5.3 Parameters of the finished product Table 5.3.1: Electrical characteristics Parameter value Remarks resistivity of inner layer conductors: 5 mω/ Au, thickness 7 µm 5 mω/ Ag, thickness 8 µm 20 mω/ AgPd, thickness 8 µm resistivity of outer layer conductors 4 mω/ Au, thickness 8 µm 2 mω/ Ag, thickness 15 µm 20 mω/ AgPd, thickness 15 µm 80 mω/ PtAu, thickness 15 µm resistivity of via connection between layers 6-7 mω / Via Au (via diameter 220 µm, thickness 140 µm) 3-5 mω / Via Ag Appx.15 mω / Via AgPd current density of inner Ag- conductor max. 1 A conductor thickness 8µm, conductor width 100 µm buried capacitor to be verified postfired capacitor to be verified revision status: G page 19 of 19