Emerging Trends and Challenges of High Density Packaging & 3D IC Integration Ricky Lee, PhD, FIEEE, FASME, FInstP Center for Advanced Microsystems Packaging Hong Kong University of Science & Technology Clear Water Bay, Kowloon, Hong Kong 4 th Annual Conference of IeMRC Loughborough University, UK 2 September, 2009
50 Years of IC Industry Development 3D-IC SoC WSI VLSI/ULSI LSI ICs Transistors Vacuum Tubes 2
Infancy of Transistors and ICs Point-Contact Transistor, 1947 Bell Labs (William Shockley *, Walter Brattain *, John Bardeen ** ) Silicon-based Junction Transistor, 1954 Texas Instruments (Gordon Teal) Integrated Circuit (IC), 1958 Texas Instruments (Jack Kilby * ) & Fairchhild Semiconductor (Robert Noyce) Planar Transistor, 1959 Fairchild Semicondcutor (Jean Hoerni) Source: SIA Monolithic Risitor-Transistor Logic, 1961 Fairchild Semiconductor (Robert Noyce) Metal Oxide Semiconductor, 1968 Fairchild Semiconductor 3
Gordon Moore s Prediction The complexity for minimum component costs has increased at a rate of roughly a factor of two per year... Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although hthere is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. I believe that such a large circuit can be built on a single wafer "Cramming more components onto integrated circuits" Electronics Magazine, 19 April 1965 Source: Intel Museum 4
Moore s Law for ICs # of Transistors on an IC will be doubled every 18-24 months Source: Wikipedia 5
More Moore (MM) and More than Moore (MtM) Source: ITRS2007 6
Nanotechnology for MM Source: Intel 7
System Integration for MtM System-on-Chip Multi-Chip Module (Multi-Chip Package) System-on-Board Package-in-Package System-in-Package Package-on-Package System-on-Packagey g 8
Evolution of Packaging Efficiency 3DP 9
Current Implementations of 3DP Various Web & Personal Sources 10
Emerging 3DP Trends Flip chips on silicon chip carrier with TSVs as interposer. (C2S) Stack multiple flip chips with TSVs as vertical interconnection. ti (C2C) Embedded wafer level packaging. (C2W) Wafer bonding for 3D integration. (W2W) Various Web & Personal Sources 11
Scope of TSV Technologies TSV Formation - Laser Drilling -Deep Reactive Ion Etching (DRIE) Interfacial Layers - Insulation - Barrier/Adhesion - Seed TSV Plugging - Copper - Tungsten - PolySi 12
TSV by Laser Drilling Punching Trepan Spiral 25 µm 29 µm 61 µm 11 µm 8µm 52 µm Direct Punching (0.8W, 200 Pulses) Trepanning (0.8W, 100 Repetitions) Spiraling (0.8W, 50 Repetitions) 13
TSV by Deep Reactive Ion Etching The TSVs are formed by DRIE on a silicon wafer with silicon oxide as the mask. The DRIE machine uses SF 6 to etch the silicon and C 4 F 8 to coat a passivation layer to protect the sidewall of the etched part during the etching gprocess. 14
Cross-Section of DRIE TSVs 65 µm 15
Interfacial Multilayer Structure of TSV Seed Layer (Cu) Silicon Substrate Adhesion/Barrier Layer (TaN or TiW) Insulation Layer (SiO 2 ) 16
SEM Micrograph of Interfacial Multilayer Structure Ti Ti 17
TSV Plugging by Copper Plating TSV Plugged with Cu Over-plated Cu Top Side of Wafer after Copper Plating Cross Section Inspection Bottom Side of Wafer after Copper Plating 18
Electroplating Basics Subconformal Subconformal plating leads to the formation of void even in the straightwalled features. Conformal In conformal plating, a deposit of equal thickness at all points of a feature leads to the creation of seam. Typical of PCB and bump processes. Superconformal Copper growth starts at the bottom of the via and rapidly progresses upwards with the aid of special plating additives that possesses different adsorption preferences on features. Required for sub-micron feature filling. 19
Functions of Plating Chemicals Copper Sulphate Sulphuric acid Chloride ions (Cl - ) Polyethylene glycol (PEG) Basic plating solution Provide the required copper ions and acid for plating. Suppressor Hinders the deposition of copper at the corners of the via. Bis(3-sulfopropyl)disulfide (SPS) Janus Green B (JGB) TPPA SYS301 Accelerator Accelerate the deposition of copper at low current density region. Leveler A weak suppressor which will flatten the copper deposition of copper on top surface of the wafer. Wetting agent Provides extra wettability for copper deposition at bottom of the via. 20
Plating Solution Optimization 21
Range of Chemicals 22
HKUST 4-Stack Flip Chip Prototype with TSV 23
Other Issues with 3D Flip Chip Stacking Re-distribution and Bumping Wafer Thinning and Handling Dicing/Stackingi or Wafer Bonding Underfill Encapsulation (?) ICs TSVs Substrate 24
Process Flow Options for TSVs 25
3D TSV Interconnect Trends Source: Yole Development 26
Industrial TSV Module Deployment (II) The new CSCM micro-camera modules will be the first produced with TCV technology, which reduces wire bonding a substrate area by mounting components directly on the wafer and running electrodes through the vias on the circuit board, securing them with balls of solders on the substrate. (50 μm dia., 70 μm deep) Source: Toshiba 27
Industrial TSV Module Deployment (I) 28
Samsung TSV and Stacking Roadmap Source: Samsung 29
Nokia 3D Packaging Roadmap Source: Nokia 30
Semiconductor 3D Equipment & Materials Consortium Source: EMC 3D The mission of the international consortium EMC 3D is to rapidly develop a cost-effective and manufacturable TSV for 3D chip stacking and MEMS integration. Technology support for the consortium goals is from associate members Fraunhofer IZM, SAIT (Samsung Advanced Institute of Technology), KAIST (Korea Advanced Institute of Science and Technology), TAMU (Texas A&M University), CEA LETI, and NXP. Material members include Rohm and Haas, Enthone, Brewer Science, and AZ Electronic Materials with wafer service support from WRS Materials. Equipment companies are Datacon, EV Group, Semitool, and XSiL. 31
Technical Roadmap of EMC 3D Source: EMC 3D 32
ITRS System-in-Package Roadmap Source: ITRS2007 33
Importance of Design Tools Source: R3Logic 34
HKUST Campus at Clear Water Bay, HK 35