Performance Engineering for High-Tech Systems: Crossing Boundaries

Transcription

1 Twan Basten Eindhoven University of Technology & TNO Embedded Systems Innovation P A G E 1 Joint work with many others Funding: Artemis EMC2, Almarvi STW Robust CPS program Min. of Economic Affairs, Océ Octo+ program Min. of Economic Affairs, ASML CARM2G program P A G E 2 3 The challenge Image processing and paper handling in production printing How to optimize productivity under cost and quality constraints? Target: 150 pages A4/minute, duplex, color Industrial challenges inspiring research Scheduling print jobs? Scheduling pages? Processing images? Configuring the printer? Managing temperature? Scheduling maintenance? Optimizing topology?

2 4 The challenge Controlling an electron microscope data-intensive control 5 The challenge Data processing and motion control in interventional x-ray Network stage Sensors Sensor data Processing Control Image Sensor Control Stage control Beam control mosquito eyes Maximizing data processing throughput? Coping with processing & communication latencies? Lens Resource sharing? Virtualization? Real-time processing? Safety? P A G E 6 Model based performance engineering 1 Which questions do we have w.r.t. performance? 2 Initial modeling based on questions. 7 Performance TNO ESI 3 Predict the past: Measurements on existing are used for calibration and validation of model X. Gives prediction accuracy and builds trust. 4 Model design alternatives that may answer questions. 5 Explore the future: Predictive models for the new are analyzed following the initial questions. Results are interpreted and feedback is given to development process. 6 Retrospective model validation builds experience.

3 P A G E 8 Reduce cost, while guaranteeing performance 9 Interplay between model and implementation Parallel code that uses all available CPU cores. Calibration using several multi core CPU platforms Modeling: Amdahl s law: Validation fitting Amdahl s law gives a good fit! 1 ) Calibration & validation T( ) the execution time with cores s the sequential fraction of the code (schematic)

4 12 13 Calibration & validation Model new 1 ) T(1) is estimated by scaling the measurements with the ratio given by a public single threaded CPU performance benchmark s is estimated from the measurements Calibration & validation Model new Prediction Prediction model implemented in a spread sheet Cost Predictions have been used to select new CPU Pareto frontier (schematic) Execution time 14 Prediction: model implemented in a spread sheet Cost Pareto frontier (schematic) Calibration & validation Model new Prediction Validation Predictions have been used to select new CPU Execution time Measurements on the new CPU confirm accuracy Combinatorial optimization

5 16 Print job scheduling 17 Print job scheduling synthetic benchmark Simultaneous sequencing (job order) and selection (print mode) execution time (ms) CPH fast and accurate jobs On-line timing constraints Compositional to cope with new jobs Generalized Traveling Salesman Problem Compositional Pareto-algebraic Heuristic CPH Generalized Traveling Salesman Problem Compositional Pareto-algebraic Heuristic CPH 18 Print job scheduling synthetic benchmark execution time (ms) objective 2 jobs CPH fast and accurate objective 1 Generalized Traveling Salesman Problem Compositional Pareto-algebraic Heuristic CPH Feedback control

6 20 Platform virtualization & resource sharing 21 Embedded control App1 App2 App1 Periodic sampling h App1 App2 Micro kernel Application layer Microkernel layer control application slot micro-kernel slot other application slots control application t CPU Memory Multi-periodic sampling Interconnect HW layer h 1 h 1 h 2 Switched linear s t 22 Embedded control cost / performance trade offs 0,700 Performance 0,600 0,500 0,400 0,300 0,200 Simulation HIL FPGA Implementation 0,100 0,000 9% / single 27% / contiguous 27% / distributed 45% / contiguous 45% / distributed 63% / contiguous 63% / distributed 90% / complete Feedback control Resources/Type of allocation

7 24 Robust scheduling of control applications 25 Robust scheduling of control applications execution time execution time Stochastic robustness analysis in a list scheduler 27 Multi-core pipelined sensing in image-based control Static pipelined control Dynamically reconfigurable pipelined control Feedback control Switched linear s

8 28 Multi-core pipelined sensing in image-based control Reconfigurable pipelined control Static pipelined control Sequential control Reconfigurable pipelined control performs best! Supervisory control Switched linear s 30 Supervisory control: ensuring safe behavior 31 Supervisory control: state-space explosion LR UR IN COND DRILL OUT Avoid collissions Drill only when material present

9 32 Supervisory control: timing analysis Minimal throughput Maximal throughput Win-win: avoid low throughput paths during controller synthesis Best practices 34 System scenarios and rigorous foundations 35 Conclusions Scenario-based design modes, configurations Design-time optimization per scenario Run-time reconfiguration between scenarios Crossing boundaries Embedded computing Timing analysis for communicating processes: (max, +)-algebra Supervisory control Combinatorial optimization Feedback control Performance engineering Game theory max, Run-time optimization game theory, Pareto algebra (max,+) algebra Strategic collaborations between academia and industry pay off