High Level Tools for Low-Power ASIC design

Transcription

1 High Level Tools for Low-Power ASIC design Arne Schulz OFFIS Research Institute, Germany 1

2 Overview introduction high level power estimation µprocessors ASICs tool overview µprocessors ASICs conclusion future work 2

3 Moores Law [Rab99] beating Moores Law 3

4 Trade-off Accuracy Abstraction level System architecture Behaviour Registertransfer e.g. SimpleScalar-based (some 100 M CPU instructions) SPICE (some 100 pattern on small circuit) Gate Transistor Simulation time 4

5 traditional design flow C/C++ program architecture definition memory optimization datapath optimization RT-level design synthesis design analysis, power estimation gain: 75% time: months gain: 30% time: weeks Standard design flow gain: 15% time: days Why High-Level? specification level impact analysis. first time right architecture. up to 75% power reduction in minutes. avoids design iteration down to RT or gates. saves up to months of design time. gain: 30% time: minutes no high-level design flow C/C++ program analysis & optimizaton yes ok? RT-level design synthesis final analysis ok? Standard design flow no gain: 75% time: minutes no gain: 15% time: days ok? no design backend design backend 5

6 Embedded Approach trend to software development: faster than hardware development cheaper than hardware development easier than hardware development updates/fixes are possible (e.g. firmware-updates) off the shelf CPUs high-level power estimation for µ-processors high-level power estimation for ASIC 6

7 Example SW Estimation Tool AccuPower overview: high level microprocessor power estimation tool contains micro architectural simulators library of VLSI layouts power estimator based on SimpleScalar (MIPS-based ISA-simulator) vendor: academic 7

8 Algorithmic Level Estimation two different approaches: quick synthesis to RTL net list complex and slow inaccurate if synthesis result does not get close to final architecture internal information about applied synthesis tool necessary complexity analysis of control data flow graph (CDFG) representation only transformation of algorithm into CDFG needed (compilation) fast but less accurate example: register power is computed by counting number of CDFG edges between operations 8

9 Example: Quick Synthesis Approach HyPE: Overview Hybrid Power Estimation uses behavioural simulation and macro models for data path components three phases of estimation: - high level simulation - calculation of data path modes - statistical power estimation very high performance vendor: academic 9

10 Less Time to Low Power minutes 90% Specification days weeks Design Time Power gain 50% 20% System Architecture Design RT-Level Synthesis Gate-Level? ORINOCO commercial estimation tools available 10

11 ORINOCO Principle Source Source Code Code C/C++ C/C++ SystemC SystemC Activity Activity Data Data Created Created by by simulation/execution simulation/execution using using real real world world data data input. input. Model Library Created by: ORINOCO RIO and ORINOCO BEACH ORINOCO DALE Constraints Voltage Frequency Timing (Critical Path Length) Area (Number of resources) Power Power Clock Clock Interconnect Interconnect Controller Controller Functional Functional Units Units Register Register I/O I/O Memory Memory Architecture Architecture Allocation Allocation Binding Binding Scheduling Scheduling Floorplan Floorplan 11

12 Example Estimation Result 12

13 Conclusion high-level power estimation: biggest gain is possible academic approaches for high-level power optimisation leading edge of current research embedded software power estimation still research topic ASIC power estimation on lower levels: commercial tools available (eg. Synopsys, Sequence, Cadence) for higher levels first available tool: ORINOCO from ChipVision 13

14 Future Work research at OFFIS (SAO-group) new metrics (interconnect, area, timing) improved models (IP, leakage) software power estimation (µ-processors, partitioning) commercial exploitation at ChipVision Design Systems 14