RecruitPlus. Bringing new wave of Automation to Recruitment process. RecruitPlus Resume Parser. ITCONS e Solutions Pvt. Ltd.

Transcription

1 RecruitPlus Bringing new wave of Automation to Recruitment process RecruitPlus Resume Parser ITCONS e Solutions Pvt. Ltd.

2 An Overview RecruitPlus Resume Parser RecruitPlus Resume Parser Windows Application for bulk parsing from File folder/ Outlook/ web page along with facility of duplication check using Click one deployment. RecruitPlus Resume Parser Web API Available on Scalable, configurable & multi tenant efficient SaaS model In house deployment in client premises.

3 Resume Parser: Extract Info from Candidate Resume Resume Parser as a Product (Windows App) RecruitPlus Resume Parser windows based application allows users to extract candidate information from resumes in file folders, MS Outlook or any online jobportal/ networking sites etc. Write us on welcome@onlineresumeparser.com for a demo login. Resume Parser as a Service (API) Open API integration of RecruitPlus Resume parser with any Job board/networking sites/ats/ HR applications etc. Write us on welcome@onlineresumeparser.com for a demo login. RecruitPlus Resume Parser can extract the candidate information from resumes in.doc,.docx,.html,.pdf,.rtf,.txt format. Parsing utility extracts all candidate parameters present in CV with a high accuracy level. Parsing utility can parser resumes per hour from each PC (depends on client/server machine configuration) thus reduces the candidate information extraction time to 5 6 seconds per resume from normal manual punching time of mins. When a new user registers on a job board o networking site, User has to fill all the required information (whether personal or professional) manually; User has no choice but to spend min good minutes just to complete the profile. With RecruitPlus TM Resume Parser, The candidate can browse the resume from PC/other Job board etc and all the required fields pertaining to personal/ professional information of candidate get filled automatically. Target market: Worldwide Corporate (English CVs) in house HR and Placement companies, ATS, HR applications, Job Portals & Career Networking sites.

4 RecruitPlus Resume Parser Window Based App Bulk Extraction of candidate information from various formats like.docx,.doc,.rtf,.pdf,.html and.txt etc from file folder, Outlook and Website. Parsing speed is as high as 20K resumes per day with 70% to 99.9% accuracy.

5 RecruitPlus Resume Parser API

6 PERSONAL DETAILS <CANDIDATE_FULL_NAME>Sunil Kumar gorgia</candidate_full_name> <CANDIDATE_FIRST_NAME>Sunil</CANDIDATE_FIRST_NAME> <CANDIDATE_MIDDLE_NAME>Kumar</CANDIDATE_MIDDLE_NAME> <CANDIDATE_LAST_NAME>Gorgia</CANDIDATE_LAST_NAME> <FATHER'S_NAME>unspecified</FATHER'S_NAME> <SECONDARY_ _ID></SECONDARY_ _ID> <OFFICIAL_ _ID>unspecified</OFFICIAL_ _ID> <PHONE_MOBILE> </PHONE_MOBILE> <PHONE_BASIC>unspecified</PHONE_BASIC> <FAX_PHONE>unspecified</FAX_PHONE> <DOB>1/2/1963</DOB> <STREET>ATS Greens II, Sector 50</STREET1> <CITY>Noida</CITY> <REGION>UP</REGION> <COUNTRY>India</COUNTRY> <PIN>201307</PIN> <CURRENT_LOCATION>INDIA</CURRENT_LOCATION> <PREFERRED_LOCATION>unspecified</PREFERRED_LOCATION> <AGE>unspecified</AGE> <TOTAL_EXPERIENCE>21Years & 10Months</TOTAL_EXPERIENCE> <CURRENT_SALARY>unspecified</CURRENT_SALARY> <EXPECTED_SALARY>unspecified</EXPECTED_SALARY> <MARITAL_STATUS>Single</MARITAL_STATUS> <GENDER>Male</GENDER> <PASSPORT_NUMBER>unspecified</PASSPORT_NUMBER> <VISA_STATUS>unspecified</VISA_STATUS> <DRIVING_LICENSE_DETAILS>unspecified</DRIVING_LICENSE_DETAILS>

7 PROFESSIONAL DETAILS <JOB_OBJECTIVE>Looking for a senior level executive position in Project Management / Business Development / Product Development and Delivery with a growth oriented organization. Interested in setting up a team or growing existing team into new business.</job_objective> <EXECUTIVE_SUMMARY>A highly dedicated professional with high commitment, integrity and passion possessing 20 years of experience in EDA software development Project and People Management, Delivery Management, Customer Engagement, Software Development and Team Management. Presently associated with Cadence Design Systems, Noida as Engineering Director. Driving projects with rich expertise in conceptualizing, planning, executing and delivering in compliance to quality standards. Leading overall product development cycle from requirement analysis to system study, designing, coding, testing and quality checking. Heading Cadence Virtuoso Physical Design Development group in India; Virtuoso platform is the market leader in Custom IC design and has 70% of the market share. Proven track record in developing teams from scratch, managing them to work individually as well as in collaboration with cross geographic teams being in sync with the corporate set parameters. Proven skills to motivate people through integrity and simplicity and inculcating the culture of achieving organizational, business and individual goals. Developing culture of innovation leading to multiple patents in various products. Possesses excellent team leadership with good interpersonal, communication and analytical skills. Excellent skills in customer engagement with demonstrated abilities in developing customer relationship. </EXECUTIVE_SUMMARY>

8 PROFESSIONAL DETAILS <SKILLS_SET_1>Virtuoso</SKILLS_SET_1><LASTUSED_DATE_1>6/18/2012</LASTUSED_DATE_1> <SKILLS_SET_2> Verilog</SKILLS_SET_2><LASTUSED_DATE_2>6/18/2012</LASTUSED_DATE_2> <SKILLS_SET_3> VHDL</SKILLS_SET_3><LASTUSED_DATE_3>6/18/2012</LASTUSED_DATE_3> <SKILLS_SET_4> HR</SKILLS_SET_4><LASTUSED_DATE_4>6/18/2012</LASTUSED_DATE_4> <SKILLS_SET_5> EDA</SKILLS_SET_5><LASTUSED_DATE_5>8/1/1997</LASTUSED_DATE_5> <SKILLS_SET_6> Cadence</SKILLS_SET_6><LASTUSED_DATE_6>6/18/2012</LASTUSED_DATE_6> <SKILLS_SET_7> Synopsys</SKILLS_SET_7><LASTUSED_DATE_7>8/1/1997</LASTUSED_DATE_7> <SKILLS_SET_8> Viewlogic</SKILLS_SET_8><LASTUSED_DATE_8>8/1/1997</LASTUSED_DATE_8> <SKILLS_SET_9> VSS</SKILLS_SET_9><LASTUSED_DATE_9>8/1/1997</LASTUSED_DATE_9> <SKILLS_SET_10> Vantage</SKILLS_SET_10><LASTUSED_DATE_10>8/1/1997</LASTUSED_DATE_10> <SKILLS_SET_11> IR</SKILLS_SET_11><LASTUSED_DATE_11>5/1/1995</LASTUSED_DATE_11> <SKILLS_SET_12> Options</SKILLS_SET_12><LASTUSED_DATE_12>5/1/1995</LASTUSED_DATE_12> <SKILLS_SET_13> C++</SKILLS_SET_13><LASTUSED_DATE_13>5/1/1995</LASTUSED_DATE_13> <SKILLS_SET_14> Solaris</SKILLS_SET_14><LASTUSED_DATE_14>5/1/1995</LASTUSED_DATE_14> <CERTIFICATIONS>Certified Internal Auditor</CERTIFICATIONS>

9 EMPLOYMENT HISTORY <CURRENT_COMPANY_NAME>Cad Design Systems</CURRENT_COMPANY_NAME> <CURRENT_DESIGNATION_>Engineering Director</CURRENT_DESIGNATION> <CURRENT_PROJECT_START_DATE>8/1/1997</CURRENT_PROJECT_START_DATE> <CURRENT_PROJECT_END_DATE>6/18/2012</CURRENT_PROJECT_END_DATE> <CURRENT_PROJECT_SUMMARY>Since Aug'97 with Cad Design Systems, Noida, current position as Engineering Director Key Deliverables Driving the Virtuoso Layout tool development team in India along with cross functional teams including Product Engineering, validation, documentation, configuration and release management. Owning complete Virtuoso custom floor planner, custom placer, Abstract Generator, Stream and LEFDEF interfaces, database converters in India. Developing their roadmaps, product execution and direction in India and delivering on the same though various releases. Collaborating with cross geography teams on analog digital mixed signal initiatives around floor planning, placement and abstract generator. Identifying deliverables and building on roadmaps. Developing other verticals on layout editing and PDK development tools and supervising these teams. Developing and co ordinating local customer engagements and helping in global customer engagements. Supported Virtuoso front end tools on business need which included Schematic Editor and Verilog, VHDL interface with front end system. Notable Achievement Received several organization level awards on "Excellence in Execution", "Teaming", "Value Practice" and "Outstanding Achievement". Felicitated with division level award on a specific customer engagement for delivering them a flow with enhanced Virtuoso layout tools which led to 30% productivity improvement. Received organization level award on "Quality Improvement" resulting into 30% reduction in customer CCRs. Instrumental in creating and resurrecting some products from concept to productization in India. Initiated identifying new ideas added into products developed in India and filing patent, about 18 patents filed from the team (about 10 are in US PTO). I am author in 5 patents out of which 4 are in US PTO. Established PDK tools development team in India with a local manager (groomed in India) and complete responsibility. Established Virtuoso Layout Editor team in India with a local manager seeded from India layout team. Developed the physical design R&D development team from scratch into a highly mature team with senior leaders focusing on different domains of complete layout design flow. Facilitated growth of other cross functional teams for physical design. Conceptualized the complete Mentorship Program for Cadence India center, implemented and made it operational with automated in housetoolassistanceinassociationwithhrteam.engagedinothercommonorganizationalinitiativessuchas training and learning programs, technical presentations, shared learning etc.</current_project_summary>

10 EMPLOYMENT HISTORY <PREVIOUS_COMPANY_NAME_1>Duet Technology</PREVIOUS_COMPANY_NAME_1> <PREVIOUS_DESIGNATION_1>Engineering Manager</PREVIOUS_DESIGNATION_1> <PREVIOUS_PROJECT_START_DATE_1>5/1/1995</PREVIOUS_PROJECT_START_DATE_1> <PREVIOUS_PROJECT_END_DATE_1>8/1/1997</PREVIOUS_PROJECT_END_DATE_1> <PREVIOUS_PROJECT_SUMMARY_1>May'95 Aug'97 with Duet Technology, Noida, last position as Engineering Manager Key Deliverables Completely responsible and accountable for Library Development group and associated software tools. Development and delivery of simulation, timing and test libraries for key semiconductor companies, e.g. AMD, Vitesse, Atmel, SMOS, LSI, IKOS etc. Development of customized libraries and validation with tools from most of the EDA vendors Cadence, Synopsys, View logic, Sunrise etc. The tools included VSS, Verilog XL, Vantage, VITAL, Leapfrog, MOTIVE etc.in house development of software tools (Verilog2VITAL) and utilities for the library development. Hiring, training and developing team. Checking test reports and quality aspects. Interfacing with customers for validation at their sites. Contributing in getting the company ISO 9000 certified. Notable Achievement Started with a small team of 2 3 people working on timing libraries and then developed into a significant business with multiple sub teams working on libraries for multiple tools for many customers. Automated library development process through in house tools to reduce turn around time. Extensive engagement in organizational initiatives such as ISO 9000 certification. Received lead internal auditor certification. Visited customers in US for problem resolution and business development.</previous_project_summary_1>

11 EMPLOYMENT HISTORY <PREVIOUS_COMPANY_NAME_2>ITI Ltd</PREVIOUS_COMPANY_NAME_2> <PREVIOUS_DESIGNATION_2>Senior Executive Engineer</PREVIOUS_DESIGNATION_2> <PREVIOUS_PROJECT_START_DATE_2>8/1/1990</PREVIOUS_PROJECT_START_DATE_2> <PREVIOUS_PROJECT_END_DATE_2>5/1/1995</PREVIOUS_PROJECT_END_DATE_2> <PREVIOUS_PROJECT_SUMMARY_2>Aug'90 May'95 with ITI Ltd., Bangalore, last position as Senior Executive Engineer Key Deliverables Developed multiple software components of the overall Vinyas Standard Cell based and Full Custom design system. All phases of the tool development including specification, design, code implementation, testing and integration into the main system were done independently. Vinyas system was used in house in ITI for telephone chip designs. This was also used by defense organizations DRDO and academic institutions. Tools developed Module Generator for RAM and ROM: Given the library of gates and specification of memory size and feature parameters, the tool can generate complete schematic circuit for the memory block in Vinyas Gate Array based system. Floor planner and P/G routing: The Vinyas Std. Cell based system was based on slicing structure and partitioning was done accordingly. To feed appropriate power to all the cells under the slicing tree, a special power and ground router was developed. This router had inter leaved structure on the same metal layer without shorting between power and ground. Power budgeting was done for appropriate layer width at various levels with consideration of IR drop and metal migration. Timing Analyzer for transistor level circuits: Timing analysis was done for the whole circuit which included combinational and sequential parts. Options for various modes from input to output paths were provided. Critical path analysis was done and worst path reported for balancing the timing accordingly. Various techniques were used to recognize specific elements like loops, multiplexors, bi directional switches etc. to determine right current propagation. Transistor Sizer: Transistor sizing was done in collusion with timing analysis. In the worst path sensitivity of each transistor was analyzedandmostsensitivetransistorwaschosenforupdatingit'swidthwhichresultedinbest optimizationontime.itwasan iterative process between transistor sizing and timing analysis with check on number of iterations to optimize time and transistor size. VHDL Analyzer: This was a front end project in start. It was simple VHDL parser and analyzer to provide report on the circuit described in VHDL. Most of the tools were developed in C / C++ on Unix / Solaris operating system.</previous_project_summary_2>

12 EDUCATIONAL DETAILS <HIGHEST_DEGREE>Master of Engineering</HIGHEST_DEGREE> <HIGHEST_EDUCATIONTYPE>Post Graduate</HIGHEST_EDUCATIONTYPE <HIGHEST_EDUCATIONDETAILS>Electrical Communication</HIGHEST_EDUCATIONDETAILS> <HIGHEST_EDUCATION_START_DATE>Unspecified</HIGHEST_EDUCATION_START_DATE> <HIGHEST_EDUCATION_YEAR_OF_PASSING>1/1/1990</HIGHEST_EDUCATION_YEAR_OF_PASSING> <HIGHEST_INSTITUTION_NAME>Indian Institute of Science</HIGHEST_INSTITUTION_NAME> <INSTITUTION_TYPE>University</INSTITUTION_TYPE> <INSTITUATION_LOCATION>unspecified</INSTITUATION_LOCATION> <HIGHEST_EDUCATION_DESCRIPTION>Master of Engineering in Electrical Communication with 1st class from Indian Institute of Science in 1990.</HIGHEST_EDUCATION_DESCRIPTION> <HIGHEST_EDUCATION_MARKS>unspecified</HIGHEST_EDUCATION_MARKS>

13 Contact us RecruitPlus Parser Sales Team Tel: /37 Need Help/Support? Log the call at Username: user ; Password: password