Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO Anne Yue

Size: px
Start display at page:

Download "Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO Anne Yue"

Transcription

1 Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO Anne Yue Synapse Design 2200 Laurelwood Rd. Santa Clara, CA 95054

2 Abstract This paper describes and compares the current EDA tools for STA, timing closure and timing ECO. In-depth studies on ETS, PrimeTime & Dorado let us understand the can/cannot of the tools. Proven-in-silicon workarounds are efficient for a faster timing closure. 3 solutions are shared in this paper to solve the left-over issues from PrimeTime ECO tool. One of the solutions(upsizing DFF) will be Enhancement features in future PrimeTime release( ). Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 2

3 Agenda Challenges for SOC Timing Closure Who Can Help on STA? Who Can Help on Timing ECO? Solutions with Clock Path ECO Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 3

4 Challenges for SOC Timing Closure ASIC design size increasing exponentially every year. 20 million instance designs last year. 65 million instance designs this year. With 32nm & less technology, temperature inversion and power related analysis bring in more PVT corners for timing STA. One ECO loop can take 3~5 days. Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 4

5 Who Can Help on STA --- ETS & PrimeTime ETS(Encounter Timing System) --- Cadence timing signoff tool PrimeTime --- Synopsys timing signoff tool ETS & PrimeTime are both silicon-proven timing signoff tools. ETS & PrimeTime can work interleave with implementation tools from other companies. Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 5

6 ETS vs. PrimeTime on Constraints The sdc coding style for clock-group related constraints matters to ETS & PrimeTime. ETS will interpret differently than PrimeTime on some clock-group definition. PrimeTime is more robust than ETS on this. With different clock-group understandings, ETS & PrimeTime will give out different sets of report. Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 6

7 ETS vs. PrimeTime on Design Slack If feed with the same quality(good) constraints, slack difference between ETS vs. PrimeTime DMSA ps with setup, 20ps with hold PrimeTime is more pessimistic than ETS. In some case ETS cannot report max_tran violation which PrimeTime reported. Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 7

8 ETS vs. PrimeTime on ECO PrimeTime DMSA can generate ECO.tcl for setup/hold/max_trans/max_fanout/max_cap DMSA MCMM features very helpful on timing closure with PVT corners/modes ETS ECO feature is under-construction. Hold time ECO is in place. No setup ECO. ETS is about 2~4 years behind PrimeTime on timing ECO. Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 8

9 Who Can Help on Timing ECO --- PrimeTime & Dorado PrimeTime is with fix_eco_timing & fix_eco_drc Same license as PrimeTime & PrimeTime-SI Dorado is a 100% ECO tool. Dorado does not have build-in timing engine. Instead, it has ECO-specific engine. Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 9

10 Dorado in ECO Dorado is with ECO for: setup/hold/max_trans/max_cap/max_fanout Dorado can generate eco.tcl & eco.def. The incremental.def file will serve as guidance for BackEnd tool ECO legalization, which increase the possibility of ECO process convergence. Clock ECO is the highlight for this tool. Remove buffers for setup fix. A new tool means the tool setup overhead efforts for design team. Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 10

11 PrimeTime in ECO fix_eco_timing can do: -- on Data Path 21 o upsize/downsize cells o insert buffer fix_eco_timing cannot do: o remove cells. o change clock path(clock Path 1 & Clock Path 2) Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 11

12 PrimeTime DMSA ECO --- Can & Cannot Data Path 21 DFF 2 DFF 1 Clock Path 2 Clock Path 1 Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 12

13 PrimeTime DMSA ECO --- fixed & left over Hold Violations : 99 ~ 100% good job! setup Violations : 85 ~ 90% DMSA ECO did very good job on cell-sizing base on MCMM timing analysis. But launch/capture clock path are untouched by the tool. Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 13

14 Before fix_eco_timing: After fix_eco_timing: Setup violations Total reg->reg reg->out in->reg in->out C2C * -> * WNS TNS NUM Hold violations C2C * -> * WNS TNS NUM Setup violations Total reg->reg reg->out in->reg in->out C2C * -> * WNS TNS NUM No hold violations found Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 14

15 How to fix the DMSA ECO left over violations? No room for Data Path 21 cell-sizing. MCMM mode DMSA ECO did better job than human in cell-sizing. PT_ECO consider DFFs as part of clock network, since the DFF/CK pin is the end point of the clock tree. PT_ECO cannot touch the clock path cells. So, DFF2 cell is not upsized by the PT tool. Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 15

16 Solution I with Clock Path ECO -- Upsizing DFFs Upsize the DFFs will benefit the setup fix in the following ways: DFF component delay # will improve. New upsized DFF improves the transition delay for downstream cells, which give possibility for another round of PT_ECO run to optimize the data path cells. So we plan to do: upsizing DFF + additional PT_ECO run Enhancement to fix_eco_timing to allow DFF sizing will be add into future PrimeTime release( ). Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 16

17 Solution II with Clock Path ECO -- Clock tree re-stitching Clock skew borrowing for left-over setup fix. 1 st level & 2 nd level(~10% chance) borrowing. By re-arrange the launch/capture clock to the same CTS branch, we can get the extra CRPR bonus for this in-depth study re-stitching. Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 17

18 2 nd Level Setup Margin Borrowing DFF3 DFF2 DFF Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 18

19 Extra bonus for CRPR with Clock Tree Re-stitching DFF 2 DFF 1 Re-stitching Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 19

20 Solution III with Clock Path ECO --- Clock tree in-law unit Utilize PD tool(icc or Encounter) to build the in-law ECO clock structure. Targeting insertion # is pre-calculated. May need two round of spef->eco to get the right insertion #. Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 20

21 Questions & Comments Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 21

22 THANKS Find EDA Tools for A Faster Timing Closure with ECO & Clock Path ECO 22

PrimeTime Mode Merging

PrimeTime Mode Merging WHITE PAPER PrimeTime Mode Merging Reducing Analysis Cost for Multimode Designs Author Ron Craig Technical Marketing Manager, Synopsys Introduction As process technologies shrink, design teams can fit

More information

4. Back-End Timing Closure for HardCopy Series Devices

4. Back-End Timing Closure for HardCopy Series Devices 4. Back-End Timing Closure for HardCopy Series Devices H51013-2.4 Introduction Back-end implementation of HardCopy series devices meet design requirements through a timing closure process similar to the

More information

High Performance Latch based Design: Optimization and Timing Verification Challenges

High Performance Latch based Design: Optimization and Timing Verification Challenges High Performance Latch based Design: Optimization and Timing Verification Challenges Kumar Subramanian KS Ramesh Product Engineering Group Intel Corporation March 11 2016 Outline Processor Design Landscape

More information

Horseshoes, Hand Grenades, and Timing Signoff: When Getting Close is Good Enough

Horseshoes, Hand Grenades, and Timing Signoff: When Getting Close is Good Enough Horseshoes, Hand Grenades, and Timing Signoff: When Getting Close is Good Enough Arvind NV, Krishna Panda, Anthony Hill Inc. March 2014 Outline Motivation Uncertainty in SOC Design Leveraging Uncertainty

More information

11. Timing Closure in HardCopy Devices

11. Timing Closure in HardCopy Devices 11. Timing Closure in HardCopy Devices qii52010-2.0 Introduction Timing analysis is performed on an FPGA design to determine that the design s performance meets the required timing goals. This analysis

More information

IC Compiler Comprehensive Place and Route System

IC Compiler Comprehensive Place and Route System Datasheet IC Compiler Comprehensive Place and Route System Overview IC Compiler is the leading place and route system. A single, convergent, chiplevel physical implementation tool, it includes flat and

More information

Presenters: Ing. Mauricio E. Caamaño B. Ing. Oscar A. Muñoz Alcazar.

Presenters: Ing. Mauricio E. Caamaño B. Ing. Oscar A. Muñoz Alcazar. Presenters: Ing. Mauricio E. Caamaño B. Ing. Oscar A. Muñoz Alcazar. Agenda 1. What is Structural Design? 2. Logic and physical optimization process 3. Signoff flows in SD 4. Structural Design team skillset

More information

Overview. Design flow. Back-end process. FPGA design process. Conclusions

Overview. Design flow. Back-end process. FPGA design process. Conclusions ASIC Layout Overview Design flow Back-end process FPGA design process Conclusions 2 ASIC Design flow 3 Source: http://www.ami.ac.uk What is Backend? Physical Design: 1. FloorPlanning : Architect s job

More information

Frontend flow. Backend flow

Frontend flow. Backend flow This section intends to document the steps taken in the first stage of this dissertation. In order to understand the design flow used by Synopsys HARDIP team, a PLL design was made, covering all the stages

More information

ADVANCED VLSI COURSE IN PHYSICAL DESIGN

ADVANCED VLSI COURSE IN PHYSICAL DESIGN ADVANCED VLSI COURSE IN PHYSICAL DESIGN Course covers all advanced topics as prescribed by industry requirements Address: #11, 1st Floor, JCR Tower, Anantha Ram Reddy Layout, Behind Vinyaka Skoda Showroom,

More information

IC Compiler II. Industry Leading Place and Route System. Overview. Accelerating Time to Results on advanced Designs. synopsys.com.

IC Compiler II. Industry Leading Place and Route System. Overview. Accelerating Time to Results on advanced Designs. synopsys.com. DATASHEET IC Compiler II Industry Leading Place and Route System Accelerating Time to Results on advanced Designs Overview IC Compiler II is the leading place and route system delivering industry-best

More information

Static Timing Analysis Techniques for FPGAs LATTICE SEMICONDUCTOR CORPORATION 2006

Static Timing Analysis Techniques for FPGAs LATTICE SEMICONDUCTOR CORPORATION 2006 Static Timing Analysis Techniques for FPGAs 1 Static Timing Analysis Techniques for FPGAs Why STA? Verify the design meets timing constraints Faster than timing-driven, gate-level simulation Ease design

More information

Section II. HardCopy Design Center Migration Process

Section II. HardCopy Design Center Migration Process Section II. HardCopy Design Center Migration Process This section provides information about software support for HardCopy Stratix devices. This section contains the following: Chapter 3, Back-End Design

More information

13. Back-End Design Flow for HardCopy Series Devices

13. Back-End Design Flow for HardCopy Series Devices 13. Back-End esign Flow for HardCopy Series evices H51019-1.4 Introduction This chapter discusses the back-end design flow executed by the HardCopy esign Center when developing your HardCopy series device.

More information

An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction

An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction by Jasmine Kaur Gulati MT14081 Under the Supervision of Dr. Sumit Darak Bhanu Prakash, ST Microelectronics

More information

A Comparative Study on Multisource Clock Network Synthesis

A Comparative Study on Multisource Clock Network Synthesis R2-12 SASIMI 2016 Proceedings A Comparative Study on Multisource Clock Network Synthesis Wen-Hsin Chen, Chun-Kai Wang, Hung-Ming Chen, Yih-Chih Chou, Cheng-Hong Tsai Institute of Electronics, National

More information

Physical Level Design using Synopsys

Physical Level Design using Synopsys 1 Physical Level Design using Synopsys Jamie Bernard, Student MS CpE George Mason University Abstract Very-Large-Scale-Integration (VLSI) of digital systems is the foundation of electronic applications

More information

5. Quartus II Support for HardCopy Stratix Devices

5. Quartus II Support for HardCopy Stratix Devices 5. Quartus II Support for HardCopy Stratix Devices H51014-3.4 Introduction Altera HardCopy devices provide a comprehensive alternative to ASICs. HardCopy structured ASICs offer a complete solution from

More information

TLM-Driven Design and Verification Time For a Methodology Shift

TLM-Driven Design and Verification Time For a Methodology Shift TLM-Driven Design and Time For a Methodology Shift By Jack Erickson, Cadence Design Systems, Inc. Transaction level modeling (TLM) is gaining favor over register-transfer level () for design components

More information

5. Quartus II Support for HardCopy II Devices

5. Quartus II Support for HardCopy II Devices 5. Quartus II Support for HardCopy II Devices H51022-2.5 HardCopy II Device Support Altera HardCopy II devices feature 1.2-V, 90 nm process technology, and provide a structured ASIC alternative to increasingly

More information

Nangate 45nm Open Cell Library. Jesper Knudsen VP Marketing

Nangate 45nm Open Cell Library. Jesper Knudsen VP Marketing Nangate 45nm Open Cell Library Jesper Knudsen VP Marketing 12 th Si2/OpenAccess+ Conference, April 16 th, 2008 Presentation Outline Why did Nangate release an Open Cell Library? Why is Library control

More information

Digital Integrated Circuits

Digital Integrated Circuits Digital Integrated Circuits Lecture 8 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University DIGITAL DESIGN FLOW Chung EPC6055 2 Timing Flip-flop samples D at clock edge D must be stable

More information

IC Validator. Overview. High-performance DRC/LVS physical verification substantially reduces time-to-results. Benefits. synopsys.

IC Validator. Overview. High-performance DRC/LVS physical verification substantially reduces time-to-results. Benefits. synopsys. DATASHEET IC Validator High-performance DRC/LVS physical verification substantially reduces time-to-results Overview Synopsys IC Validator is a comprehensive physical verification signoff solution that

More information

Cadence Transistor-Level EMIR Solution Voltus-Fi Custom Power Integrity Solution

Cadence Transistor-Level EMIR Solution Voltus-Fi Custom Power Integrity Solution Cadence Transistor-Level EMIR Solution Voltus-Fi Custom Power Integrity Solution Scott / Graser 16 / Oct / 2015 Agenda Introduction -- Cadence Power Signoff Solution Transistor-Level EMIR Challenges and

More information

White Paper TimeQuest Timing Analyzer: Native SDC Support for Timing Analysis of FPGA-Based Designs

White Paper TimeQuest Timing Analyzer: Native SDC Support for Timing Analysis of FPGA-Based Designs White Paper TimeQuest Timing Analyzer: Native SDC Support for Timing Analysis of FPGA-Based Designs Introduction The field programmable gate array (FPGA) market has changed significantly in the past few

More information

Hierarchical Design and Analysis Environment. Improve performance and capacity while reducing design time

Hierarchical Design and Analysis Environment. Improve performance and capacity while reducing design time Hierarchical Design and Analysis Environment Improve performance and capacity while reducing design time Design Complexity Increasing More and more FPGA designs are Platform designs today Users integrating

More information

Robustness and Reliability - Facing new Quality Levels for Automotive ICs with Design for Yield

Robustness and Reliability - Facing new Quality Levels for Automotive ICs with Design for Yield International Cooperation Forum Automotive IC-Design Challenges Strategies Trends Munich, Germany, October 25, 2005 Robustness and Reliability - Facing new Quality Levels for Automotive ICs with Design

More information

Integrated Design System Workshop Challenges for CAD Departments in providing Integrated Design Systems

Integrated Design System Workshop Challenges for CAD Departments in providing Integrated Design Systems Integrated Design System Workshop Challenges for CAD Departments in providing Integrated Design Systems Director EDA Alliance Management Base Technologies & Services Communication Solutions Infineon Technologies

More information

StarRC Custom Parasitic extraction for next-generation custom IC design

StarRC Custom Parasitic extraction for next-generation custom IC design Datasheet Parasitic extraction for next-generation custom IC design Overview StarRC is the advanced parasitic extraction solution architected for next-generation custom digital, analog/mixed-signal (AMS)

More information

Section I. HardCopy III Design Flow and Prototyping with Stratix III Devices

Section I. HardCopy III Design Flow and Prototyping with Stratix III Devices Section I. HardCopy III Design Flow and Prototyping with Stratix III Devices Revision Histy This section provides a description of the design flow and the implementation process used by the HardCopy Design

More information

HardCopy II Device Handbook, Volume 2

HardCopy II Device Handbook, Volume 2 HardCopy II Device Handbook, Volume 2 Preliminary Information 101 Innovation Drive San Jose, CA 95134 www.altera.com H5V2-4.5 Copyright 2008 Altera Corporation. All rights reserved. Altera, The Programmable

More information

Using Coverage to Deploy Formal in a Simulation World

Using Coverage to Deploy Formal in a Simulation World Using Coverage to Deploy Formal in a Simulation World Vigyan Singhal and Prashant Aggarwal Oski Technology, Inc. {vigyan,prashant}@oskitech.com Abstract. Formal verification technology has today advanced

More information

Obstacle-aware Clock-tree Shaping during Placement

Obstacle-aware Clock-tree Shaping during Placement Obstacle-aware Clock-tree Shaping during Placement Dong-Jin Lee and Igor L. Markov Dept. of EECS, University of Michigan 1 Outline Motivation and challenges Limitations of existing techniques Optimization

More information

ECE 699: Lecture 2. ZYNQ Design Flow

ECE 699: Lecture 2. ZYNQ Design Flow ECE 699: Lecture 2 ZYNQ Design Flow Required Reading The ZYNQ Book Chapter 3: Designing with Zynq ( How do I work with it? ) Xcell Journal Xilinx Unveils Vivado Design Suite for the Next Decade of All

More information

Overcoming the Challenges in Very Deep Submicron

Overcoming the Challenges in Very Deep Submicron Overcoming the Challenges in Very Deep Submicron for area reduction, power reduction and faster design closure A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of

More information

High Level Tools for Low-Power ASIC design

High Level Tools for Low-Power ASIC design High Level Tools for Low-Power ASIC design Arne Schulz OFFIS Research Institute, Germany 1 Overview introduction high level power estimation µprocessors ASICs tool overview µprocessors ASICs conclusion

More information

IMPLEMENTATION OF LOW POWER ASIC DESIGN BY SCRIPTED FLOW APPROACH. Abstract

IMPLEMENTATION OF LOW POWER ASIC DESIGN BY SCRIPTED FLOW APPROACH. Abstract IMPLEMENTATION OF LOW POWER ASIC DESIGN BY SCRIPTED FLOW APPROACH Mr. Navandar Rajesh Kedarnath 1 & Deokar Subhash Mahadeo 2, Ph. D. Abstract This paper focusing on automated flow using script for physical

More information

Ant Colony Optimization

Ant Colony Optimization Ant Colony Optimization Part 2: Simple Ant Colony Optimization Fall 2009 Instructor: Dr. Masoud Yaghini Outline Ant Colony Optimization: Part 2 Simple Ant Colony Optimization (S-ACO) Experiments with S-ACO

More information

AN 453: HardCopy II ASIC Fitting Techniques

AN 453: HardCopy II ASIC Fitting Techniques AN 453: HardCopy II ASIC Fitting Techniques November 2008 AN-453-2.0 Introduction Engineers often use a flexible, reprogrammable Stratix II FPGA for prototyping a project, and then transfer the design

More information

Moonsu Kim, Kyounghwan Lim and Cheoljun Bae Samsung Electronics Co., Ltd. System LSI Division

Moonsu Kim, Kyounghwan Lim and Cheoljun Bae Samsung Electronics Co., Ltd. System LSI Division Moonsu Kim, Kyounghwan Lim and Cheoljun Bae Samsung Electronics Co., Ltd. System LSI Division 1/9 Design Trend According to advanced process node, - # of cells, voltage, random variation impact - Parametric

More information

HX5000 Design Flow and Infrastructure. Honeywell and Synopsys Enable Next Generation Rad-Hard ASICs

HX5000 Design Flow and Infrastructure. Honeywell and Synopsys Enable Next Generation Rad-Hard ASICs HX5000 Design Flow and Infrastructure Honeywell and Synopsys Enable Next Generation Rad-Hard ASICs Overview Radiation-hardened application specific integrated circuits (ASICs) can now achieve extremely

More information

Expanding the Reach of Formal. Oz Levia November 19, 2013

Expanding the Reach of Formal. Oz Levia November 19, 2013 Expanding the Reach of Formal Oz Levia November 19, 2013 Agenda Jasper Our Product Strategy and Apps Design Coverage App What will it mean to you? Page 2 2013, Jasper Design Automation All Rights Reserved.

More information

Altera s Roadmap. Looking Forward Altera Corporation

Altera s Roadmap. Looking Forward Altera Corporation Altera s Roadmap Looking Forward 2004 Altera Corporation Agenda Technology & Process Product Roadmap & Challenges The Design Environment The System Design Decision HardCopy II Structured ASICs 2 2004 Altera

More information

Thin Nitride Measurement Example

Thin Nitride Measurement Example Thin Nitride Measurement Example GOAL: Get the most information from your data and analyze it properly to make the right decisions! Look at the data in multiple ways to understand your process better.

More information

If it moves, chop it in half, then simulate it

If it moves, chop it in half, then simulate it Interactions of Double Patterning Technology with wafer processing, OPC and design flows Kevin Lucas, Chris Cork, Alex Miloslavsky, Gerry Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Greg Rollins Synopsys

More information

Accelerating Xilinx All Programmable FPGA and SoC Design Verification with Blue Pearl Software

Accelerating Xilinx All Programmable FPGA and SoC Design Verification with Blue Pearl Software Accelerating Xilinx All Programmable FPGA and SoC Design Verification with Blue Pearl Software Introduction Xilinx All Programmable FPGAs and SoCs are used across multiple markets, powering applications

More information

AccuCell. Simucad Sales Training INTERNAL USE ONLY NOT FOR CUSTOMERS

AccuCell. Simucad Sales Training INTERNAL USE ONLY NOT FOR CUSTOMERS AccuCell Simucad Sales Training INTERNAL USE ONLY NOT FOR CUSTOMERS Who Buys Cell Characterization Software? Commercial Libraries Users Who Do Not Have In-house Characterization Tool Characterize Different

More information

High Level Synthesis with Catapult 8.0. Richard Langridge European AE Manager 21 st January 2015

High Level Synthesis with Catapult 8.0. Richard Langridge European AE Manager 21 st January 2015 High Level Synthesis with Catapult 8.0 Richard Langridge European AE Manager 21 st January 2015 Calypto Overview Background Founded in 2002 SLEC released 2005 & PowerPro 2006 Acquired Mentor s Catapult

More information

Sharif University of Technology Introduction to ASICs

Sharif University of Technology Introduction to ASICs SoC Design Lecture 3: Introduction to ASICs Shaahin Hessabi Department of Computer Engineering Sharif University of Technology IC Technology The term ASIC is often reserved for circuits that are fabricated

More information

MAXIMIZE POWER AND EFFICIENCY WITH PADS PLACEMENT AND ROUTING JIM MARTENS, MENTOR GRAPHICS

MAXIMIZE POWER AND EFFICIENCY WITH PADS PLACEMENT AND ROUTING JIM MARTENS, MENTOR GRAPHICS MAXIMIZE POWER AND EFFICIENCY WITH PADS PLACEMENT AND ROUTING JIM MARTENS, MENTOR GRAPHICS P A D S W H I T E P A P E R w w w. m e n t o r. c o m / p a d s INTRODUCTION Printed Circuit Board design is a

More information

Rethinking SoC Verification Enabling Next-Generation Productivity & Performance

Rethinking SoC Verification Enabling Next-Generation Productivity & Performance White Paper Rethinking SoC Verification Enabling Next-Generation Productivity & Performance March 214 Rebecca Lipon Senior Product Marketing Manager, Synopsys Introduction The introduction of the iphone

More information

Hot Chips-18. Design of a Reusable 1GHz, Superscalar ARM Processor

Hot Chips-18. Design of a Reusable 1GHz, Superscalar ARM Processor Hot Chips-18 Design of a Reusable 1GHz, Superscalar ARM Processor Stephen Hill Consulting Engineer ARM - Austin Design Centre 22 August 2006 1 Outline Overview of Cortex -A8 (Tiger) processor What is reusability

More information

What powers your campus?

What powers your campus? What powers your campus? Now, more than ever, it s critical that administrators deliver the on-demand experience students have come to expect while squeezing the most out of reduced budgets. Campus solutions

More information

Verifying High Speed Peripheral IPs by Sreekanth Ravindran and Chakravarthi M.G., Mobiveil

Verifying High Speed Peripheral IPs by Sreekanth Ravindran and Chakravarthi M.G., Mobiveil Verifying High Speed Peripheral IPs by Sreekanth Ravindran and Chakravarthi M.G., Mobiveil Abstract High speed serial interconnect bus fabric is the SoC backbone, managing dataflow and keeping up with

More information

3D & 2½D Test Challenges Getting to Known Good Die & Known Good Stack

3D & 2½D Test Challenges Getting to Known Good Die & Known Good Stack 1 3D & 2½D Test Challenges Getting to Known Good Die & Known Good Stack Advantest Corporation 2 The final yield Any Multi-die Product Must Consider the Accumulated Yield Assume Test Can Provide 99% Die

More information

1. are generally independent of the volume of units produced and sold. a. Fixed costs b. Variable costs c. Profits d.

1. are generally independent of the volume of units produced and sold. a. Fixed costs b. Variable costs c. Profits d. Final Exam 61.252 Introduction to Management Sciences Instructor: G. V. Johnson December 17, 2002 1:30 p.m. to 3:30 p.m. Room 210-224 University Centre Seats 307-328 Paper No. 492 Model Building: Break-Even

More information

How to check complex PCBs for SI/PI/EMC Issues

How to check complex PCBs for SI/PI/EMC Issues 1 Public ETAS/EHS2-Grävinghoff 2015-11-23 ETAS GmbH 2015. All rights reserved, also regarding any disposal, exploitation, Outline Outline Motivation & History EDA Import Rule Setup & EMC/SI/PI Rules Results

More information

TSMC Property. ConFab. Bridging the Fabless-Foundry Gap. BJ Woo. Sr. Director Business Development TSMC TSMC, Ltd

TSMC Property. ConFab. Bridging the Fabless-Foundry Gap. BJ Woo. Sr. Director Business Development TSMC TSMC, Ltd ConFab Bridging the Fabless-Foundry Gap BJ Woo Sr. Director Business Development TSMC 2 Outline Fabless Requirements Technology Scaling Challenges IP Quality Foundry Integrated Manufacturing Value Summary

More information

Defining The Future Through Partnerships

Defining The Future Through Partnerships v2 Apr 21, 2017 Agenda 1. About Us 2. Business Units 3. Customers 4. Quality 5. Markets & Applications 6. Team 7. Value Proposition The Valingro Group Valingro builds Businesses that transcends time Presence

More information

THE PMP EXAM PREP COURSE

THE PMP EXAM PREP COURSE THE PMP EXAM PREP COURSE Session 2 PMI, PMP and PMBOK are registered marks of the Project Management Institute, Inc. www.falconppm.com Agenda 9:00 10:15 Practice the PMP Questions 10:15 10:30 Break 10:30

More information

Development and Characterization of 300mm Large Panel ewlb (embedded Wafer Level BGA)

Development and Characterization of 300mm Large Panel ewlb (embedded Wafer Level BGA) Development and Characterization of 300mm Large Panel ewlb (embedded Wafer Level BGA) Seung Wook Yoon, Yaojian Lin and Pandi C. Marimuthu STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442 E-mail

More information

The Secrets of Optimizing your EHR

The Secrets of Optimizing your EHR EHR Insider s Guide The Secrets of Optimizing your EHR 1 2 3 4 5 6 7 8 Making your EHR run better = leverage. On your mark, get set STOP! Your EHR vendor: The best optimization partner. First, a GAP analysis.

More information

MULTICYCLE LOADING PATTERN SEARCHES FOR END-OF-LIFE SCENARIOS WITH ROSA

MULTICYCLE LOADING PATTERN SEARCHES FOR END-OF-LIFE SCENARIOS WITH ROSA 211 Water Reactor Fuel Performance Meeting Chengdu, China, Sept. 11-14, 211 T2-15 MULTICYCLE LOADING PATTERN SEARCHES FOR END-OF-LIFE SCENARIOS WITH ROSA H.P.M. Gibcus 1, F.C.M. Verhagen 1, J.T. van Bloois

More information

Research Article Modified 16-b Square-root Low Power Area Efficient Carry Select Adder

Research Article Modified 16-b Square-root Low Power Area Efficient Carry Select Adder Research Journal of Applied Sciences, Engineering and Technology 8(21): 222-2226, 214 DOI:1.1926/rjaset.8.1221 ISSN: 24-7459; e-issn: 24-7467 214 Maxwell Scientific Publication Corp. Submitted: September

More information

Bring order to chaos

Bring order to chaos Quintiq Company Planner Bring order to chaos It s an ever demanding and fast-paced world. If you can t deliver on commitments, your competitors will. You ve scaled up your business with specialized equipment,

More information

GENERALIZED TASK SCHEDULER

GENERALIZED TASK SCHEDULER CHAPTER 4 By Radu Muresan University of Guelph Page 1 ENGG4420 CHAPTER 4 LECTURE 4 November 12 09 2:49 PM GENERALIZED TASK SCHEDULER In practical applications we need to be able to schedule a mixture of

More information

High Volume Signal and Power Integrity Design for ASICs

High Volume Signal and Power Integrity Design for ASICs High Volume Signal and Power Integrity Design for ASICs Brian Young brian.young@ti.com Agenda Background SI Methodology Outline SI Numerical Example PI Methodology Outline PI Numerical Example Summary

More information

Project Management. Learning Objectives. What are Projects? Dr. Richard Jerz. Describe or Explain:

Project Management. Learning Objectives. What are Projects? Dr. Richard Jerz. Describe or Explain: Project Management Dr. Richard Jerz 1 Learning Objectives Describe or Explain: What are projects The role of the project manager Work breakdown structure Project management tools (Gantt, PERT, & CPM) The

More information

Project Management. Dr. Richard Jerz rjerz.com

Project Management. Dr. Richard Jerz rjerz.com Project Management Dr. Richard Jerz 1 2010 rjerz.com Learning Objectives Describe or Explain: What are projects The role of the project manager Work breakdown structure Project management tools (Gantt,

More information

QVM: Enabling Organized, Predictable, and Faster Verification Closure by Gaurav Jalan, SmartPlay Technologies, and Pradeep Salla, Mentor Graphics

QVM: Enabling Organized, Predictable, and Faster Verification Closure by Gaurav Jalan, SmartPlay Technologies, and Pradeep Salla, Mentor Graphics QVM: Enabling Organized, Predictable, and Faster Verification Closure by Gaurav Jalan, SmartPlay Technologies, and Pradeep Salla, Mentor Graphics Until recently, the semiconductor industry religiously

More information

Inventory Management 101 Basic Principles SmartOps Corporation. All rights reserved Copyright 2005 TeknOkret Services. All Rights Reserved.

Inventory Management 101 Basic Principles SmartOps Corporation. All rights reserved Copyright 2005 TeknOkret Services. All Rights Reserved. Inventory Management 101 Basic Principles 1 Agenda Basic Concepts Simple Inventory Models Batch Size 2 Supply Chain Building Blocks SKU: Stocking keeping unit Stocking Point: Inventory storage Item A Loc

More information

Intensification of a Perfusion Platform using Single-use XCell ATF Systems

Intensification of a Perfusion Platform using Single-use XCell ATF Systems Intensification of a Perfusion Platform using Single-use XCell ATF Systems Olaf Mol Sr. Bioprocess Scientist The world leader in serving science Global Footprint- Biologics Princeton, USA PD Center of

More information

Thermal Design of SoC at the Micron Scale Rajit Chandra, Ph.D. Founder, CTO Gradient Design Automation Santa Clara, California

Thermal Design of SoC at the Micron Scale Rajit Chandra, Ph.D. Founder, CTO Gradient Design Automation Santa Clara, California Thermal Design of SoC at the Micron Scale Rajit Chandra, Ph.D. Founder, CTO Gradient Design Automation Santa Clara, California www.gradient-da.com 3/19/2008 2008 Gradient Design Automation 1 Electronic

More information

Interlayer Dielectric (ILD) Cracking Mechanisms and their Effects on Probe Processes. Daniel Stillman, Daniel Fresquez Texas Instruments Inc.

Interlayer Dielectric (ILD) Cracking Mechanisms and their Effects on Probe Processes. Daniel Stillman, Daniel Fresquez Texas Instruments Inc. Interlayer Dielectric (ILD) Cracking Mechanisms and their Effects on Probe Processes Daniel Stillman, Daniel Fresquez Texas Instruments Inc. Outline Probe Optimization Why is it needed? Objective and obstacles

More information

Philip Simpson. FPGA Design. Best Practices for Team-based Design

Philip Simpson. FPGA Design. Best Practices for Team-based Design FPGA Design 5 Philip Simpson FPGA Design Best Practices for Team-based Design Philip Simpson Altera Corporation San Jose, CA 95134 USA Feilmidh@sbcglobal.net ISBN 978-1-4419-6338-3 e-isbn 978-1-4419-6339-0

More information

Optimal Quality Assurance for Mass Production Apparel Industry

Optimal Quality Assurance for Mass Production Apparel Industry Optimal Quality Assurance for Mass Production Apparel Industry By: James O'Connell Thesis Advisor: Dr. Albert Tan Summary: The quality assurance process for an apparel company was examined. After determining

More information

Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs

Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs July 2007, v1.0 Application Note 463 Overview Introduction f This application note describes the differences between Stratix II FPGA and HardCopy

More information

TOCICO Critical Chain Project Management Certification Webinar

TOCICO Critical Chain Project Management Certification Webinar TOCICO CCPM Exam Review TOCICO Critical Chain Project Management Certification Webinar Presented By: Janice F. Cerveny, Ph.D. (cervenyj@fau.edu) Date: June 7, 2009 Sample Questions provided (with my gratitude)

More information

Resource Critical Path Approach to Project Schedule Management

Resource Critical Path Approach to Project Schedule Management 1 Resource Critical Path Approach to Project Schedule Management Vladimir Liberzon Spider Management Technologies, spider@mail.cnt.ru RCP definition A Guide to the Project Management Body of Knowledge

More information

DReAM : A System to improve operational efficiency and maintain competency in semiconductor IC design industry. Mar. 8, 2012

DReAM : A System to improve operational efficiency and maintain competency in semiconductor IC design industry. Mar. 8, 2012 DReAM : A System to improve operational efficiency and maintain competency in semiconductor IC design industry Mar. 8, 2012 1 Flexible ASIC Business Model 2 The Initiative of GUC s DReAM 3 Design Workflow

More information

Digital VLSI Design. Lecture 1: Introduction

Digital VLSI Design. Lecture 1: Introduction Digital VLSI Design Lecture 1: Introduction Semester A, 2018-19 Lecturer: Dr. Adam Teman 20 October 2018 Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied

More information

Air-traffic Flow Management with ILOG CP Optimizer. Ulrich Junker ILOG

Air-traffic Flow Management with ILOG CP Optimizer. Ulrich Junker ILOG Air-traffic Flow Management with ILOG CP Optimizer Ulrich Junker ILOG 1 Outline Eurocontrol s Air Traffic Flow Management Problem How to develop a precise and accurate optimization model? How to find good

More information

Project Time Management

Project Time Management Project Time Management Prof. Dr. Daning Hu Department of Informatics University of Zurich Adapted from Managing Information Technology Projects, Schwalbe Learning Objectives Define activities as the basis

More information

Full-Chip Power/Performance Benefits of Carbon Nanotube- Based Circuits

Full-Chip Power/Performance Benefits of Carbon Nanotube- Based Circuits J. lnf. Commun. Converg. Eng. 13(3): 180-188, Sep. 2015 Regular paper Full-Chip Power/Performance Benefits of Carbon Nanotube- Based Circuits Taigon Song and Sung Kyu Lim*, Member, KIICE School of Electrical

More information

Capital Harness. The de facto software solution for the electrical wire harness industry

Capital Harness. The de facto software solution for the electrical wire harness industry Capital Harness The de facto software solution for the electrical wire harness industry CAPITAL HARNESS A comprehensive set of software tools that enable the design, engineering for manufacture, validation

More information

A Conditional Probability Model for Vertical Multithreaded Architectures

A Conditional Probability Model for Vertical Multithreaded Architectures A Conditional Probability Model for Vertical Multithreaded Architectures Robert M. Lane rmlkcl@mindspring.com Abstract Vertical multithreaded architectures can be estimated using a model based on conditional

More information

$250,000,000 Failure. What Would You Do? April 23, Copyright ecameron, Inc. 1

$250,000,000 Failure. What Would You Do? April 23, Copyright ecameron, Inc. 1 $250,000,000 Failure What Would You Do? 1 PMI s Talent Triangle 4/23/2016 Real Project Audit Case Study 4/23/2016 Rules Actual project decisions points Rules Roundtable Discussion Rules You just can t

More information

Artificial Intelligence Breadth-First Search and Heuristic

Artificial Intelligence Breadth-First Search and Heuristic Artificial Intelligence Breadth-First Search and Heuristic Chung-Ang University, Jaesung Lee The original version of this content is came from MIT OCW of MIT Electrical Engineering and Computer Science

More information

SCHEDULING AND THE POWER OF AI

SCHEDULING AND THE POWER OF AI SCHEDULING AND THE POWER OF AI Moderated by Scott Blair Managing Editor Engineering News-Record SCHEDULING AND THE POWER OF AI Chris Callen CEO Grit Virtual, Inc. Michael Gekas, AIA Virtual Construction

More information

ALLEGRO PCB LIBRARIAN 610

ALLEGRO PCB LIBRARIAN 610 DATASHEET ALLEGRO PCB LIBRARIAN 610 AUTOMATED LIBRARY PART CREATION, VALIDATION, AND MANAGEMENT Cadence Allegro PCB Librarian 610, a 600 series product within the Allegro system interconnect design platform,

More information

Production error analysis for a line of manufacturing machines, variable structure control approach Starkov, K.; Pogromskiy, A.Y.; Rooda, J.E.

Production error analysis for a line of manufacturing machines, variable structure control approach Starkov, K.; Pogromskiy, A.Y.; Rooda, J.E. Production error analysis for a line of manufacturing machines, variable structure control approach Starkov, K.; Pogromskiy, A.Y.; Rooda, J.E. Published in: Proceedings of the APMS International Conference

More information

EDA Technologies Fueling IoT Implementation, Current and Future

EDA Technologies Fueling IoT Implementation, Current and Future EDA Technologies Fueling IoT Implementation, Current and Future Michael Thompson Internet of Things (IoT) Summit, RWW 2018 Anaheim, California January 14, 2018 IoT Standards/Applications 2 Industry Trends

More information

From Russia With Love:

From Russia With Love: From Russia With Love: Truly Integrated Project Scope, Schedule, Resource and Risk Information Vladimir Liberzon, PMP and Russell D. Archibald, PMP Presentation Objectives Describe proven methods used

More information

1. HardCopy IV Design Flow Using the Quartus II Software

1. HardCopy IV Design Flow Using the Quartus II Software January 2011 HIV52001-2.2 1. HardCopy IV Design Flow Using the Quartus II Sotware HIV52001-2.2 This chapter provides recommendations or HardCopy IV development, planning, and settings considerations in

More information

Automating the In-Circuit Test in Your Factory

Automating the In-Circuit Test in Your Factory Automating the In-Circuit Test in Your Factory Measurement Test Division Keysight Technologies July 23, 2015 Agenda Page 2 Overview of Inline ICT automation - Introduction to Keysight & In Circuit Test

More information

CIS QA LEVEL 2 WEEK 5 TOPIC: LINEAR PROGRAMMING OBJECTIVE AND SHORT ANSWER QUESTIONS

CIS QA LEVEL 2 WEEK 5 TOPIC: LINEAR PROGRAMMING OBJECTIVE AND SHORT ANSWER QUESTIONS CIS QA LEVEL 2 WEEK 5 TOPIC: LINEAR PROGRAMMING OBJECTIVE AND SHORT ANSWER QUESTIONS 1. In the graphical method of solving a Linear Programming problem, the feasible region is the region containing A.

More information

Mindset Shift of Here and Now

Mindset Shift of Here and Now Mindset Shift of Here and Now Jennifer Kalz, CBAP, CUA, CSM May 23 rd, 2018 Learning Objectives Understand the shifts in thinking that need to occur within the organization Understand the underlying reason(s)

More information

Closing the gap between ASIC & Custom

Closing the gap between ASIC & Custom Closing the gap between ASIC & Custom Chapters 9, 10 and 11 Presented by Raimo Mäkelä Content of presentation Chapter 9 Faster and Lower Power Cell-Based Design with Transistor-Level Cell Sizing Chapter

More information

Alternatives to Vertical Probing

Alternatives to Vertical Probing Alternatives to Vertical Probing Philip W. Seitzer Distinguished Member of Technical Staff Equipment Engineering & Development Lucent Technologies, Allentown, PA 6/4/00 1 Outline Vertical Probing Background

More information

Assurity Life. We wanted a process that would get all of an agent s information into the system from start to finish, with minimal human intervention.

Assurity Life. We wanted a process that would get all of an agent s information into the system from start to finish, with minimal human intervention. success story Company snapshot Insurance Company has provided protection and peace of mind to customers for over 125 years. The company s roots go back to the late 1800s when it began serving customers

More information