Chapter 9: Multiplication.. Saj Alam and Samya Zain

Transcription

1 Chapter 9: Multiplication.. Saj Alam and Samya Zain Monday November 6,

2 Simple Multiplication Examples

3 Multiplication A B = C A= Multiplicand n A = Number of digits of Multiplicand (A) B = Multiplier n B = Number of digits of Multiplier (B) C = product n C n A + n B 3

4 Example 1: 53 n A = 2 10 n B = n C = 3 n C < n A + n B Example 2: n A = 2 n B = n C = n A + n B 3915 n C = 4 4

5 Binary Number System System Digits: 0 and 1 Bit (short for binary digit): A single binary digit LSB (least significant bit): The rightmost bit MSB (most significant bit): The leftmost bit 53 = MSB LSB 5

6 Binary To Decimal Conversion = = = = = = = 6

7 Binary Multiplication Example 1: MSB multiplication LSB addition Example 2: Example 3: 7

8 Decimal = Multiplicand(MC) ; n A = 2 = Multiplier(MP) ; n B = 2 = product ; n C n A + n B 53 = = Binary weight Binary Bit0 : start product Bit1 : MC shifted left Bit2 : MC shifted left Bit3 : MC shifted left product Bit4 : MC shifted left =1166 8

9 Left Shift Algorithm (LSA) Step1:Write the Multiplicand(MC) and the Multiplier(MP) with LSB lined up. Step2: Look at LSB of Multiplier. IF LSB MP = 0 put {00 n A } as initial product IF LSB MP = 1 copy Bit0 of MC as initial product Step3: Look at the next LSB bit (Bit1 MP ) of Multiplier. IF Bit1 MP = 0 put {00 n A } as product 2 IF Bit1 MP = 1 Shift left and copy Bit1 of MC as product 2 Step4:Repeat STEP 3 until all bits in the MP are used up. Step5:Check the number of digits or bits in the MC and MP. n C n A + n B 9

10 Right Shift Algorithm (RSA) Decimal Multiplication 10

11 initial product shift right one digit shift right one digit shift right one digit final product 11

12 Decimal 47 = 33 = = 1551 shift right one digit Add & shift right one digit Binary Binary weight initial product Add & shift right one digit Add & shift right one digit Add & shift right one digit = Multiplicand(MC) = Multiplier(MP) final product =

13 Right Shift Algorithm (RSA) Step1:Write the Multiplicand(MC) and the Multiplier(MP) with LSB lined up. Step2: Put initial product {000 n A } Step3a: Look at LSB of Multiplier. IF LSB MP = 0 put {00 n A } as product 2 IF LSB MP = 1 copy Bit0 of MC as product 2 Step3b: add initial product and product 2 Step3c: Shift the resulting sum one digit to right. Step4a: Look at the next LSB bit (Bit1 MP ) of Multiplier. IF Bit1 MP = 0 put {00 n A } as product 3 IF Bit1 MP = 1 copy Bit1 of MC as product 3 Step4b: add product2 and product 3 Step4c: Shift the resulting sum one digit to right. Step5: Repeat Steps 4a, 4b and 4c until all bits in the MP are used up. Step6:Check the number of digits or bits in the MC and MP. n C n A + n B 13

14 Try yourself:

15 Right Shift Algorithm (RSA) for 16- Bit Multiplication Wednesday November 8,

16 16- Bit Multiplication AX DX BX CX CF Multiplicand = FFFF Multiplier = FFFF AX Multiplier BX Multiplicant DX Bit count CX CF FF FF FF 00 FF 10H CF 16

17 AX SUB AX, AX ; AX ; CF Multiplier BX MOV BX, MPLY Multiplicant DX MOV DX, MCAND Bit count CX MOV CX, 10H ; number of bits CF Examine LSB of MPLIER RCR BX, 1 ; Examine LSB of MPLIER NEXT: Bit = 0 JNC SHIFT ; skip addition step if bit = 0 NO YES Add MCND to AX ADD AX, DX ; add MCAND to product YES Shift the product right by 1 bit. Re-examine the next bit. Decrement counter Is CX = 0? Store final product in memory NO SHIFT: RCR AX, 1 ; shift the product 1 bit right RCR BX, 1 ; & examine next bit of MPLY DEC CX ; change counter down by 1 JCXZ DONE ; if CX = 0, all bits are done JMP NEXT ; otherwise go on to next bit DONE: MOV PRODL, BX ; store low word MOV PRODH, AX ; store high word 17 RET

18 AX DX AX DX AX SUB AX, AX ; AX ; CF Multiplicand = F F DX MOV DX, MCAND Multiplier = 3 BX MOV BX, MPLY Bit count CX MOV CX, 10H ; number of bits F0 0F RCR BX, 1 ; Examine LSB of MPLIER No change No change H No change BX CX BX CX CF CF 1 AX DX NEXT: JNC SHIFT ; skip addition step if bit = 0 ADD AX, DX ; Since CF = 1 & put in AX F0 0F No change No change Note: CF is reset BX CX CF 0 18

19 SHIFT: RCR AX, 1 ; shift the product 1 bit right AX DX AX DX Put CF = 0 and Right shift all values No change RCR BX, 1 ; & examine next bit of MPLY (BX) AX DX No change No change DEC CX ; change counter down by No change No change As CX 0 : JCXZ DONE ; if CX = 0, all bits are done JMP NEXT ; otherwise go on to next bit JNC SHIFT ; skip addition step if bit = 0 & CF = 1: ADD AX, DX No change No change No change H No change H BX CX BX CX BX CX CF 1 CF 1 CF 1 Note: CF did not change 19

20 AX DX Carry OverFlow AX DX AX DX Adding: ADD result in AX: No change SHIFT: RCR AX, 1 ; shift the product 1 bit right RCR BX, 1 ; & examine next bit of MPLY DEC CX ; change counter down by 1 JCXZ DONE ; if CX = 0, all bits are done JMP NEXT ; otherwise go on to next bit No change H No change No change H H BX CX BX CX BX CX CF 1 CF 1 CF 0 20

21 AX DX DEC CX ; change counter down by No change No change As CX 0 & CF = 0: SHIFT: RCR AX, 1 ; shift the product 1 bit right RCR BX, 1 ; & examine next bit of MPLY No change H BX CX CF 0 AX DX No change No change H BX CX CF 1 AND SO ON untill the counter CX comes to 0H.. 21

22 ;***************************************************************************** TITLE MAIN PROGRAM MUL16(UNSIGNED) ; ; Author: M. Sajjad Alam (University at Albany) ; ; This program multiplies two 16-bit numbers. The numbers to be multiplied are stored in the data segment at MPLY and MCND. Space is reserved at ; PRODL and PRODH for the product. The program multiplies unsigned numbers using the right shift algorithm. ; The largest two numbers that can be multiplied are: FFFFh and FFFFh or in decimal and For the purpose of testing the program, we suggest ; you test the program for the following examples: ;FFFFh x 10h = FFFF0h, FFFFh x 100h = FFFF00h, FFFFh x 1000h = FFFF000h ; FFFFh x Fh = EFFF1h, FFFFh x FFh = FEFF01h, FFFFh x FFFh = FFEF001h ; FFFFh x FFFFh = FFFE0001 ; INPUT: DX <- Multiplicand ; BX <- Multiplier ; CX <- Bit Counter = 10h = 16 ; OUTPUT: AX <- High word of product ; BX <- Low Word of product ;***************************************************************************** SSEG SEGMENT PARA STACK 'STACK' ; Start of Stack Segment DB 64 DUP('STACK') ; Reserve 64 bytes SSEG ENDS ; End of Stack Segment ;***************************************************************************** DSEG SEGMENT PARA PUBLIC 'DATA' ; Start of data segment ; Enter here the data words MCND DW 0FFFFH ; Store multiplicand MPLR DW 0FFFH ; Store multiplier ; Reserve two words for the product PRODL DW? ; Low byte of Product PRODH DW? ; High byte of Product DSEG ENDS ; End of data segment ;***************************************************************************** CSEG SEGMENT PARA PUBLIC 'CODE' ; Start of Code Segment ASSUME CS:CSEG, DS:DSEG, SS:SSEG MUL16 PROC FAR 22

23 ; Set up the Stack with proper values to return to DOS or DEBUG PUSH DS ; Save DS on the stack SUB AX,AX ; Load 0 into AX PUSH AX ; Save 0 on the stack ; Initialize the Data Segment registers MOV AX,DSEG ; Store Address DSEG in AX MOV DS,AX ; Transfer AX to Data Seg Reg ; ; Programming task starts here START: SUB AX,AX ; Store 0 in AX and clear CF MOV BX,MPLR ; Store multiplier in BX MOV DX,MCND ; Store multiplicand in DX MOV CX,16 ; Store # of bits in CX RCR BX,1 ; Rotate BX one bit right NEXT: JNC SHIFT ; If CF=1, skip the adding ADD AX,DX ; Add multipicand to AX SHIFT: ; Perform right shift of prod RCR AX,1 ; Right shift of AX thru CF RCR BX,1 ; Right shift CF into BX DEC CX ; Decrease bit count by 1 JCXZ DONE ; Done if bit count is 0 JMP NEXT ; Otherwise loop for next bit DONE: ; Multiplication is finished MOV PRODL,BX ; Store low word at PRODL MOV PRODH,AX ; Store high word at PRODH RET ; return to debug MUL16 ENDP CSEG ENDS END MUL16 23

24 **************************************************************** MUL16 MULTIPLICATION OF TWO 16-BIT NUMBERS Author: M. Sajjad Alam Date: November 4, 1996 Debug session showing the multiplication of 0FFh by 0FFFFh C:\PHY353\MUL16>debug mul16_m.exe -u 1B5E:0000 1E PUSH DS 1B5E:0001 2BC0 SUB AX,AX 1B5E: PUSH AX 1B5E:0004 B85D1B MOV AX,1B5D 1B5E:0007 8ED8 MOV DS,AX 1B5E:0009 2BC0 SUB AX,AX 1B5E:000B 8B1E0000 MOV BX,[0000] 1B5E:000F 8B MOV DX,[0002] 1B5E:0013 B91000 MOV CX,0010 1B5E:0016 D1DB RCR BX,1 1B5E: JNB 001C 1B5E:001A 03C2 ADD AX,DX 1B5E:001C D1D8 RCR AX,1 1B5E:001E D1DB RCR BX,1 1B5E: DEC CX 1B5E:0021 E302 JCXZ B5E:0023 EBF3 JMP B5E: E0400 MOV [0004],BX 1B5E:0029 A30600 MOV [0006],AX 1B5E:002C CB RETF We want to get past the point where the data segment register is loaded and the data segment is defined. At offset 0009, we have already moved the data segment offset value 1B5D into the data segment register DS. -g9 AX=1B5D BX=0000 CX=017D DX=0000 SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=0009 NV UP EI PL ZR NA PE NC 1B5E:0009 2BC0 SUB AX,AX

25 We can now do a dump of the data segment and identify the location of the data words corresponding to multiplicand and multiplier Note the mulplicand 0FFFH was the first data word in the data segment and now present at location 1B5D:0000. The multiplier 0FFH which is the second data word in the data segment is 0FFH which is equivalent to 00 FF. In the memory the lower byte FFH is loaded first, followed by the high byte 00H as can be seen at location 1B5D:0003 and 1B5D:0004, respectively B5D:0000 1B5D:0003 -dds:00 1B5D:0000 FF FF FF B5D:0010 1E 2B C0 50 B8 5D 1B 8E-D8 2B C0 8B 1E B.+.P.] B5D: B D1 DB C2 D1 D8 D1 DB...s... 1B5D: E3 02 EB F3 89 1E A CB 13 A1 06 I... 1B5D:0040 3C 8B C A3 1A C 41 C6 06 B2 10 <...<..A...A... 1B5D:0050 FF 5E 8B E5 5D C3 55 8B-EC 56 8B 5E 04 8B ^..].U..V.^..v. 1B5D:0060 8B B8 FF-FF 5E 5D C3 8B B..9.s...^]..v B5D: B E 5D C3 90 2B C0 5E 5D.9.v...^]..+.^] A look at the general purpose registers shows that they have data from previous operations sitting in them at this stage r AX=1B5D BX=0000 CX=017D DX=0000 SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=0009 NV UP EI PL ZR NA PE NC We will now carry on the necessary steps so that we have the registers AX, BX, CX, and DX loaded with the multiplier and multiplicand B5E:000B 8B1E0200 MOV BX,[0002] DS:0002=00FF -t AX=0000 BX=00FF CX=017D DX=0000 SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=000F NV UP EI PL ZR NA PE NC 1B5E:000F 8B MOV DX,[0000] DS:0000=FFFF -t AX=0000 BX=00FF CX=017D DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=0013 1B5E:0013 B91000 MOV CX,0010 -t NV UP EI PL ZR NA PE NC AX=0000 BX=00FF CX=0010 DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=0016 NV UP EI PL ZR NA PE NC 25

26 Note: now the AX=0000, the initial product. BX contains the multiplier and DX contains the multiplicand. The register CX is loaded with the counter 10H or 16, indicating the number of shifts needed to complete the multiplication. We are now ready to shift the multiplier right into the carry bit to examine if the bit is a '1' or '0' AX=0000 BX=00FF CX=0010 DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=0016 NV UP EI PL ZR NA PE NC 1B5E:0016 D1DB RCR BX,1 -t AX=0000 BX=007F CX=0010 DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=0018 NV UP EI PL ZR NA PE CY 1B5E: JNB 001C Note when RCR BX,1 is executed, the 1 in the LSB (least significant bit) of register BX is shifted to the carry flag so that is now read CY. BX now reads 007FH which is exactly what you expect if you shift right by one bit. The '0' from the 9th bit shifts into the 8th bit position, the '1' from the 5th bit position moves into the 4th bit position and the '1 from the 1st bit moves into the carry flag. In the meantime, the 0 from the carry flag moves into the 16th bit. We have 007FH left in register BX. Note: the 1st bit of the multiplier moved into the carry flag is a '1' so we have to add the multiplicand in register DX to the intermediate product in AX. The instruction at offset 0018 when executed changes the next instruction counter IP to offset 001A t AX=0000 BX=007F CX=0010 DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=001A NV UP EI PL ZR NA PE CY 1B5E:001A 03C2 ADD AX,DX -t AX=FFFF BX=007F CX=0010 DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=001C NV UP EI NG NZ NA PE NC 1B5E:001C D1D8 RCR AX, Register AX now contains the sum of the multiplicand in register DX and the initial product Note : the carry flag has been reset to NC or '0'. We are ready to shift the intermediate product right by one bit into the register BX t AX=7FFF BX=007F CX=0010 DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=001E OV UP EI NG NZ NA PE CY When we executed RCR AX,1, the LSB of AX was moved into the carry flag, changing it to CY. Also note the '0' from the carry flag has been stuffed into the MSB (most significant bit) of AX so that the highest nibble in AX is 7 instead of F. Further the LSB bit of BX or the next multiplier bit is presented into the carry flag leaving 26 as CY or "1".

27 -t AX=7FFF BX=007F CX=0010 DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=001E OV UP EI NG NZ NA PE CY 1B5E:001E D1DB RCR BX, When we executed RCR BX,1, the LSB of BX is shifted into the carry flag and the LSB of AX sitting in the carry flag is shifted to the highest bit of the register BX. This completes the shift of the register combination AX BX right by one bit t AX=7FFF BX=803F CX=0010 DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=0020 OV UP EI NG NZ NA PE CY 1B5E: DEC CX When we executed RCR BX,1, the LSB of BX is shifted into the carry flag and the LSB of AX sitting in the carry flag is shifted to the highest bit of the register BX. This completes the shift of the register combination AX BX right by one bit t AX=7FFF BX=803F CX=000F DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=0021 NV UP EI PL NZ AC PE CY 1B5E:0021 E302 JCXZ t AX=7FFF BX=803F CX=000F DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=0023 NV UP EI PL NZ AC PE CY 1B5E:0023 EBF3 JMP We have completed examining the first bit of the multiplier so we decrease the CX counter by 1 so that CX = 000FH. Since this is not '0', the jump to end of the looping is skipped and the instruction pointer IP is set to the next location, given by offset t AX=7FFF BX=803F CX=000F DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=0018 NV UP EI PL NZ AC PE CY 1B5E: JNB 001C We are back at the point where are ready to check the carry flag carries a '0' or '1' from the next bit of the mutliplier in register BX. In the meantime, the intermediate product has been shifted one bit to the right. And we are into the second loop already. We want to shorten our work, so we jump to the end of loop. 27

28 We are back at the point where are ready to check the carry flag carries a '0' or '1' from the next bit of the multiplier in register BX. In the meantime, the intermediate product has been shifted one bit to the right. And we are into the second loop already. We want to shorten our work, so we jump to the end of loop g21 AX=BFFF BX=401F CX=000E DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=0021 NV UP EI PL NZ NA PO CY 1B5E:0021 E302 JCXZ t AX=BFFF BX=401F CX=000E DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=0023 NV UP EI PL NZ NA PO CY 1B5E:0023 EBF3 JMP t AX=BFFF BX=401F CX=000E DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=0018 NV UP EI PL NZ NA PO CY 1B5E: JNB 001C Above, we have completed the multiplication by the second bit. The counter CX has been decremented by 1 to 000EH. We are ready to start examining the third bit of the multiplier which is present as CY or '1'. We do not wish to demonstrate all the identical loop for the remaining bits so we will jump to the part where multiplication by all bits have been executed. The counter CX=0 at this stage

29 -g25 AX=00FE BX=FF01 CX=0000 DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=0025 NV UP EI PL ZR NA PE NC 1B5E: E0400 MOV [0004],BX DS:0004=0000 -t AX=00FE BX=FF01 CX=0000 DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=0029 NV UP EI PL ZR NA PE NC 1B5E:0029 A30600 MOV [0006],AX DS:0006=0000 -t AX=00FE BX=FF01 CX=0000 DX=FFFF SP=013C BP=0000 SI=0000 DI=0000 DS=1B5D ES=1B39 SS=1B49 CS=1B5E IP=002C NV UP EI PL ZR NA PE NC 1B5E:002C CB RETF We executed all instructions up to code offset 0025H. Here the counter CX=0 signifies that 16 shifts have taken place and mutliplication by the 16 bits in the multiplier have been completed. The product should be in registers AX BX = 00FE FF01 which is indeed what the product of FFFFH x FF should be. Below, we show where the product is stored in the data segment. The low word of the product in register BX is loaded first at the location 1B5D:0004 and 1B5D:005 with the low byte being loaded before the higher byte. Again, the higher word of the product in register AX=00FE is loaded at location 1B5D:0006 and 1B5D: AX: 1B5D:0006 & 1B5D:0007 -dds:00 BX :1B5D:0004 & 1B5D:0005 1B5D:0000 FF FF FF FF FE product stored here 1B5D:0010 1E 2B C0 50 B8 5D 1B 8E-D8 2B C0 8B 1E B.+.P.] B5D: B D1 DB C2 D1 D8 D1 DB...s... 1B5D: E3 02 EB F3 89 1E A CB 0F 2B C0 I B5D: E8 7B C F8 EB 06 8B 5E F8 PW.{...F...^. 1B5D:0050 C FF 46 F8 8B 46-F8 A3 06 3A 56 E8 D F..F...:V... 1B5D: C4 02 0B C0 76 0B 56-FF 36 E0 11 E8 7B v.V.6...{.. 1B5D:0070 C B E C4 04 B W..@P.p... 29

30 30

31 BACK UP SLIDES 31

32 53 = 22 = Bit0 : start product = Multiplicand ; MC = Multiplier ; MP 32

33 33

34 And Truth Table Or Truth Table Exclusive Or Truth Table 34

35 AND Gate: a logic circuit designed to compare TRUE-FALSE (or on-off or one-zero) inputs and pass a resultant TRUE signal only when all the inputs are TRUE. Binary: having two components or possible states. Binary code: a system for representing things by combinations of two symbols, such as one and zero, TRUE and FALSE, or the presence or absence of voltage. Binary number system: a number system that uses two as its base and expresses numbers as strings of zeros and ones. Bit: the smallest unit of information in a computer, equivalent to a single zero or one. The word "bit" is a contraction of binary digit. Boolean algebra: a method for expressing the logical relationships between entities such as propositions or on-off computer circuit; invented by the 19th Century English mathematician George Boole. Byte: a sequence of bits, usually eight, treated as a unit for computation or storage. Carry: the digit added to the next column in a an additional problem when the sum of the numbers in a column equals or exceeds the number base. Kilobyte: 1,024 bytes (1,024 being one K, or two to the 10th power); often used as a measure of memory capacity. Logic Gate: a circuit that accepts one or more than one input and always produces a single predicatable output. OR gate: a circuit designed to compare binary TRUE-FALSE (or on-off or one-zero) inputs and pass a resultant TRUE signal if any input is TRUE. XOR gate: a circuit designed to compare binary TRUE-FALSE (or on-off or one-zero) inputs and pass a resultant TRUE signal if a single input is TRUE, otherwise the output is FALSE. 1 Bit = Binary digit 1 Byte = 8 Bits 1 Kilobyte = 1,000 Bytes 1 Megabyte = 1,000 Kilobytes 1 Gigabyte = 1,000 Megabytes 1 Terabyte = 1,000 Gigabyte 1 Pet byte = 1,000 Terabytes 1 Exabyte = 1,000 Petabytes 1 Zettabyte = 1,000 Exabytes 1 Yottabyte = 1,000 Zettabytes 35