Rapid Assessment of Passive Components Using Step Stress Tests

Transcription

1 Rapid Assessment of Passive Components Using Step Stress Tests Anto Peter, Michael H. Azarian, Michael Pecht Center for Advanced Life Cycle Engineering University of Maryland, College Park ASTR 2015, Sep 9 11, Cambridge, MA 1

2 IntroducLon OEMs have a lot of choices when it comes to choosing suppliers for both new and tradilonal passive part technologies. Modern passive components are highly reliable. Accelerated life tests with constant stress levels laslng several thousands of hours may slll not produce many failures. This makes it infeasible for OEMs to use tradilonal accelerated tests to perform part and supplier seleclon. Accelerated life tests should be designed to produce the same failure mechanisms as the end use condilons, ensuring that components are not overstressed. Overstress thresholds are not clearly defined for newer technologies. ASTR 2015, Sep 9 11, Cambridge, MA 2

3 Step Stress TesLng Methodology Stress Level Sudden Death Region Overstress Region IniLal Measurement Stress applicalon Discharge/Cool down Measure Parameters Max Rated Opera2ng Condi2ons Increment stress level Time Step stress teslng is a type of accelerated life test using Lme varying stress applicalon. Step stress tests deliberately stress components to levels beyond their rated operalng condilons. ORen, these tests are used to idenlfy the level under a certain stress at which a component fails. Can step stress tes*ng can be used as a rapid assessment tool? Can step stress be used to design accelerated life tests? ASTR 2015, Sep 9 11, Cambridge, MA 3

4 Case Studies: EDLCs and Ta Capacitors Electric double layer capacitors (EDLCs) and polymer Tantalum (Ta) capacitors: newer capacitor technologies; highest specific capacitances (capacitance per unit volume or weight) available; high operalonal reliabililes. LiXle informalon available on accelerated teslng for these components Good candidates for step stress test analysis. EDLCs from several manufacturers were subjected to two single stress tests. Though single stress tests are widely used, they do not provide insights into the interaclon of different stress condilons. For polymer Ta capacitors, we also tested the compelng MnO 2 Ta capacitor technology. These capacitors were subjected to two simultaneous stresses. MulL- stress tests provide insights into the interplay of different failure mechanisms produced by mullple stresses and interaclon of combined stresses, though interpretalon of results is more challenging. ASTR 2015, Sep 9 11, Cambridge, MA 4

5 Capacitors Charge Storage Principles Electrode Dielectric Electrode + Oxide layer (dielectric) + Separator Electrolyte Film capacitors C= ε 0 ka/d ElectrolyLc capacitors Current collector Porous carbon electrode + Separator Electrolyte Current collector Electrode Separator Electrolyte Li ions + Current collector EDLCs Li ion baxeries ASTR 2015, Sep 9 11, Cambridge, MA 5

6 EDLCs - Background EDLCs, or Electrical Double Layer Capacitors, belong to a class of capacitors known as ultracapacitors or supercapacitors; and have capacitances in the range F. Charge storage occurs at the double layer, due to electrostalc forces Typical cycle life - 100, ,000 cycles. EDLCs are used alongside other rechargeable energy sources such as Li- ion baxeries. ApplicaLons BaXery packs in hybrid and electric vehicles RegeneraLve braking and KineLc energy recovery system (KERS) Memory / RAID controller cards ASTR 2015, Sep 9 11, Cambridge, MA 6

7 EDLC Samples Sample A 4.7 F / 2.5 V Sample B 2.2 F / 2.7V Sample C 5 F / 2.7 V Sample D 2.2 F / 2.5 V Sample E 350 F / 2.5 V Sample F 9 F / 2.5 V Sample G 5 F / 5 V ASTR 2015, Sep 9 11, Cambridge, MA 7

8 Measurement Capacitance and DC Resistance Measurement procedure and calculalons are based on the standards JIS / IEC Charging Charging (30 minutes) (30 minutes) U R Rated voltage U Voltage U 2 C = I D ( t U U 1 2 t1) 2 R DC = ΔU I D U 1 Constant current method (Capacitance) DC resistance method (DCR) t 1 t 2 Time ASTR 2015, Sep 9 11, Cambridge, MA 8

9 EDLC Temperature Step Stress Tests Temperature Stress ( C) Samples measured at room temperature once every hour. No electrical bias applied during stressing 1 hour T R +10 C +20 C +30 C +40 C 150 C x Time (hours) C and DCR measured prior to any stressing; Temperature stresses were applied to each sample in the absence of any electrical stresses. The stress level was started at the rated maximum operalon temperature (varied), and incremented in steps of 10 C. Each stress level held for 1 hour. C and DCR were measured between successive stress levels at room temperature. ASTR 2015, Sep 9 11, Cambridge, MA 9

10 EDLC Temperature Stress Tests 5 Capacitance VariaLon % Change in capacitance Sample B Sample A A B C D E F G - 20 Temperature stress above max opera*ng temperature ( C) All samples showed a decrease in capacitance with increase in temperature. Sample B showed a drop in capacitance greater than 20%. The shaded region indicates the margin outside the rated max where accelerated teslng could be performed. ASTR 2015, Sep 9 11, Cambridge, MA 10

11 EDLC Temperature Stress Tests DC Resistance VariaLon Sample B Sample C Sample A A B C % Change in DCR D E F G Temperature stress above max opera*ng temperature ( C) The DC resistance of the samples did not show much varialon (<30%) at temperatures below a delta of 40 C (temp~100 C). Samples A, B and C showed greatest increase in DCR. ASTR 2015, Sep 9 11, Cambridge, MA 11

12 EDLC Voltage Step Stress Tests No temperature stresses applied during voltage stressing Voltage Stresses (V) 30 mins V R +0.5V +1.0V +1.5V 5V 1 2 x Time (hours) C and DCR measured prior to any stressing; Voltage stresses were applied to each sample in the absence of any thermal stresses (room temperature) The stress level was started at the rated voltage (varied), and incremented in steps of 0.5 V. Each stress level held for 30 minutes. C and DCR were measured between successive stress levels at room temperature. ASTR 2015, Sep 9 11, Cambridge, MA 12

13 EDLC Voltage Step Stress Tests Capacitance VariaLon 15 % Change in Capacitance Sample F A B C D - 10 Sample C F Voltage Stress above rated voltage (V) An inilal increase in capacitance was observed in all samples with 0.5V of voltage stress (over rated V). Sample C had the greatest drop in capacitance (~19%) ASTR 2015, Sep 9 11, Cambridge, MA 13

14 EDLC Voltage Step Stress Tests DC Resistance VariaLon 1400 Sample C 1200 A % Change in DCR Sample F B C D 200 F Voltage Stress above rated voltage (V) The DC resistance of all samples increased with increase in voltage. Samples C, D and F failed due to an increase in DCR. ASTR 2015, Sep 9 11, Cambridge, MA 14

15 EDLC Failure Mechanisms Electrolytes in EDLCs were found to contain propylene carbonate using FTIR; PC is known to cause exfolialon (cracking) of carbon under electrical bias Elevated voltage and temperature condilons causes formalon of resislve films known as Solid Electrolyte Interphase (SEI) Factors causing loss of charge carriers: SEI formalon, gas generalon, electrolyte leakage and other side reaclons affects capacitance Factors causing loss of ion mobility: Loss of surface porosity of electrodes, degradalon of separator affects DCR Propylene Carbonate (PC) Increasing Temperature ExfoliaLon SEI formalon SolvaLon Sheath X + Increasing voltage Increasing voltage ASTR 2015, Sep 9 11, Cambridge, MA 15

16 Lessons from EDLC Step Stress Tests Overstress mechanisms Excessive exfolialon, highly accelerated SEI growth Wear- out mechanisms SEI layer (side reaclons), normal exfolialon Voltage stresses 0.5V above rated maximum could cause excessive exfolialon. Voltages in excess of 1V over rated voltage or temperatures at least 60 C in excess of rated specificalon could cause rapid SEI formalon. Failure mechanisms underlying temperature and voltage stresses are idenlcal, if the intermediate exfolialon step is excluded. If both the stresses were combined, the recommended windows of individual stresses for accelerated teslng would be narrower (confirmed by later teslng). De- ralng might be necessary if both stresses are applied simultaneously during operalon in the field. Samples A, B and C were less robust in comparison to other samples, as they showed greatest degradalon of capacitance and DC resistance. These samples would be least tolerant towards voltage or temperature stresses over rated specificalon (narrowest windows). ASTR 2015, Sep 9 11, Cambridge, MA 16

17 Tantalum Capacitors - Background Ta capacitors are electrolylc capacitors with the liquid electrolyte replaced by solid MnO 2 or polymer. Ta capacitors have greater reliability compared to most aluminum electrolylc capacitors. They also offer greater performance stability over a wider range of temperatures and frequencies. MnO 2 Ta capacitors are unstable under surge current condilons, and can ignite. The tendency to fail catastrophically can be aggravated by thermal stresses. The catastrophic exothermic failures can be milgated by use of conduclve polymers. However, conduclve polymers degrade rapidly under elevated humidity and temperature condilons. Liquid aluminum electrolytic capacitors Tantalum Capacitors ASTR 2015, Sep 9 11, Cambridge, MA 17

18 Ta Capacitor Step Stress Tests Samples Electrolyte Type Mfr Rated Voltage (V) Capacitance (µf) Rated Temp* ( C) ESR* (mω) DCL* (µa) DF* (%) Polymer A MnO 2 A Polymer B MnO 2 B * Maximum values at 25 C; ESR = Equivalent Series Resistance; DCL = DC Leakage Current; DF = DissipaLon Factor Two sets of step stress tests were performed, both with voltage step stresses: one with temperature cycling and one with temperature- humidity stresses. 10 samples of each type were included in each test, for a total of 40 samples per step stress test The samples were uniformly distributed over the test board. ASTR 2015, Sep 9 11, Cambridge, MA 18

19 Test Board #BM*1 #AM*1 #BP*1 #AP*2 Dummy capacitors with #BP*2 embedded thermocouples #AM*2 #AM*3 #BM*3 #BP*4 #AP*4 #BM*5 #AM*5 #AP*6 A Mfr A B Mfr B M MnO2 P Polymer #AP*1 #BM*2 #AP*3 #BP*3 #BM*4 #AM*4 #BP*5 #AP*5 #BP*6 #AM*6 #BM*6 #AM*7 #BM*7 #AP*7 #BP*7 #BP*8 #AP*8 #BM*8 #AM*8 #BM*9 #AM*9 #BP*9 #AP*9 #AP*0 #BP*0 #AM*0 #BM*0 Thermocouples ASTR 2015, Sep 9 11, Cambridge, MA 19

20 Temperature ( C) Ta Capacitors Thermal Cycling with Thermal Cycling Profile 15 minutes 25 minutes 125 C Voltage Step Stresses Time (min) Voltage Stress (V) 72 hours 1 V R 1.33 Voltage Step Stresses Samples measured at room temperature once every 72 hours V R V R - 55 C 80 minutes (1 cycle) Time (hours) Voltage stresses applied simultaneously with temperature cycling Capacitance (C), dissipalon factor (DF) and DC leakage current (DCL) were measured once every 72 hours at room temperature. ASTR 2015, Sep 9 11, Cambridge, MA 20

21 Ta Capacitors Temperature Cycling DC Leakage VariaLon Leakage Threshold for Polymer Leakage Threshold for MnO 2 ASTR 2015, Sep 9 11, Cambridge, MA 21

22 RelaLve Humidity (% RH) Temperature ( C) Ta Capacitors THB with Voltage Step Temperature Humidity Profile 45 mins 90 mins 85 C 25 C 85%RH Stresses Voltage Stress (V) 72 hours 1 V R 1.33 Voltage Step Stresses Samples measured at room temperature once every 72 hours V R V R Time (hours) 72 hours hours (not to scale) Time (hours) Voltage stresses applied simultaneously with temperature humidity bias Capacitance (C), dissipalon factor (DF) and DC leakage current (DCL) were measured once every 72 hours at room temperature. ASTR 2015, Sep 9 11, Cambridge, MA 22

23 Ta Capacitors Temperature Humidity Bias DC Leakage VariaLon ASTR 2015, Sep 9 11, Cambridge, MA 23

24 Ta Capacitors Failure Mechanisms Field CrystallizaLon Under the influence of elevated temperatures and electric field, amorphous, dielectric Ta 2 O 5 is converted to a conduclve, crystalline state. Field crystallizalon could be inilated as early as the manganizalon step during capacitor fabricalon. CTE Mismatch MnO 2 is slffer than conduclve polymers. Thermal stresses induced by temperature cycling could lead to cracking of the dielectric in MnO 2 tantalum capacitors. SoRer polymer material (PEDOT) absorbs stress generated due to CTE mismatch Ag layer PEDOT Tantalum Ta 2 O 5 with crystallization Graphite Polymer DegradaLon At elevated temperatures and high humidity levels, the PEDOT electrolyte could decompose and irreversibly lose its conduclve properles. This would isolate the anode and the cathode. ASTR 2015, Sep 9 11, Cambridge, MA 24

25 Lessons from Ta Cap Step Stress Tests Overstress mechanisms none idenlfiable Wear- out mechanisms Field crystallizalon, cathode degradalon The trends seen in both tests seem to indicate that all Ta capacitors are more prone to degradalon under thermal cycling than under THB tests. Accelerated thermal cycling tests must use voltage stresses that are less than 1.33 V R ; whereas for THB tests, this limit is higher, at 2.33 V R. Under both sets of tests, the polymer Ta capacitor rated for the lower temperature performed best (with respect to DCL). The polymer Ta capacitor rated for the higher temperature performed similar to both MnO 2 Ta capacitors. The results indicate that when subjected to higher temperatures, the voltage de- ralng may have to be heavier. AddiLonally, due to the occurrence of stress induced field crystallizalon, MnO 2 Ta capacitors must be protected against voltage / current transients, especially when they are likely to see temperature gradients. ASTR 2015, Sep 9 11, Cambridge, MA 25

26 Conclusions Single stress step stress tests on EDLCs revealed differences among parts useful for part seleclon; also provides guidance for designing accelerated tests. Voltage and temperature stresses produced similar failure modes and mechanisms suggests that if these effects were combined, components would experience faster degradalon. This would require de- ralng. Dual stress step stress tests on Ta capacitors indicated that effects of temperature cycling / humidity and voltage were confounded. However when comparing results, impact of temperature cycling was found to be harsher. No clear overstress threshold could be idenlfied. However, the trends were indicalve of the robustness of various sample groups. Voltage acceleralon and de- ralng factors could be idenlfied for both environmental condilons. In the relalvely short test windows (~100 hrs for EDLCS and ~500 hrs for Ta caps) step stress tests were able to provide insights valuable for accelerated test design, rapid assessment of suppliers, and de- ralng for two passive technologies. ASTR 2015, Sep 9 11, Cambridge, MA 26