ELEC 7364 Lecture Notes Summer Si Oxidation. by STELLA W. PANG. from The University of Michigan, Ann Arbor, MI, USA

Similar documents
Section 4: Thermal Oxidation. Jaeger Chapter 3. EE143 - Ali Javey

Section 4: Thermal Oxidation. Jaeger Chapter 3

EE THERMAL OXIDATION - Chapter 6. Basic Concepts

CHAPTER 4: Oxidation. Chapter 4 1. Oxidation of silicon is an important process in VLSI. The typical roles of SiO 2 are:

MICROCHIP MANUFACTURING by S. Wolf

Lecture 4. Oxidation (applies to Si and SiC only) Reading: Chapter 4

THERMAL OXIDATION - Chapter 6 Basic Concepts

Oxide Growth. 1. Introduction

Chapter 4. UEEP2613 Microelectronic Fabrication. Oxidation

Microelettronica. Planar Technology for Silicon Integrated Circuits Fabrication. 26/02/2017 A. Neviani - Microelettronica

Doping and Oxidation

More on oxidation. Oxidation systems Measuring oxide thickness Substrate orientation Thin oxides Oxide quality Si/SiO2 interface Hafnium oxide

Silicon Oxides: SiO 2

Why silicon? Silicon oxide

HOMEWORK 4 and 5. March 15, Homework is due on Monday March 30, 2009 in Class. Answer the following questions from the Course Textbook:

Isolation Technology. Dr. Lynn Fuller

EE 143 CMOS Process Flow

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant

EE 143 FINAL EXAM NAME C. Nguyen May 10, Signature:

EECS130 Integrated Circuit Devices

Instructor: Dr. M. Razaghi. Silicon Oxidation

ME 141B: The MEMS Class Introduction to MEMS and MEMS Design. Sumita Pennathur UCSB

Czochralski Crystal Growth

X-Ray Reflectivity Study of Hafnium Silicate Thin Films Prepared by Thermal Chemical Vapor Deposition

ECSE-6300 IC Fabrication Laboratory Lecture 2 Thermal Oxidation. Introduction: Oxide

Characteristics of HfO 2 pmosfet with Ultrashallow Junction Prepared by Plasma Doping and Laser Annealing

Semiconductor Technology

Chapter 5 Thermal Processes

MOSFET. n+ poly Si. p- substrate

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant

CMOS Technology. Flow varies with process types & company. Start with substrate selection. N-Well CMOS Twin-Well CMOS STI

Kinetics of Silicon Oxidation in a Rapid Thermal Processor

MOS Gate Dielectrics. Outline

Chapter 3 Silicon Device Fabrication Technology

EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects

EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects

Review Literature for Mosfet Devices Using High- K

EE 143 MICROFABRICATION TECHNOLOGY FALL 2014 C. Nguyen PROBLEM SET #9

ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline:

Microelectronics. Integrated circuits. Introduction to the IC technology M.Rencz 11 September, Expected decrease in line width

Chapter 3 CMOS processing technology

ECSE-6300 IC Fabrication Laboratory Lecture 4: Dielectrics and Poly-Si Deposition. Lecture Outline

EE 330 Lecture 9. IC Fabrication Technology Part 2

EE 330 Lecture 8. IC Fabrication Technology Part II. - Oxidation - Epitaxy - Polysilicon - Interconnects

EE 434 Lecture 9. IC Fabrication Technology

Processing of Semiconducting Materials Prof. Pallab Banerjee Department of Material Science Indian Institute of Technology, Kharagpur

Chapter 2 Manufacturing Process

Materials Characterization

Amorphous and Polycrystalline Thin-Film Transistors

A Novel Low Temperature Self-Aligned Field Induced Drain Polycrystalline Silicon Thin Film Transistor by Using Selective Side-Etching Process

METAL OXIDE SEMICONDUCTOR (MOS) DEVICES. Term Paper Topic: Hafnium-based High-K Gate Dielectrics

Lecture 22: Integrated circuit fabrication

Chapter 2 MOS Fabrication Technology

Semiconductor Manufacturing Technology. Semiconductor Manufacturing Technology

Highly Reliable Low Temperature Ultrathin Oxides Grown Using N 2 O Plasma

University of Texas Arlington Department of Electrical Engineering. Nanotechnology Microelectromechanical Systems Ph.D. Diagnostic Examination

Changing the Dopant Concentration. Diffusion Doping Ion Implantation

CS/ECE 5710/6710. N-type Transistor. N-type from the top. Diffusion Mask. Polysilicon Mask. CMOS Processing

Hafnium silicate and nitrided hafnium silicate as gate dielectric candidates for SiGe-based CMOS technology

NON-PLANAR SILICON OXIDATION: AN EXTENSION OF THE DEAL-GROVE MODEL BRIAN D. LEMME. B.S., University of Nebraska-Lincoln, 2000 A REPORT

Ion Implantation Most modern devices doped using ion implanters Ionize gas sources (single +, 2+ or 3+ ionization) Accelerate dopant ions to very

Nucleation and growth of nanostructures and films. Seongshik (Sean) Oh

Oxidation of Silicon

EE 5344 Introduction to MEMS. CHAPTER 3 Conventional Si Processing

Silicon Manufacturing

Growth of Gate Oxides on 4H SiC by NO at Low Partial Pressures

Silicon VLSI Technology. Fundamentals, Practice and Modeling

MOS Front-End. Field effect transistor

Characterization of Interfacial Oxide Layers in Heterostructures of Hafnium Oxides Formed on NH 3 -nitrided Si(100)

Hei Wong.

Microstructure of Electronic Materials. Amorphous materials. Single-Crystal Material. Professor N Cheung, U.C. Berkeley

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009

Fabrication Technology

Oxidation SMT Yau - 1

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras

Passivation of SiO 2 /Si Interfaces Using High-Pressure-H 2 O-Vapor Heating

PY2N20 Material Properties and Phase Diagrams

the surface of a wafer, usually silicone. In this process, an oxidizing agent diffuses into the wafer

Thermal Oxidation and Growth of Insulators (Chapter 3 - Jaeger 3) Key advantage of Si: Oxidation of Si into SiO 2 (glass) Major factor in making

Effect of annealing temperature on the electrical properties of HfAlO thin films. Chun Lia, Zhiwei Heb*

Chapter 3. In this chapter, we use sol-gel method to combine three high-k precursors, i.e. HfCl 4, ZrCl 4 and SiCl 4 together to form hafnium silicate

2007 IEEE International Conference on Electron Devices and Solid-State Circuits

Etching Etching Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference

Fairchild Semiconductor Application Note June 1983 Revised March 2003

EE CMOS TECHNOLOGY- Chapter 2 in the Text

Characterization and control of defect states of polycrystalline silicon thin film transistor fabricated by laser crystallization

Ultrathin oxynitride formation by low energy ion implantation

Chapter 2 Crystal Growth and Wafer Preparation

Ajay Kumar Gautam [VLSI TECHNOLOGY] VLSI Technology for 3RD Year ECE/EEE Uttarakhand Technical University

Temperature Scales. Questions. Temperature Conversions 7/21/2010. EE580 Solar Cells Todd J. Kaiser. Thermally Activated Processes

MOS interface processing and properties utilizing Ba-interface layers

ECE520 VLSI Design. Lecture 7: CMOS Manufacturing Process. Payman Zarkesh-Ha

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras

Oxidation induced precipitation in Al implanted epitaxial silicon

Lecture #18 Fabrication OUTLINE

DEPOSITION AND CHARACTERISTICS OF TANTALUM NITRIDE FILMS BY PLASMA ASSISTED ATOMIC LAYER DEPOSITION AS CU DIFFUSION BARRIER

Supplementary Figure 1. (a-d). SEM images of h-bn film on iron foil with corresponding Raman spectra. Iron foil was reused for re-growth of h-bn

1. Introduction. What is implantation? Advantages

Chapter 5: Atom and Ion Movements in Materials

Silicon Wafers: Basic unit Silicon Wafers Basic processing unit 100, 150, 200, 300, 450 mm disk, mm thick Current industrial standard 300 mm

Transcription:

ELEC 7364 Lecture Notes Summer 2008 Si Oxidation by STELLA W. PANG from The University of Michigan, Ann Arbor, MI, USA Visiting Professor at The University of Hong Kong The University of Michigan Visiting Prof. HKU p. 1 S. W. Pang Typical CMOS Cross-Section Planar Technology with Multiple Levels The University of Michigan Visiting Prof. HKU p. 2 S. W. Pang

Films on Si Dif f us i on Im p l a n t a t i o n Depo s i t i o n Mod i f i c a t i on R e a c t i on Fil m for m ation Pl a t i ng Spin c o a t i ng Phys i c a l Ch e m i c a l O x ida t ion Nit r i d a t ion Si l i c i d a t ion Pho t ol i t h ogra phy Etchi n g The University of Michigan Visiting Prof. HKU p. 3 S. W. Pang Typical SiO 2 Thickness The University of Michigan Visiting Prof. HKU p. 4 S. W. Pang

Trends for Gate Oxide Deposited Oxide The University of Michigan Visiting Prof. HKU p. 5 S. W. Pang Si Oxidation Consumption of Si to form SiO 2 - Some of the Si near the surface is used to grow Oxide - Si-SiO 2 Interface moves down as SiO 2 is grown Thermal Oxide: Amorphous; 2.27 g/cm3; E g =9 ev (Quartz is Crystalline) The University of Michigan Visiting Prof. HKU p. 6 S. W. Pang

Oxide Structure and Interface The University of Michigan Visiting Prof. HKU p. 7 S. W. Pang Dry and Wet Oxide Oxidation Temperature 900 to 1100 C Dry Oxide: Slower Growth Rate, Better Quality Si + O 2 SiO 2 Wet Oxide: Faster Growth Rate, Lower Quality Si + 2H 2 O SiO 2 + 2H 2 The University of Michigan Visiting Prof. HKU p. 8 S. W. Pang

Oxidation Kinetics - Deal-Grove Model Oxidizing Species: O 2, O, O +, O -, O 2+, 1. Transportation from Ambient to Wafer Surface 2. Diffusion from SiO 2 Surface to Si-SiO 2 Interface 3. Reaction at Si-SiO 2 The University of Michigan Visiting Prof. HKU p. 9 S. W. Pang Oxidation Rate - Flux Balance and Interaction at Interface x o 2 + Axo = B(t + τ) x o = A 2 [(1+ t + τ A 2 / 4B )1/ 2 1] where x o =oxide thickness; t = oxidation time A = 2D( 1 + 1 k s h ) with D=Diffusion Constant; k s =Reaction Rate Constant; h=gas phase mass transfer B = 2DC * N 1 with C*=Concentration of Oxidizing Species in SiO 2 ; N 1 =Number of Oxidant Molecules. Since SiO 2 has 2.2x10 22 molecules/cm 3, for O 2 oxidation, N 1 = 2.2x10 22 molecules/cm 3 and for H 2 O oxidation, N 1 =4.4x10 22 molecules/cm 3 τ = x 2 i + Ax i B with xi =Initial Oxide Thickness The University of Michigan Visiting Prof. HKU p. 10 S. W. Pang

Oxidation Rate Constants For Short Oxidation Time Linear Region - B/A = Linear Rate Constant, depends on Reaction Rate at Interface (t +τ ) << A2 4B x o B (t +τ ) A B A = k C * s For Long Oxidation Time Parabolic Region N 1 - B=Parabolic Rate Constant, Oxidation limited by Diffusion t >>τ x o 2 Bt The University of Michigan Visiting Prof. HKU p. 11 S. W. Pang Oxidation Rate Varies with Time Both Rate Constants (B/A, B) increase with Temperature - Faster for Wet Oxidation compared to Dry Oxidation B/A (µm/hr) B (µm 2 /hr) (hr) 1000 C Dry 0.071 0.0117 0.37 1000 C Wet 1.27 0.287 0 1200 C Wet 14.4 0.72 0 The University of Michigan Visiting Prof. HKU p. 12 S. W. Pang

Oxidation Rate Constants B/A Linear Rate Constant - Reaction Rate at Interface B Parabolic Rate Constant - Diffusion The University of Michigan Visiting Prof. HKU p. 13 S. W. Pang Si Wafers in Oxidation Furnace Horizontal furnace The University of Michigan Visiting Prof. HKU p. 14 S. W. Pang

Color Chart for Si 3 N 4 Thickness The University of Michigan Visiting Prof. HKU p. 15 S. W. Pang Factors that Affect Oxidation - I Crystal Orientation - Oxidation Rate for (111) > (110) > (100) - B Little Dependence on Orientation since diffusion through oxide is not affected by Si orientation - B/A Oxidation Rate Ratio (111)/(100) ~ 1.68 Reaction Rate at Si-SiO 2 interface depends on number of Bonds available for Oxidation; (111) 1.18x10 15 cm -2 ; (100) 6.77x10 14 cm -2 - Less Crystal Orientation Dependence at Higher Temperature or Longer Time since the oxidation is limited by Diffusion in Parabolic region Dopant Effects - Dopants (B, As, P, ) Enhance Oxidation Rate - For B: B Piles up in SiO 2, weakens SiO 2 Structure and enhances Diffusion of Oxidant - For P: P Piles up in Si. Linear Rate Constant (B/A) becomes faster, not much effect on B - Heavy Doping causes E F to shift, which increases Vacancies in Si. This provides more Reaction Sites for Oxidation The University of Michigan Visiting Prof. HKU p. 16 S. W. Pang

Factors that Affect Oxidation - II H 2 O Effect (Dry vs. Wet Oxidation) - H 2 O Increases Oxidation Rate with Lower Quality Oxide and more Defects - Both B/A and B increase for Wet Oxidation - Faster Reaction Rate at SiO 2 -Si Interface - Larger Amount of Oxidant Allowed in SiO 2 : C* for H 2 O 3x10 19 cm -3 ; C* for O 2 5.2x10 16 cm -3 Halogen Effect (Cl 2 or F-based) - 1-5 % HCl Addition - Increases Oxidation Rate since HCl reacts with O 2 to from H 2 O - Converts Impurities in Si (e.g. Na, Fe, ) to form Volatile Products: Reduce Metallic Impurity Concentration and Defects in Oxide; Improve Breakdown Voltage and Lifetime The University of Michigan Visiting Prof. HKU p. 17 S. W. Pang Factors that Affect Oxidation - III Pressure Effect - High Pressure Oxidation 10-25 atm, 600-1200 C Increases Vertical Growth Rate faster than Lateral Growth Rate Oxide can be grown at Lower Temperature (Temperature reduced by 30 C with increase of 1 atm) Reduce Birdʼs Beak Encroachment - Low Pressure Oxidation 10-2 to 1 atm, 800-1000 C Reduce Rate for Thin Oxide Higher Oxide Quality to grow at Lower Pressure than Lower Temperature Oxidation rate ~ P 0.8 The University of Michigan Visiting Prof. HKU p. 18 S. W. Pang

Faster Oxidation Rate at Higher Pressure The University of Michigan Visiting Prof. HKU p. 19 S. W. Pang Oxidation to Isolate Devices ~30% Volume Expansion when Oxide is Formed Defects Around Birdʼs Beak Recess Oxide to Reduce Topography The University of Michigan Visiting Prof. HKU p. 20 S. W. Pang

Dopant Distribution at Interface Dopant Re-Distribute until Chemical Potential is the same on each side of Interface Can Affect V T due to change in Channel Doping Segregation Coefficient Dopant in Si m = Dopant in SiO 2 Examples: (Dry Oxidation, 950 C; Left: B in Si; Right: P in Si) The University of Michigan Visiting Prof. HKU p. 21 S. W. Pang Dopants In Oxide and Near Interface a) m<1, slow oxide diffusion: e.g. B b) m<1, fast oxide diffusion: e.g. B with H c) m>1, slow oxide diffusion: e.g. P d) m>1, fast oxide diffusion: e.g. Ga The University of Michigan Visiting Prof. HKU p. 22 S. W. Pang

Thin Oxide (<30 nm) Grown at Lower Temperature, Lower Pressure, Rapid Thermal Oxidation (RTO), or Plasma-Assisted Oxidation Deal-Grove Model: OK for Wet Oxidation (τ=0); Faster Initial Growth Rate, Adjusted by having τ > 0 For Thin Oxide, Oxidation Rate decreases exponentially with thickness: dx ox dt = B 2x ox + A +C 1e From D-G Excess Rate Decay Length: L 1 ~ 5 nm; L 2 ~ 7 nm Si Surface with Additional Sites for Oxidation. These sites decrease exponentially into Si with decay length of ~3 nm. These sites enhance oxidation Blocking Layer SiO causes accumulation of Oxygen that can transform rapidly to SiO 2 x ox L 1 +C 2 e x ox L 2 The University of Michigan Visiting Prof. HKU p. 23 S. W. Pang Problems - Large Leakage Current (e.g. at 1V, 1x10-12 A/cm 2 for 3.5 nm, 10 A/cm 2 for 1.5 nm) - Defects in Oxide and Interface - Control of Oxide Thickness - Dopant Penetration from Doped Poly-Si Gate Approaches Ultra Thin Gate Oxide (<5 nm) - Nitrided Films (Oxide-Nitride, Oxide-Nitride-Oxide, Oxynitride, ) - High k Dielectrics (ε SiO2 =3.9; ε Si3N4 =7.5; ε Ta2O5 =25; ε TiO2 =50; ε SrTiOx3 =150, ) Equivalent Oxide Thickness (compared to SiO 2 with ε=3.9) For x eq = 3 nm and with ε SiO2 = 3.9, ε TiO2 = 50: x TiO2 = X eq ε TiO2 ε SiO2 = 38.5nm The University of Michigan Visiting Prof. HKU p. 24 S. W. Pang

Alternative Oxides Thermal Oxidation with NO, N 2 O, O 2 re-oxidation of oxynitrides HF/H 2 O Vapor - NO Oxynitride, Self-Limiting Growth since nitrogen rich oxide is a diffusion barrier - N 2 O Reduce to NO and O which grow oxide with N Close to Si -SiO 2 Interface: NO Nitrogen in Oxide; O Remove N in Oxide near Surface - O 2 Anneal of Oxynitride Forms SiO 2 at Interface with Oxynitride near Surface Plasma Assisted Oxidation - Remote Plasma to Activate O 2, N 2 O, N 2, NH 3, - Lower Thermal Budget - Typical Condition for Oxidation/Nitridation: 300 C, 300 mtorr, <1 min; Annealing at 900 C, 30 s - N Tends to Locate Close to Si-SiO 2 Interface with ~1 monolayer N (7x10 14 cm -2 ) after 90 s plasma exposure when remote plasma at higher pressure (~300 mtorr) and N 2 O is used - N Tends to be at Top Surface when N2 is used at lower pressure (~100 mtorr) - Effective in Lowering Leakage Current and Blocking B Diffusion from Poly-Si Gate The University of Michigan Visiting Prof. HKU p. 25 S. W. Pang Oxide-Nitride Stacks Advantages of Nitride - Interface Nitridation Lower Leakage Current - Bulk Nitride Allows Increased Physical Thickness - Top-Surface Nitride Block Dopant Diffusion from Poly-Si Gate Disadvantages of Nitride - Film Stability - Positive Charges and Defects in Nitride tend to vary when Bias is Applied - Worse Stability and Reliability of Nitride as Gate Dielectric The University of Michigan Visiting Prof. HKU p. 26 S. W. Pang

High k Dielectrics Allows Thicker Film to Lower Leakage Current - Fowler-Nordheim Tunneling Current Increases Exponentially with Reduced Thickness or Reduced Barrier Height Needs Thicker Film with Larger Barrier Height Needs Thermally Stable Film (most high k films form SiO 2 on Si) Needs to develop New Etching Techniques Silicates and Oxide of Hafnium and Zirconium - HfSiON, HfO 2, HfSiO,. The University of Michigan Visiting Prof. HKU p. 27 S. W. Pang Properties of Insulators The University of Michigan Visiting Prof. HKU p. 28 S. W. Pang