Impact of Filament Evolution on Reliability Issues of Oxide Electrolyte Based Conductive Bridge Random Access Memory Hangbing Lv, Xiaoxin Xu, Hongtao Liu, Qing Luo, Qi Liu, Shibing Long, Ming Liu* Institute of Microelectronics of Chinese Academy of Sciences October 11-16, 2015, Advances in ReRAM : Materials & Interfaces, in Chania, Greece
Introduction Outline Integration of 1 kb CBRAM array Physical Mechanism and Improving Approaches on 1. Endurance 2. Retention 3. Uniformity Summary
Resistive Switching Memory Expected performances: MLC, Low Cost, High speed, 3D stackable ITRS 2013 suggests RRAM should be received additional focus to accelerate the progress of commercialization.
Classification of Resistive Switching Also named as CBRAM, ECM and PMC. Ref. R. Waser, et. al., Adv. Mater., 21, 2632, 2009
Conductive Bridge RAM CBRAM Structure Active electrode: Ag, Cu, Ni Solid-electrolyte materials Chalcogenide- or sulfide-based insulators Oxides :ZrO 2, HfO 2, Ta 2 O 5, WO 3, SiO 2,ZnO Other: a-si, and ion-conducting polymers. Counter electrode: Pt, W, TiN, Si
Switching Mechanism of CBRAM Ref. R. Waser, et. al., Adv. Mater., 21, 2632, 2009 ECM theory describes the filament growth process : (i) oxidation reaction (M M Z+ +Ze - ); (ii)m Z+ electro-migration from anode to cathode under electric field; (iii) reduction reaction (M Z+ +Ze - M).
Ease of Integration CBRAM on Cu BEOL NEC, VLSI 2010 SMIC, VLSI 2010 Copper interconnect is widely used in modern CMOS process; The Cu-based CBRAM is easy to integrate in the back end of line of CMOS; The Cu-based CBRAM is the first choice from cost point of view.
Obstacles for RRAM Application RRAM Reliability Issues: Endurance, Retention, Uniformity, Failure Mechanism, Optimization Applications Obstacles Hurdles
Introduction Outline Integration of 1 kb CBRAM array Physical Mechanism and Improving Approaches on 1. Endurance 2. Retention 3. Uniformity Summary
Integration of HfO 2 -CBRAM on CMOS Step4. Connect bitline with decoder TM TM TM for column decoder Chip image WL M1 M1 M1 M1 Step3. Dep. Oxide and Top electrode TM TM TM for column decoder WL M1 M1 M1 M1 RRAM Step2. Litho to define memory cells TM TM TM for column decoder WL M1 M1 M1 M1 CMOS Step1. After top metal CMP TM TM TM for column decoder WL M1 M1 M1 M1
1T1R Structure and 1kb Array The HfO 2 based CBRAM is integrated on the top of transistor; The copper of Top Metal line serves as BE and Pt as TE; The thickness of HfO 2 layer is about 4 nm.
Current (A) Voltage (V) Programming of 1T1R Device 600.0µ 400.0µ RESET 200.0µ 0.0-200.0µ -400.0µ -600.0µ Icc SET -3-2 -1 0 1 2 Voltage (V) 4 3 2 1 0-1 -2-3 V1 RRAM OSC V2 Rs HRS LRS Read Read Set pulse 50ns/-2.5V 0 1 2 3 Time ( s) V1 V2 Reset pulse 50ns/+3V LRS HRS Read The DC programming voltage for SET and RESET is around 1V. The programming speeds are as fast as 50 ns for both SET and RESET.
Read/Write Test of 1 kb Array Test chip Probe card test
Introduction Outline Integration of 1 kb CBRAM array Physical Mechanism and Improving Approaches on 1. Endurance 2. Retention 3. Uniformity Summary
Resistance ( ) Characteristic of Endurance Failure Resistance ( ) 10 10 10 8 LRS 10 6 10 4 10 2 HRS Endurance failure: R HRS /R LRS <5 SET: 3 V, 50 ns RESET: 2.5 V, 50ns LRS struck 10 12 SET: WL=2.5 V, SL=0~2 V RESET: WL=3.5 V, BL=0~2 V 10 10 10 8 10 6 10 4 HRS Failure trend 10 0 10 2 10 4 10 6 10 8 Number of Cycles 0 2500 5000 Number of Cycles The HRS is degraded with switching cycle both in pulse and DC programming; The LRS stuck is the major endurance failure in the case of CBRAM. H. Lv, et al., Sci. Rep. 5:7764, 2015.
Resistance (k ) Normalized LRS LRS Dependence with Switching Cycles 1.2 1.0 0.8 0.6 0.4 LRS Evolution trend 0 2500 5000 Number of Cycles 1.20 Experiment data 10 7 Fitting result 1.15 10 6 HRS 2 1.10 10 5 1.05 HRS α =0.00252/ 1 K 10 4 1.00 10 3 180 150200 200 220 240 250260 300 280 Temperature (K) (K) ( )108 HRS Resistance HRS 3 Slight decrease in LRS from 1.2 kω at initial cycles to 0.6 kω can be observed; The LRS shows positive temperature coefficient, indicting a metallic property. H. Lv, et al., Sci. Rep. 5:7764, 2015.
Current (ma) Cycled Dependent I-V Characteristics 10 0 10-2 10-4 10-6 10-8 10-10 HRS 2 HRS 1 HRS 3 1st cycle 500th 2500th 5000th -2-1 0 1 2 Voltage (V) 10 7 10 6 10 5 10 4 10 3 150 200 250 300 Temperature (K) HRS Resistance ( )108 HRS 1 HRS 2 HRS 3 The SET voltage is deceased with cycling while the RESET voltage is increased; The increase in V RESET suggested that the retraction of CF became more difficult with cycling; The temperature independence of various HRS suggests the conduction of HRS is tunneling. H. Lv, et al., Sci. Rep. 5:7764, 2015.
Switching Mechanism of HfO 2 -CBRAM CF Q. Liu, et al., Adv. Mater., 24, 1844 (2012) For SET process, metallic filament is formed with the help of electric field; The RESET process is a combination effect of electric field and joule heating. Both the lateral diffusion caused by Joule heating and vertical drift resulted from the electric field can contribute the tunnel gap formation during RESET process.
Modeling of HRS with Cycling The HRS can be modeled by a direct tunneling equation in low voltage regime, since the read voltage is as low as 0.1 V; With increasing cycles, the gap length is reduced.
Failure Analysis by HRTEM The filament sizes of the two samples are nearly the same; The most remarkable difference is the concentration of copper in the filament; The copper accumulation inside filament is the root of endurance failure.
High Temperature Endurance The DC endurance at 100 and 150 are reduced to about 500 cycles and 100 cycles. The copper accumulation is accelerated by high temperature programming. H. Lv, et al., Sci. Rep. 5:7764, 2015.
Resistance ( ) Resistance ( ) Tailor pulse condition for better endurance 10 12 10 10 10 12 10 10 10 8 10 6 10 4 10 2 SET: 3V/50ns RESET conditions: 2.5V/50ns 2.5V/500ns 2.5V/5 s 10 0 10 2 10 4 10 6 10 8 10 10 Number of Cycles 10 0 10 2 10 4 10 6 10 8 Number of Cycles Copper accumulation is related to the flux difference of copper in or out of the electrolyte during the SET and RESET; The Q set /Q reset is closely related with the pulse duration of SET and RESET (t set /t reset ). Longer RESET pulse results in better endurance, while longer SET pulse degrades the endurance. 10 8 10 6 10 4 10 2 RESET: 2.5V/5 s SET condition: 3V/50ns 3V/500ns 3V/5 s H. Lv, et al., Sci. Rep. 5:7764, 2015.
Introduction Outline Integration of 1 kb CBRAM array Physical Mechanism and Improving Approaches on 1. Endurance 2. Retention 3. Uniformity Summary
Dependence of HRS retention with cycling HRS retention is degraded with cycling. The failure mechanism of HRS retention is related with the Cu diffusion into the tunnel gap. The gap length is reduced with cycling, resulting in the worse of HRS retention with cycling. H. Lv, et al., Sci. Rep. 5:7764, 2015.
Dependence of LRS retention with cycling LRS retention is improved with cycling. The failure mechanism of LRS retention is related with the Cu out-diffusion from the filament region. The Cu accumulation inside the filament with cycling enhances the LRS retention. H. Lv, et al., Sci. Rep. 5:7764, 2015.
LRS retention improve by forming single CF For the same LRS value, the single CF case and multi-cf case have the same effective area of CF. The surface area of single-cf is smaller than that of multi- CFs, resulting in less diffusion probability and better LRS retention. X. Xu, et al., IEEE EDL, 36, 129 (2015)
Forming Single CF by CPM CPM VPM Current programming tends to form single CF, while voltage programing tends to form multi-cf. W. Lian, et al., IEEE EDL, 32, 1053 (2011)
LRS retention improve by forming single CF Better LRS retention was achieved by current programming, as shown in the baking results at various temperature. X. Xu, et al., IEEE EDL, 36, 129 (2015)
HRS retention improve by CF fully rupture HRS failure is due to the ions refilled the tunnel gap; Higher HRS corresponds to wider gap length better HRS retention can be expected; Current program can get higher HRS because of eliminating the partial RESET states; Current program has better HRS retention than voltage W. Lian, et al., IEEE EDL, 32, 1053 (2011) program. X. Xu, et al., IEEE EDL, 36, 129 (2015)
Introduction Outline Integration of 1 kb CBRAM array Physical Mechanism and Improving Approaches on 1. Endurance 2. Retention 3. Uniformity Summary
Origin of the uniformity issues 1. Randomness of CF growth path 2. Randomness of CF rupture degree 1st cycle 2nd cycle Cycle 1 Cycle 2 TE (Pt) Tunnel gap d n BE (Cu) Voltage distribution Resistance distribution Uniformity issue of RRAM: Dispersion of voltage; Dispersion of resistance; Decreased array yield Lowered programming successful ratio
Improving uniformity: NC induced CF growth Lightning Rod Effect Nanocrystal island was used to confine the location of filament, owing to the enhanced electrical field by lighting rod effect. Q. Liu, et al., ACS Nano, 31, 6162 (2010)
Improving uniformity: Bi-layer structure The location of randomly formed filament can be confined by a pin layer in bi-layer structure. The dispersion of SET voltage is greatly minimized. Single RS layer Bi-layer structure RS layer Pin layer H. Lv, et al., IEEE EDL 31, 978 (2010)
Improving uniformity: Doping technology By doping, traps with different types, density and profiles were intentionally introduced into the dielectric film. Lower forming voltage and better uniformity were achieved by doping Doping Ti Q. Liu, et al., IEEE EDL, 30, 1335 (2009) W. Guan, et al., APL, 91, 062111 (2007) and IEEE EDL, 29, 434 (2008); Q. Liu, et al., IEEE EDL, 30, 1335 (2009)
Resistance ( ) Current (IDS/mA) Improving uniformity: Gate induced programming (a) (a) V S =0V V S =0V (b) (b) V S =0V V S =0V V G Fixed V G Fixed V G Ramped V G Ramped V D Ramped V D Ramped V G Ramp scheme Conventional scheme V D Fixed V D Fixed Gradual RESET Abrupt RESET 10 3 0.0 0.5 1.0 1.5 2.0 2.5 3.0 10 1 3.5 Gate Voltage (V) Abrupt RESET is observed for the V G ramp scheme. The intermediate state can be effective eliminated. IDS (ma) 10 0 10-1 10-2 10-3 10-4 10-5 1.5 1.0 0.5 (a) SET: -2-1 0 1 Voltage (V) (a) SET RESET V G =2.5 V V S =0~2 V A RESET: B C V G =3.3 V V D =0~1.5 V 10 9 10 7 10 5 H. Liu, et al., IEEE EDL 35, 1224 (2014)
Power (IxV) (mw) Resistance ( ) Cumulative Probability Power (IxV) (mw) Resistance ( ) Improving uniformity: Gate induced programming 1.0 0.8 0.6 0.4 0.2 0.0 LRS V G RAMP V D RAMP HRS 10 1 10 3 10 5 10 7 10 9 10 11 Resistance ( ) Improved distribution of HRS is obtained by Vg ramp scheme. The decreased power generation slows the filament rupture process in VD RAMP. The V G ramp scheme has a positive feedback of power generation, accelerating the rupture process of CF 2 1 0 2 1 0-1 (a) 10 1 0.0 0.5 1.0 1.5 (b) VRRAM (V) Accelerating Decreasing 10 5 10 4 10 3 10 2 10 0 0.0 0.5 1.0 1.5 2.0 VRRAM (V) 10 8 10 6 10 4 10 2 H. Liu, et al., IEEE EDL 35, 1224 (2014)
Introduction Outline Integration of 1 kb CBRAM array Physical Mechanism and Improving Approaches on 1. Endurance 2. Retention 3. Uniformity 4. Summary
Summary Resistive Switching memory is a promising candidate for next generation nonvolatile memory. For mass production, reliability issues should be rigorously solved. In order to have a better overallperformance, it is important to carefully tune the material, interface, program scheme, etc.
Group members: Acknowledgement Group leader: Prof. Ming Liu Researcher : Prof. Shibing Long, Dr. Qi Liu, Dr. Hangbing Lv, Student: Ming Wang, Xiaoxin Xu, Hongtao Liu, Guoming Wang, Yang Li, Haitao Sun, Meiyu Zhang Funding: Ministry of Science and Technology, China under grant nos. 2010CB934200, 2011CBA00602, 2011AA010401 and 2011AA010402. National Natural Science Foundation of China under grant nos. 61221004, 61106119, 61106082, 61334007, 61322408 and 61274091.
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