Wafer-to-Wafer Bonding and Packaging Dr. Thara Srinivasan Lecture 25 Picture credit: Radant MEMS Reading Lecture Outline Senturia, S., Chapter 17, Packaging. Schmidt, M. A. Wafer-to-Wafer Bonding for Microstructure Formation, pp. 1575-1585. Tummala, R.R. Fundamentals of Microsystems Packaging, pp. 556-66. Today s Lecture MEMS Packaging: Why a Whole Lecture? Wafer Bonding Methods for MEMS Bonding Tools and Characterization Packaging: Die-Level, Wafer-Level 2
MEMS and the Package Packaging electronics Provide electrical interconnects, protect electronics Dice up wafer, assemble into ceramic/plastic package Single package, many chips Packaging MEMS Provide electrical (and other, i.e., fluidic, optical) interconnects, protect micromechanical elements, interface with outside environment Dicing cannot be done after release unless precautions taken Environment inside package important Package should not mechanically stress MEMS Single chip, many packages Packaging, test and calibration important to MEMS design 3 Die Level Current MEMS Packages Wafer Level Cronos Relay Die level release and ceramic package Motorola Accelerometer Bosch Gyroscope Wafer bonded package with glass frit seal and lateral feedthroughs (sealed MEMS is then placed into ceramic package) CMOS region MEMS region Wafer bonded package with glass frit seal and lateral feedthroughs BSAC/Sandia Partial Hexsil cap assembled onto Sandia imems chip using wafer-to-wafer transfer4
Lecture Outline MEMS Packaging Wafer Bonding Methods for MEMS Bonding tools and characterization Packaging: die-level, wafer-level 5 Wafer Bonding in MEMS Wafer-level packaging MEMS device construction Sealed structures, i.e., pressure sensors and fluidic channels Multiwafer structures, i.e., µtas, microturbines, optical devices, inkjet print heads Motorola pressure sensor Jensen group, MIT MIT microturbine 6
Sealed Structures Microfluidic channel structures Pressure sensors and valves Caliper Technologies Redwood Microsystems MEMS valve 7 Wafer Bonding Methods Surface bonding Metallic layer bonding Insulating layer bonding 8
Fusion Bonding Two ultra-smooth (<10 Å roughness) wafers are bonded without adhesives or applied external forces Technique Surface preparation: O 2 plasma, hydration, or HF dip Room temperature contacting leads to hydrogen bonding, van der Waals forces Annealing at 600-1200 C brings bond to full strength Low temperature fusion bonding also possible using Ziptronix surface preparation Mechanism Hydrophilic ~ Si O Si Hydrophobic ~ Si Si Ziptronix 9 Anodic Bonding Bonds an electron conducting material, Si, to an ion conducting material, e.g. sodium glass (Pyrex) Technique Voltage applied ~ 200-1500 V Elevated temperature ~ 180-500 C Positive ions in glass migrate, creating depletion layer near Si surface; voltage drop creates large E-field pulling surfaces into contact Pro and con CTE mismatch concerns + Hermetic sealing 10
Anodic Bonding 1. after 5 sec 2. after 20 sec Only center bond pin active All bond pins active 3. after 2,5 min 4. after 8 min ø100 mm, Pyrex - 500 µm, 430 C, 800 V, N 2-1000 mbar Bond front spreads Bond 98% completed 11 Metal Layer Bonding Pattern seal rings and bond pads photolithographically Eutectic bonding Uses eutectic point in metal-si phase diagrams to form silicides Au and Si have eutectic point at 363 C + Low-T process, can bond slightly rough surfaces Au contamination of CMOS Solder bonding PbSn (183 C), AuSn (280 C) + Lower-T process, can bond really rough surfaces Thermocompression Commonly done with electroplated Au, other soft metals T ~ room temperature to 300 C P ~ 1-2 MPa + Lowest-T process, can bond rough surfaces, topography 12
Thermocompression Bonding Transfer of hexsil actuator onto CMOS wafer Angad Singh, et al., Transducers 97 13 Bonding with Insulating Layers Adhesives, i.e. epoxies, BCB Screen Glass Paste Cap Wafer Glass frit bonding Stencil or screen printed glass paste 350-450 C: glass flows Hermetic Wide sealing layer required (500 µm) Cap Wafer Device Wafer P: 1000 mbar Glass Frit Frame Device T: 425 C 14
Glass Frit Bonding Packaged switch by Radant MEMS Suss MicroTEC 15 Wafer Bonding Methods Techniques Advantages Drawbacks Surface bonding Hermetic Flat surface required Anodic strong bond high-voltage Fusion (Direct) strong bond high temp Surface-activated varies varies Metallic interlayer Hermetic Non-flat surface ok Specific metals required Eutectic strong bond flat surface req d Thermocompression non-flat surface ok high force Solder self-aligning solder flow possible Insulating interlayer Non-flat surface ok Varies Glass frit Adhesive hermetic common in MEMS versatile large area medium-hi temp non-hermetic 16
Lecture Outline MEMS Packaging Wafer Bonding Methods for MEMS Bonding Tools and Characterization Packaging: Die-Level, Wafer-Level 17 Bonding Tool Suss SB 6e Bonder 18
Wafer Bonding Considerations Topography: planar or textured? Material: insulating or conducting? Hermeticity required? Maximum temperature or force allowed? Biocompatibility? 19 Bond Characterization Nondestructive Visual inspection Imaging ~ IR transmission, ultrasonic, X-ray topography X-ray Destructive Cross-sectional analysis using SEM or TEM Defect etching a cross-sectioned sample Bond strength measurement techniques Pressure burst test Tensile-shear test Knife-edge test Acoustic IR 20
Lecture Outline MEMS Packaging Wafer Bonding Methods for MEMS Bonding Tools and Characterization Packaging: Die-Level, Wafer-Level 21 Issues Specific to MEMS Packaging MEMS are micromechanical structures Damaged during dicing step? Package environment important: hermeticity required? Considerations Bonding method Stack thickness Mechanical stress of package Coefficient of thermal expansion mismatch Thermal management Electrical feedthrough method 22
Packaging Approaches Die-level vs. wafer level 23 Die Level Packaging Conventionally, MEMS have been diced, then released to protect them from the sawing process. But die-level release is expensive and slow Die are then packaged in ceramic cavity packages. Ceramic packages are large and expensive Cronos Relay Fabricate Singulate Release Package Ceramic Cavity Package 24
Dicing After Release? Analog Devices upside-down-saw process Texas Instruments fabrication and packaging for DMD chip 25 Wafer Level Packaging Alternately, do the MEMS release at the wafer level Release seal dice Wafer level packaging must follow the wafer level release, to avoid damaging the MEMS. Much smaller packages are possible. Fabricate Release Wafer bond Singulate Chip Scale Package (CSP) 26
Wafer-level packaged MEMS Clarisay surface acoustic wave filters Packaged gyroscope by IMEC, Bosch and STS Packaged switch by Radant MEMS 27 Wafer-Level MEMS Package Types Bulk wafer caps Current Industry standard Micro-assembled hexsil caps Berkeley In situ caps Toyota Berkeley 28
Bulk Wafer Caps Industry standard, examples: Motorola accelerometers Bosch gyroscopes Clarisay SAW filter Radant MEMS switch Pros and cons + Robust + Hermetic + Wafer-level Large on-chip area required for seal ring 29 Micro-Assembled Caps Fabricate microcaps on donor wafer Transfer microcaps to target wafer by wafer bonding and separation Thin seal ring requires little real estate (~1% of bulk cap) Potentially much less expensive than wafer-bonded caps M. Cohn PhD, J. Heck PhD, Howe group Align Bond Separate 30
Micro-Assembled Cap Fabrication The hexsil process makes honeycomb type, high-aspectratio structures from thin film deposition Recess etch Deep trench etch Electroplate gold bumps & seal ring Deposit & pattern sacrificial, structural layers Release etch Thermocompression-bond to target wafer 31 Microcap Assembly CMOS region MEMS region Several hexsil caps assembled onto bare gold die Partial Hexsil cap assembled onto Sandia imems chip Heck PhD, Howe group, Sandia Labs 32
In Situ Sealing Seal MEMS devices on wafer scale postrelease Microshells fabricated over MEMS Release etch frees MEMS through access holes Access holes are sealed using film deposition, possibly at low pressure + Simplifies packaging process Adds development to fabrication process T. Corman et al. shell MEMS Lebouitz et al., BSAC Toyota 33 Hermeticity Hermetic package has internal cavity with acceptable level of gas-tightness Metals, glasses, semiconductors are considered hermetic materials; plastic seals are not Getters (certain metal alloys) can absorb and react with gases in package to keep pressure low T. Corman et al 34
Wafer Level Package Interconnects Through-silicon vias + Small area required + True chip scale package (BGA-ready) Expensive processing cap wafer 35 Wafer Level Package Interconnects Lateral surface feedthroughs + Simplest fabrication Larger on-chip area required Not a true chip scale package (substrate required) Wire bonding required wafer T. Corman 36
Wafer Level Package Interconnects Hybrid approach, e.g., Shellcase T contact, ChipScale Feedthroughs on MEMS wafer are contacted by sawing through wafer backside + Small area required + True chip scale package (BGAready) Shellcase proprietary Top cover wafer MEMS wafer Contact pad on the die External lead ChipScale Top cover wafer MEMS wafer Bottom cover wafer Shellcase 37 Packaging Testing and Failure Failure mechanisms Delamination, e.g. due to temperature cycling Environmental exposure and loss of hermeticity Testing hermeticity Helium leak detection Radioisotope method IR method 38
Packaging for Fluidics In addition to electronic interfaces Fluidic interface for sample introduction Optical interface for detection Implantable devices Biocompatibility Don t shock the patient Cepheid 39