Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes. Jason Chou and Sze Pei Lim Indium Corporation
|
|
- Elfrieda Mosley
- 6 years ago
- Views:
Transcription
1 Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes Jason Chou and Sze Pei Lim Indium Corporation
2 Agenda Company introduction Semiconductor assembly roadmap challenges Fine pitch, low stand-off Warpage Smaller Cu-pillar solder cap, fewer flux amount More pre-process and thermal oxidation on bond pad surface Five case studies in using surface analysis tools to drive understanding of semiconductor assembly materials
3 Company Introduction Indium Corporation is a premier materials supplier to global industries including: Electronics assembly Semiconductor Solar energy Thin-film Thermal management
4 Indium Corporation Global Manufacturing and Sales Offices
5 From Mobile to Wearable to IoT Technology driving force: lighter, thinner, smaller
6 Solder Joint Evolution Solder Joint by Package Type Flip-Chip Solder Joint High-Pb Solder Eutectic Solder (PbSn63) SnAg2 Sn(?)
7 Assembly and Process Challenges for FC-BGA Thinner substrates and thinned die increase warpage Processes oxidize / contaminate the ball-attach pad surface Bottom Cu/OSP pads badly oxidized
8 Process and Material Challenges in Flip-Chip Solder Microbump Thickness & alloy Oxidation Contamination IMC thickness No-clean Flux Residue level (ULR) Wetting power Compatibility with MUF/CUF Rheology Substrate or Leadframe Leadframe / Substrate Surface treatment Oxidation Contamination Warpage
9 Advanced Analytical Techniques for Semiconductor Assembly Advanced analytical and preparation techniques now necessary to understand failure modes Auger spectroscopy SIMS (secondary ion mass spectrometry) FIB (focused ion beam) Drive deep understanding of mechanisms
10 Surface Analysis by SIMS / Auger Auger Electron: 0.4 ~ 5nm Secondary Electron (SIMS): <50 nm SEM EDX: 1000 ~ 3000 nm SIMS Auger SEM EDX
11 Case Study 1: Solder Cap Contamination SEM and EDX analysis The SEM did not find foreign or abnormal material EDX analysis showed high C and O levels Good solder joint Bad solder joint
12 Case Study 1: Solder Cap Contamination Solder cap shows abnormal one has dark surface with impurity SIMS data shows abnormal one has high C, O content Abnormal Normal
13 Case Study 2: Wafer Bumping Cleaning Optimization Auger test method is very sensitive to carbon, oxygen (oxide) Good tool for process optimization STD STD (exclude S, Ca) 40S50DI 40S25DI 60S50DI 60S25DI 70S50DI 70S25DI Name Start KE Peak KE End KE PP At. % PP At. % PP At. % PP At. % PP At. % PP At. % PP At. % PP At. % C KL Sn MN O KL S LM Ca LM Ag MN % Carbon Condition
14 Case Study 3: Leadframe Surface Treatment Surface roughness (adhesion enhancement) treatment is used to increase MUF/CUF adhesion Different surface treatment will induce different wetting performance Scanned Area 3.0µ m
15 µ m Scanned Area Case Study 3: Leadframe Surfaces with SIMS Analysis SIMS analysis quantifies oxidation level and oxide depth Important for process tuning 3.50E E E E E E E+08 C 2.00E+08 C 1.50E E+08 O Cu 1.50E E+08 O Cu 5.00E E E E E E E E+08 C O Cu 5.00E+07
16 BGA Process and Thermal Treatment 2~4 times Substrate SMT Reflow Die Bond Wire bond D/B Cure Saw Singulation BM Pre-clean PMC Molding Pre-Baking Many thermal process before BM will induce pad surface oxidation, which will induce yield loss (missing ball ) and low productivity
17 Case Study 4: BM Pad Surface with SIMS Analysis 2~4 times Substrate SMT Reflow Die Bond Wire bond D/B Cure Saw Singulation BM Pre-clean PMC Molding Pre-Baking 1.40E E+08 Fresh substrate 3.50E E+06 Post Molding cure 1.00E E E E E+07 Cu 12C 16O 32S 58Ni 138Ba 197Au 2.50E E E E E+05 O, C 12C 16O 32S 58Ni 138Ba 9.00E E E E E E E E E+07 Flux clean x1 12C 16O 32S 58Ni 138Ba 197Au 9.00E E E E E E E E E+07 Flux clean x2 12C 16O 32S 58Ni 138Ba 197Au
18 Supplier-B Supplier-A Case Study 5: FIB Analysis on OSP Substrate Deposit Pt for FIB analysis OSP Cu Fresh Cu OSP Substrate
19 Case Study 5: FIB and SIMS post-flux clean Indium WS-575-C shows better cleaning efficiency on OSP substrate base on FIB and SIMS analysis result WS-575-C 4.00E E F 4.00E E F 3.00E E E E E+07 12C 16O 32S 58Ni 2.50E E E+07 12C 16O 32S 58Ni 1.00E+07 63Cu 1.00E+07 63Cu 5.00E E E E+07 K-5-NC 5.00E E+07 K-5-F 4.00E E E+07 12C 3.50E+07 12C 3.00E+07 16O 3.00E+07 16O 2.50E+07 32S 2.50E+07 32S 2.00E+07 58Ni 2.00E+07 58Ni 1.50E+07 63Cu 1.50E+07 63Cu 1.00E Au 1.00E Au 5.00E E+06 Competitor OSP residue
20 Summary Advanced analytical techniques create: Knowledge of the mechanisms of flux activity and usage Improved materials and processes Higher yield, improved reliability, and speed time to market
21 Thank you!
Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip
Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip SzePei Lim (Presenter), Jason Chou, Maria Durham, and Dr. Andy Mackie Indium Corporation 1 Outline of Presentation Roadmaps and challenges
More informationWS-575-C-RT. Halogen-Free Ball-Attach Flux PRODUCT DATA SHEET
-RT Halogen-Free Ball-Attach Introduction Indium Corporation s Ball-Attach -RT allows customers to use a completely halogen-free (NIA = no intentionally added halogens) single-step ball-attach process
More informationTHE EFFECTS OF INTERNAL STRESSRS IN BGA Ni LAYER ON THE STRENGTH OF Sn/Ag/Cu SOLDER JOINT
THE EFFECTS OF INTERNAL STRESSRS IN BGA Ni LAYER ON THE STRENGTH OF Sn/Ag/Cu SOLDER JOINT C.H. Chien 1, * C.J. Tseng 1,2 T.P. Chen 1,3 1 Department of Mechanical and Electro-Mechanical Engineering, National
More informationFuture Electronic Devices Technology in Cosmic Space and Lead-free Solder Joint Reliability
The 22nd Microelectronics Work Future Electronic Devices Technology in Cosmic Space and Lead-free Solder Joint Reliability Key Points (1) High Speed Solder Ball Shear Test (2) Relationship between Surface
More informationAn Innovative High Throughput Thermal Compression Bonding Process
An Innovative High Throughput Thermal Compression Bonding Process Li Ming 2 September 2015 Outline Introduction Throughput improved TCB Process Liquid Phase Contact (LPC) bonding Flux-LPC-TCB under inert
More informationComparative Study of NiNiP Leadframes from Different Processes
Comparative Study of NiNiP Leadframes from Different Processes Wu-Hu Li *1, Jeffrey Khai Huat Low 1, Harry Sax 2, Raymond Solis Cabral 1, Esperidion De Castro Salazar 1, Pauline Min Wee Low 1 1 Infineon
More informationChallenges in Material Applications for SiP
Challenges in Material Applications for SiP Sze PeiLim Regional Product Manager for Semiconductor Products Indium Corporation Indium Corporation Materials Supplier: SMT solder pastes and fluxes Power semiconductor
More informationS/C Packaging Assembly Challenges Using Organic Substrate Technology
S/C Packaging Assembly Challenges Using Organic Substrate Technology Presented by Bernd Appelt ASE Group Nov. 17, 2009 Overview The Packaging Challenge Chip Substrate Interactions Stiffeners for FC-BGA
More informationWF6317. A superactive low-volatile/high heat-resistant water-soluble flux for ball soldering
WF637 A superactive low-volatile/high heat-resistant water-soluble flux for ball soldering Low viscosity and high tacking power stabilize ball holding force and ensures excellent solder wettability Easy
More information3D-WLCSP Package Technology: Processing and Reliability Characterization
3D-WLCSP Package Technology: Processing and Reliability Characterization, Paul N. Houston, Brian Lewis, Fei Xie, Ph.D., Zhaozhi Li, Ph.D.* ENGENT Inc. * Auburn University ENGENT, Inc. 2012 1 Outline Packaging
More informationFuture Electronic Devices Technology in Cosmic Space and Electroless Ni/Pd/Au Plating for High Density Semiconductor Package Substrate
JAXA 25 rd Microelectronics Workshop Future Electronic Devices Technology in Cosmic Space and Electroless Ni/Pd/Au Plating for High Density Semiconductor Package Substrate November 2, 2012 Yoshinori Ejiri
More information1 Thin-film applications to microelectronic technology
1 Thin-film applications to microelectronic technology 1.1 Introduction Layered thin-film structures are used in microelectronic, opto-electronic, flat panel display, and electronic packaging technologies.
More informationFraunhofer IZM Bump Bonding and Electronic Packaging
Fraunhofer IZM Bump Bonding and Electronic Packaging Fraunhofer Institute for Reliability and Microintegration (IZM) Gustav-Meyer-Allee 25 13355 Berlin Germany Dipl.-Ing. Thomas Fritzsch Contact: thomas.fritzsch@izm.fraunhofer.de
More informationChips Face-up Panelization Approach For Fan-out Packaging
Chips Face-up Panelization Approach For Fan-out Packaging Oct. 15, 2015 B. Rogers, D. Sanchez, C. Bishop, C. Sandstrom, C. Scanlan, TOlson T. REV A Background on FOWLP Fan-Out Wafer Level Packaging o Chips
More informationAdvancements In Packaging Technology Driven By Global Market Return. M. G. Todd
Advancements In Packaging Technology Driven By Global Market Return M. G. Todd Electronic Materials, Henkel Corporation, Irvine, California 92618, USA Recently, the focus of attention in the IC packaging
More informationMEPTEC Semiconductor Packaging Technology Symposium
MEPTEC Semiconductor Packaging Technology Symposium Advanced Packaging s Interconnect Technology Process Shift and Direction October 23, 2014 Jay Hayes- Director of Business Development -Bumping and Flip
More informationFlip Chip Bump Electromigration Reliability: A comparison of Cu Pillar, High Pb, SnAg, and SnPb Bump Structures
Flip Chip Bump Electromigration Reliability: A comparison of Cu Pillar,,, and SnPb Bump Structures Ahmer Syed, Karthikeyan Dhandapani, Lou Nicholls, Robert Moody, CJ Berry, and Robert Darveaux Amkor Technology
More informationTIN-BASED LEAD-FREE SOLDER BUMPS FOR FLIP-CHIP APPLICATION. S. Yaakup, H. S. Zakaria, M. A. Hashim and A. Isnin
TIN-BASED LEAD-FREE SOLDER BUMPS FOR FLIP-CHIP APPLICATION S. Yaakup, H. S. Zakaria, M. A. Hashim and A. Isnin Advanced Materials Research Centre (AMREC), SIRIM Berhad, Lot 34, Jalan Hi-Tech 2/3, Kulim
More information3D-IC Integration using D2C or D2W Alignment Schemes together with Local Oxide Reduction
3D-IC Integration using D2C or D2W Alignment Schemes together with Local Oxide Reduction Gilbert Lecarpentier*, Jean-Stéphane Mottet* SET S.A.S. (Smart Equipment Technology), 131 Impasse Barteudet, 74490
More informationVarious Techniques for Reliability Estimation and Failure Analysis of Electronic Products and Components
JFE No. 13 2006 8 p. 97 102 Various Techniques for Reliability Estimation and Failure Analysis of Electronic Products and Components BAN Mitsuyuki SHIMAUCHI Yutaka JFE JFE JFE X IC Pb Abstract: JFE Techno-Research
More informationShear Strength in Solder Bump Joints for High Reliability Photodiode Packages
Materials Transactions, Vol. 44, No. 10 (2003) pp. 2163 to 2168 #2003 The Japan Institute of Metals Shear Strength in Solder Bump Joints for High Reliability Photodiode Packages Chong-Hee Yu 1, Kyung-Seob
More informationLead-Free Solder Bump Technologies for Flip-Chip Packaging Applications
Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications Zaheed S. Karim 1 and Jim Martin 2 1 Advanced Interconnect Technology Ltd. 1901 Sunley Centre, 9 Wing Yin Street, Tsuen Wan, Hong
More informationEffect of Process Variations on Solder Joint Reliability for Nickel-based Surface Finishes
Effect of Process Variations on Solder Joint Reliability for Nickel-based Surface Finishes Hugh Roberts Atotech USA Inc., Rock Hill, SC, USA Sven Lamprecht, Gustavo Ramos and Christian Sebald Atotech Deutschland
More informationFailure Modes in Wire bonded and Flip Chip Packages
Failure Modes in Wire bonded and Flip Chip Packages Mumtaz Y. Bora Peregrine Semiconductor San Diego, Ca. 92121 mbora@psemi.com Abstract The growth of portable and wireless products is driving the miniaturization
More informationCost Analysis of Flip Chip Assembly Processes: Mass Reflow with Capillary Underfill and Thermocompression Bonding with Nonconductive Paste
Cost Analysis of Flip Chip Assembly Processes: Mass Reflow with Capillary Underfill and Thermocompression Bonding with Nonconductive Paste Amy Palesko Lujan SavanSys Solutions LLC 10409 Peonia Court Austin,
More informationChallenges for Embedded Device Technologies for Package Level Integration
Challenges for Embedded Device Technologies for Package Level Integration Kevin Cannon, Steve Riches Tribus-D Ltd Guangbin Dou, Andrew Holmes Imperial College London Embedded Die Technology IMAPS-UK/NMI
More informationBridging Supply Chain Gap for Exempt High-Reliability OEM s
Bridging Supply Chain Gap for Exempt High-Reliability OEM s Hal Rotchadl hrotchadl@premiers2.com www.premiers2.com Premier Semiconductor Services Tempe, AZ RoHS exempt high reliability OEMs breathed a
More informationWelcome to SMTA Brazil Chapter Brook Sandy-Smith Dr. Ron Lasky Tim Jensen
Welcome to SMTA Brazil Chapter 2013 Presented by Authors Ivan Castellanos Edward Briggs Brook Sandy-Smith Dr. Ron Lasky Tim Jensen Advantages / Concerns HP testing Mechanical properties New work Area ratio
More informationReliability of Lead-Free Solder Connections for Area-Array Packages
Presented at IPC SMEMA Council APEX SM 2001 For additional information, please email marketing@amkor.com Reliability of Lead-Free Solder Connections for Area-Array Packages Ahmer Syed Amkor Technology,
More informationHot Chips: Stacking Tutorial
Hot Chips: Stacking Tutorial Choon Lee Technology HQ, Amkor Enabling a Microelectronic World Mobile Phone Technology Change Feature Phone Smartphone Smartphones as a Percentage of All Phones Source : The
More informationChallenges of Fan-Out WLP and Solution Alternatives John Almiranez
Challenges of Fan-Out WLP and Solution Alternatives John Almiranez Advanced Packaging Business Development Asia Introduction to Fan-Out WLP Introduction World of mobile gadgetry continues to rapidly evolve
More informationChapter 4 Fabrication Process of Silicon Carrier and. Gold-Gold Thermocompression Bonding
Chapter 4 Fabrication Process of Silicon Carrier and Gold-Gold Thermocompression Bonding 4.1 Introduction As mentioned in chapter 2, the MEMs carrier is designed to integrate the micro-machined inductor
More informationMaterial based challenge and study of 2.1, 2.5 and 3D integration
1 Material based challenge and study of 2.1, 2.5 and 3D integration Toshihisa Nonaka Packaging Solution Center R&D Headquarters Hitachi Chemical Co., Ltd., Sep. 8, 2016 Hitachi Chemical Co., Ltd. 2010.
More informationTechnology Drivers for Plasma Prior to Wire Bonding
Technology Drivers for Plasma Prior to Wire Bonding James D. Getty Nordson MARCH Concord, CA, USA info@nordsonmarch.com Technology Drivers for Plasma Prior to Wire Bonding Page 1 ABSTRACT Advanced packaging
More informationA STUDY OF THE ENEPIG IMC FOR EUTECTIC AND LF SOLDERS
A STUDY OF THE ENEPIG IMC FOR EUTECTIC AND LF SOLDERS G.Milad, D.Gudeczauskas, G.Obrien, A.Gruenwald Uyemura International Corporation Southington, CT ABSTRACT: The solder joint formed on an ENEPIG surface
More informationDevelopment of a Fluxless Flip Chip Bonding Process for Optical Military Electronics
Development of a Fluxless Flip Chip Bonding Process for Optical Military Electronics Michael Girardi, Daric Laughlin, Philip Abel, Steve Goldammer, John Smoot NNSA s Kansas City Plant managed by Honeywell
More informationAustralian Journal of Basic and Applied Sciences. Pb-Free Solder Ball Robustness Comparison under AC and TC Reliability Test
AENSI Journals Australian Journal of Basic and Applied Sciences ISSN:1991-8178 Journal home page: www.ajbasweb.com Pb-Free Solder Ball Robustness Comparison under AC and TC Reliability Test 1,2 Tan Cai
More informationContamination on. Semiconductor Assembly: A Failure Analysis Perspective BY JONATHAN HARRIS, CMC LABORATORIES, INC.
The Impact of Plated Layer Contamination on Semiconductor Assembly: A Failure Analysis Perspective BY JONATHAN HARRIS, CMC LABORATORIES, INC. In the world of both package and board level assembly, the
More informationLead Free Surface Mount Technology. Ian Wilding BSc Senior Applications Engineer Henkel Technologies
Lead Free Surface Mount Technology Ian Wilding BSc Senior Applications Engineer Henkel Technologies Overview of the Presentation First contact: Impact on the production operator Packaging Labelling Impact
More informationBonding Technologies for 3D-Packaging
Dresden University of Technology / Karsten Meier, Klaus-Juergen Wolter NanoZEIT seminar @ SEMICON Europa 2011 Dresden System integration by SoC or SiP solutions offer advantages regarding design efforts,
More informationEncapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga )
Encapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga ) Henry M.W. Sze, Marc Papageorge ASAT Limited 14th Floor, QPL Industrial Building, 138 Texaco Road, Tseun Wan, Hong
More informationElectrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer
Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer Li Zheng, Student Member, IEEE, and Muhannad S. Bakir, Senior Member, IEEE Georgia Institute of Technology Atlanta,
More informationNext Gen Packaging & Integration Panel
Next Gen Packaging & Integration Panel ECTC 2012 Daniel Tracy, Sr. Director Industry Research & Statistics SEMI May 29, 2012 Packaging Supply Chain Market Trends Material Needs and Opportunities Market
More informationNovel Materials and Activities for Next Generation Package. Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima
Novel Materials and Activities for Next Generation Package Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima 1. Activities of Packaging Solution Center 2. Novel Materials for Next Gen.
More informationWire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017
Amkor Technology, Inc. White Paper Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017 Abstract Expanding its ChipArray Ball Grid Array (CABGA) package form factor miniaturization
More informationAging Treatment Characteristics of Shear Strength in Micro Solder Bump
Materials Transactions, Vol. 43, No. 2 (22) pp. 3234 to 3238 c 22 The Japan Institute of Metals Aging Treatment Characteristics of Shear Strength in Micro Solder Bump Chong-Hee Yu, Kyung-Seob Kim 2, Yong-Bin
More informationSupplementary Materials for
www.sciencemag.org/cgi/content/full/336/6084/1007/dc1 Supplementary Materials for Unidirectional Growth of Microbumps on (111)-Oriented and Nanotwinned Copper Hsiang-Yao Hsiao, Chien-Min Liu, Han-wen Lin,
More informationHow Bad's the Damage?
How Bad's the Damage? Evaluating Probe Damage On Aluminum, Solder, Gold, UBM, and Copper Pads. Ken Smith Vice President of Technology Development Pyramid Probe Division, Cascade Microtech Goal of Presentation
More informationProject Proposal. Cu Wire Bonding Reliability Phase 3 Planning Webinar. Peng Su June 6, 2014
Project Proposal Cu Wire Bonding Reliability Phase 3 Planning Webinar Peng Su June 6, 2014 Problem Statement Background Work of the inemi Cu wire reliability project identified that bonding quality and
More informationLS720V Series. Comparison of crack progression between Sn-Cu-Ni-Ge and M773. Development of Ag-free/M773 alloy
LS72V Series Low-Ag/Ag-free solder pastes with lower void Reduces voids by improving fluidity of flux during solder melting Reduces voids even in bottom surface electrode type components by improving solder
More informationTSV Processing and Wafer Stacking. Kathy Cook and Maggie Zoberbier, 3D Business Development
TSV Processing and Wafer Stacking Kathy Cook and Maggie Zoberbier, 3D Business Development Outline Why 3D Integration? TSV Process Variations Lithography Process Results Stacking Technology Wafer Bonding
More informationFlip Chip - Integrated In A Standard SMT Process
Flip Chip - Integrated In A Standard SMT Process By Wilhelm Prinz von Hessen, Universal Instruments Corporation, Binghamton, NY This paper reviews the implementation of a flip chip product in a typical
More informationLead Free Solder for Flip Chip
Lead Free Solder for Flip Chip Zhenwei Hou & R. Wayne Johnson Laboratory for Electronics Assembly & Packaging Auburn University 162 Broun Hall, ECE Dept. Auburn, AL 36489 USA 334-844-1880 johnson@eng.auburn.edu
More informationHBLED packaging is becoming one of the new, high
Ag plating in HBLED packaging improves reflectivity and lowers costs JONATHAN HARRIS, President, CMC Laboratories, Inc., Tempe, AZ Various types of Ag plating technology along with the advantages and limitations
More informationEXTRA FINE PITCH FLIP CHIP ASSEMBLY PROCESS, UNDERFILL EVALUATION AND RELIABILITY
As originally published in the SMTA Proceedings EXTRA FINE PITCH FLIP CHIP ASSEMBLY PROCESS, UNDERFILL EVALUATION AND RELIABILITY Fei Xie, Ph.D. *, Daniel F. Baldwin, Ph.D. *, Han Wu *, Swapon Bhattacharya,
More informationAs originally published in the IPC APEX EXPO Conference Proceedings.
As originally published in the IPC APEX EXPO Conference Proceedings. Influence of Salt Residues on BGA Head in Pillow (Hip) J. Servin, C. Gómez, M. Domínguez, A. Aragón CONTINENTAL CUAUTLA Av. Ignacio
More informationEffect of Reflow Profile (RSP Vs RTP) on Sn/Ag/Cu Solder Joint Strength in Electronic Packaging
ISSN 2231-8798 2012 UniKLBMI Effect of Reflow Profile (RSP Vs RTP) on Sn/Ag/Cu Solder Joint Strength in Electronic Packaging I. Ahmad 1, A. Jalar 2 Z. Kornain 3 & U. Hashim 4 1 Universiti Tenaga Nasional
More informationSIDE WALL WETTING INDUCED VOID FORMATION DUE TO SMALL SOLDER VOLUME IN MICROBUMPS OF Ni/SnAg/Ni UPON REFLOW
SIDE WALL WETTING INDUCED VOID FORMATION DUE TO SMALL SOLDER VOLUME IN MICROBUMPS OF Ni/SnAg/Ni UPON REFLOW Y. C. Liang 1, C. Chen 1, *, and K. N. Tu 2 1 Department of Materials Science and Engineering,
More informationT/C stress resistant high reliability solder alloy SB6NX / SB6N. Patented by Panasonic
T/C stress resistant high reliability solder alloy X / Patented by Panasonic Sn 3.5Ag 0.5Bi 6.0In 0.8Cu Sn 3.5Ag 0.5Bi 6.0In X & solder alloy X alloy is Panasonic patented Conventional (Sn3.5Ag0.5Bi6In)
More informationA Roadmap to Low Cost Flip Chip Technology and Chip Size Packaging using Electroless Nickel Gold Bumping
A Roadmap to Low Cost Flip Chip Technology and Chip Size Packaging using Electroless Nickel Gold Bumping T. Oppert, T. Teutsch, E. Zakel Pac Tech Packaging Technologies GmbH Am Schlangenhorst 15-17, Germany
More informationUltra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes
Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes Andrew Strandjord, Thorsten Teutsch, and Jing Li Pac Tech USA Packaging Technologies, Inc. Santa Clara, CA USA 95050 Thomas Oppert, and
More informationEffect of Multiple Flip-Chip Assembly on Joint Strength of AuSn solder in Hybrid Compact Optoelectronic Module
1 Effect of Multiple Flip-Chip Assembly on Joint Strength of AuSn solder in Hybrid Compact Optoelectronic Module K.-M. Chu, Student Member, IEEE, J.-S. Lee, H. Oppermann, G. Engelmann, J. Wolf, H. Reichl,
More informationChallenges and Solutions for Cost Effective Next Generation Advanced Packaging. H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012
Challenges and Solutions for Cost Effective Next Generation Advanced Packaging H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012 Outline Next Generation Package Requirements ewlb (Fan-Out Wafer
More informationHenkel Enabling Materials for Semiconductor and Sensor Assembly. TechLOUNGE, 14 November 2017
Henkel Enabling Materials for Semiconductor and Sensor Assembly TechLOUNGE, 14 November 2017 Content Brief HENKEL Introduction and ELECTRONICS Focus Areas Innovative Semiconductor and Sensor Assembly Solutions
More informationLead Free Soldering Technology
Lead Free Soldering Technology Chung-Ang University Young-Eui Shin Trend of Package Small, Light, High performance High speed, Large capacity High integrity, High density Comparison of package size 45mm
More informationAdaption to scientific and technical progress under Directive 2002/95/EC
. Adaption to scientific and technical progress under Directive 2002/95/EC Results previous evaluation Exemption No. 15 Lead in solders to complete a viable electrical connection between semiconductor
More informationDevelopments in low-temperature metal-based packaging
Developments in low-temperature metal-based packaging 2011. 12.14 Jiyoung Chang and Liwei Lin Ph.D. Candidate, Department of Mechanical Engineering University of California at Berkeley 1 1 Contents Project
More informationBasic PCB Level Assembly Process Methodology for 3D Package-on-Package
Basic PCB Level Assembly Process Methodology for 3D Package-on-Package Vern Solberg STC-Madison Madison, Wisconsin USA Abstract The motivation for developing higher density IC packaging continues to be
More informationEPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS
As originally published in the SMTA Proceedings. EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS Neil Poole, Ph.D., Elvira Vasquez, and Brian J. Toleno, Ph.D. Henkel Electronic
More informationAdaption to scientific and technical progress under Directive 2002/95/EC
. Adaption to scientific and technical progress under Directive 2002/95/EC Results previous evaluation Exemption No. 7 a a) Lead in high melting temperature type solders (i.e. lead-based alloys containing
More information5. Packaging Technologies Trends
5. Packaging Technologies Trends Electronic products and microsystems continue to find new applications in personal, healthcare, home, automotive, environmental and security systems. Advancements in packaging
More informationRecent Advances in Die Attach Film
Recent Advances in Die Attach Film Frederick Lo, Maurice Leblon, Richard Amigh, and Kevin Chung. AI Technology, Inc. 70 Washington Road, Princeton Junction, NJ 08550 www.aitechnology.com Abstract: The
More informationInterfacial Reactions between the Sn-9Zn Solder and Au/Ni/SUS304 Multi-layer Substrate
, July 6-8, 2011, London, U.K. Interfacial Reactions between the Sn-9Zn Solder and Au/Ni/SUS304 Multi-layer Substrate *Yee-Wen Yen 1, Chien-Chung Jao 2, Kuo-Sing Chao 1, Shu-Mei Fu Abstract Sn-9Zn lead-free
More informationCopper Wire Packaging Reliability for Automotive and High Voltage
Copper Wire Packaging Reliability for Automotive and High Voltage Tu Anh Tran AMPG Package Technology Manager Aug.11.2015 TM External Use Agenda New Automotive Environments Wire Bond Interconnect Selection
More informationSelection and Application of Board Level Underfill Materials
Selection and Application of Board Level Underfill Materials Developed by the Underfill Materials Design, Selection and Process Task Group (5-24f) of the Assembly and Joining Committee (5-20) of IPC Supersedes:
More informationIMC Layers Formed with Various Combinations of Solders and Surface Finishes and Their Effect on Solder Joint Reliability
IMC Layers Formed with Various Combinations of Solders and Surface Finishes and Their Effect on Solder Joint Reliability Per-Erik Tegehall, Swerea IVF 4 th Electronic Materials and Assembly Processes for
More informationThe Relationship of Components, Alloys and Fluxes, Part 1
The Relationship of Components, Alloys and Fluxes, Part 1 By Dr. Ning-Cheng Lee Saturday, 01 October 2005 Call it a love triangle or a Bermuda Triangle. Either way, the best alloy may be determined by
More informationMaterial Selection and Parameter Optimization for Reliable TMV Pop Assembly
Selection and Parameter Optimization for Reliable TMV Pop Assembly Brian Roggeman, David Vicari Universal Instruments Corp. Binghamton, NY, USA Roggeman@uic.com Martin Anselm, Ph.D. - S09_02.doc Lee Smith,
More informationRecent Trends of Package Warpage and Measurement Metrologies (inemi Warpage Characterization Project Phase 3)
Recent Trends of Package Warpage and Measurement Metrologies (inemi Warpage Characterization Project Phase 3) Wei Keat Loh 1, Ron Kulterman 2, Haley Fu 3, Masahiro Tsuriya 3 1 Intel Technology Sdn. Bhd.
More informationFLUX AND CHEMICAL PRODUCTS FOR ELECTRONIC SOLDERING
FLUX AND CHEMICAL PRODUCTS FOR ELECTRONIC SOLDERING C1 CRM :) SlfNl!llGll!S activation range. No dean flux with a 4.5% in solid contents. Green Flux pens. Precise control in the flux deposition. ldeal
More informationEFFECT OF THERMAL AGING ON THE IMC LAYER BETWEEN SnAgSb SOLDER AND Cu SUBSTRATE. Universiti Kebangsaan Malaysia, 43600, Bangi, Selangor, Malaysia
EFFECT OF THERMAL AGING ON THE IMC LAYER BETWEEN SnAgSb SOLDER AND Cu SUBSTRATE W. Shualdi 1, I. Ahmad 1, G. Omar 2 and A. Isnin 3 1 Department of Electrical, Electronic and System, Faculty of Engineering,
More informationCERN/NA62 GigaTracKer Hybrid Module Manufacturing
CERN/NA62 GigaTracKer Hybrid Module Manufacturing Fraunhofer Institute for Reliability and Microintegration Gustav-Meyer-Allee 25 13355 Berlin Germany Dipl.-Ing. Thomas Fritzsch Contact: Fraunhofer IZM
More informationFlip chip bumping technology Status and update
Nuclear Instruments and Methods in Physics Research A 565 (2006) 290 295 www.elsevier.com/locate/nima Flip chip bumping technology Status and update M. Juergen Wolf, Gunter Engelmann, Lothar Dietrich,
More informationPoP/CSP Warpage Evaluation and Viscoelastic Modeling
PoP/CSP Warpage Evaluation and Viscoelastic Modeling Wei Lin, Min Woo Lee Amkor Technology 19 S Price Rd, Chandler, AZ 85286 wlin@amkor.com Abstract The purpose of this paper was to evaluate the critical
More informationReaction of Sn-Bearing Solders with Nickel-based Under Bump Metallisations
STR/03/069/ST Reaction of Sn-Bearing Solders with Nickel-based Under Bump Metallisations G. Qi, M. He and Z. Chen Abstract This work relates to wafer bumping technologies for flip chip packaging applications
More informationRELIABILITY OF SAC405 AND SAC387 AS LEAD-FREE SOLDER BALL MATERIAL FOR BALL GRID ARRAY PACKAGES
123 RELIABILITY OF SAC405 AND SAC387 AS LEAD-FREE SOLDER BALL MATERIAL FOR BALL GRID ARRAY PACKAGES 1 I. Ahmad, 2 A. Jalar, 1 B.Y. Majlis and 3 R. Wagiran 1 Department of Electrical, Electronic and System
More informationCharacterization of Coined Solder Bumps on PCB Pads
Characterization of Coined Solder Bumps on PCB Pads Jae-Woong Nah, Kyung W. Paik, Won-Hoe Kim*, and Ki-Rok Hur** Department of Materials Sci. & Eng., Korea Advanced Institute of Science and Technology
More information*EP A2* EP A2 (19) (11) EP A2 (12) EUROPEAN PATENT APPLICATION. (43) Date of publication: Bulletin 2005/08
(19) Europäisches Patentamt European Patent Office Office européen des brevets *EP00891A2* (11) EP 1 08 91 A2 (12) EUROPEAN PATENT APPLICATION (43) Date of publication: 23.02.0 Bulletin 0/08 (1) Int Cl.
More information3D Package Technologies Review with Gap Analysis for Mobile Application Requirements. Apr 22, 2014 STATS ChipPAC Japan
3D Package Technologies Review with Gap Analysis for Mobile Application Requirements Apr 22, 2014 STATS ChipPAC Japan T.Nishio Contents Package trends and roadmap update Advanced technology update Fine
More informationIME Technical Proposal. High Density FOWLP for Mobile Applications. 22 April High Density FOWLP Consortium Forum
IME Technical Proposal High Density FOWLP for Mobile Applications 22 April 2014 Packaging driver for portable / mobile applications Key drivers/needs Smaller form-factor lower profile, substrate-less Higher
More informationA Flexible Vertical MEMs Probe Card Technology for Pre-Bump and ewlp Applications
June 12 to 15, 2011 San Diego, CA A Flexible Vertical MEMs Probe Card Technology for Pre-Bump and ewlp Applications Mike Slessor Rick Marshall (MicroProbe, Inc.) Vertical MEMS for Pre-Bump Probe Introduction:
More informationHigh Density PoP (Package-on-Package) and Package Stacking Development
High Density PoP (Package-on-Package) and Package Stacking Development Moody Dreiza, Akito Yoshida, *Kazuo Ishibashi, **Tadashi Maeda, Amkor Technology Inc. 1900 South Price Road, Chandler, AZ 85248, U.S.A.
More informationCLAD MATERIAL ~ FINE CLAD is a solution for high density, low cost PWB.
~ CLAD MATERIAL ~ FINE CLAD is a solution for high density, low cost PWB. Principle of bonding technique Principle of bonding technique Step 1 Material A, B In vacuum Step 2 Surface activated treatment
More informationINEMI Packaging Substrate Workshop, Toyama, Japan, 2014 Challenges of Organic Substrates from EMS Perspective Weifeng Liu, Ph. D.
INEMI Packaging Substrate Workshop, Toyama, Japan, 2014 Challenges of Organic Substrates from EMS Perspective Weifeng Liu, Ph. D. Date (4/10/2014) AEG - WW Microelectronics and Packaging OUTLINE Overview
More informationCopper Wire Bonding Technology and Challenges
Copper Wire Bonding Technology and Challenges By Dr Roger Joseph Stierman Date: 21 & 22 October 2013 Venue: SHRDC, Shah Alam, Selangor *2 days training package RM 3,000 per pax [*] * includes hotel accommodation
More informationAssembly Challenges in Developing 3D IC Package with Ultra High Yield and High Reliability
Assembly Challenges in Developing 3D IC Package with Ultra High Yield and High Reliability Raghunandan Chaware, Ganesh Hariharan, Jeff Lin, Inderjit Singh, Glenn O Rourke, Kenny Ng, S. Y. Pai Xilinx Inc.
More informationEffect of pinhole Au/Ni/Cu substrate on self-alignment of advanced packages
Materials Science and Engineering B76 (2000) 87 94 www.elsevier.com/locate/mseb Effect of pinhole Au/Ni/Cu substrate on self-alignment of advanced packages K.C. Hung, Y.C. Chan *, H.C. Ong, P.L. Tu, C.W.
More informationBy Ron Blankenhorn, Pac Tech USA, Santa Clara, Calif., and Thomas Oppert, Pac Tech GbmH, Nauen, Germany
INTRODUCTION Modern microelectronic products require packages that address the driving forces of reduced size and weight, as well as increased performance at high frequencies. Flipchip and direct chip
More informationEffectiveness of Conformal Coat to Prevent Corrosion of Nickel-palladium-goldfinished
As originally published in the IPC APEX EXPO Conference Proceedings. Effectiveness of Conformal Coat to Prevent Corrosion of Nickel-palladium-goldfinished Terminals Michael Osterman Center for Advanced
More informationSilver Diffusion Bonding and Layer Transfer of Lithium Niobate to Silicon
Chapter 5 Silver Diffusion Bonding and Layer Transfer of Lithium Niobate to Silicon 5.1 Introduction In this chapter, we discuss a method of metallic bonding between two deposited silver layers. A diffusion
More information