Reliability Evaluation of CIF (chip-in-flex) and COF (chip-on-flex) packages

Reliability Evaluation of CIF (chip-in-flex) and COF (chip-on-flex) packages Jae-Won Jang* a, Kyoung-Lim Suk b, Kyung-Wook Paik b, and Soon-Bok Lee a a Dept. of Mechanical Engineering, KAIST, 335 Gwahangno Yuseong-Gu, Daejeon, Korea; b Dept. of Materials Science and Engineering, KAIST, 335 Gwahangno Yuseong-Gu, Daejeon, Korea ABSTRACT CIF (chip-in-flex) and COF (chip-on-flex) packages have the advantages of fine pitch capability, and flexibility. Anisotropic conductive films (ACFs) are used for the interconnection between chip and substrate. Display, mobile device, and semiconductor industry require for smaller and more integrated packages. Both CIF and COF packages are an alternative for the demands. However, there are some reliability problems of interconnection between the chip and substrate because the packages are subjected to various loading conditions. These may degrade the functionality of the packages. Therefore, reliability assessment of both packages is necessary. In this study, experimental tests were performed to evaluate the reliability of interconnection between the chip and substrate of CIF and COF packages. Thermal cycling tests were performed to evaluate the resistance against thermal fatigue. The shape and warpage of the chip of CIF and COF packages were observed using optical methods (e.g., shadow Moiré and Twyman/Green interferometry). These optical Moiré techniques are widely used for measuring small deformations in microelectronic packages. The stress distribution around the chip was evaluated through FEA (finite element analysis). In addition, we suggested modifying design parameter of CIF packages for the reliability enhancement. Keywords: CIF, COF, Reliability, Shadow Moiré, Twyman/Green interferometry, Thermal cycling test, FEA 1. INTRODUCTION In last a decade, electronic devices are rapidly developed. As a result, nowadays, we can use small and mobile electronic products such as cellular phone, MP3 players, and PMP (portable multimedia players). Furthermore, these products becomes smaller and smaller. Nevertheless, these include many enhancements and more features than last ones to meet consumer demands. In other words, microelectronic packages of the products are more integrated, smaller, and thinner than before. It is realized by using flip-chip assembly, and adhesive interconnection. Flip-chip assembly using adhesive interconnection offered several advantages of small packages size, fine pitch for high I/O density, and environmental compatibility [1], [2]. In addition, the flexibility of the flip-chip assembly is increased by using thin and flexible substrate. CIF and COF packages have thin and flexible substrate. CIF packages are fabricated by adding two more flex substrate on COF packages. As mentioned, CIF and COF packages have many advantages. However, these packages are exposed to serious mechanical problems due to the temperature profile during packaging process and various loading conditions. For example, the shrinkage of ACF induces the warpage of the packages. When the power of the packages turns on and off periodically, they experience thermal fatigue. *jwjang@kaist.ac.kr; phone +82-42-350-3069; fax +82-42-350-5013; care.kaist.ac.kr

In this study, the reliability of CIF and COF packages was evaluated. To investigate the thermal reliability of the packages, thermal cycling tests were performed. We used optical method to measure the warpage and shape of the packages. Moiré technique is adequate and widely used to measure the small deformation in microelectronic packages. Out-of-plane deformation of the specimens was investigated by using shadow Moiré and Twyman/Green interferometry. Stress distribution around the chip was obtained by FEA. 2. SPECIMENS COF packages specimen consists of a silicon chip and a flex substrate (1 st flex substrate). For the interconnection between the chip and flex substrate, ACF was used. In case of CIF packages specimen, two more flex substrates (2 nd and 3 rd flex substrates) were stacked on COF packages, and ACFs were used for the assembly between the 1 st and 2 nd, and 2 nd and 3 rd substrates. These ACFs were different from that used for COF assembly. Figure 1 shows the COF and CIF packages specimens. Schematic diagrams of cross section are illustrated in Figure 2. (a) Figure 1. (a) COF, and (b) CIF packages specimen. (b) (a) Figure 2. Schematic diagram of (a) COF, and (b) CIF packages specimen. (b) Specification and thermo-mechanical properties of materials consist of the packages are listed in Tables 1 and 2 [3]-[5]. Table 1. Specification of flex substrates 1 st PI 2 nd PI 3 rd PI Size [mm 2 ] 26 26 14 14 15 15 PI thickness [µm] 20 80 (including adhesive) 20 Cu electrode upper: 27 15 thickness [µm] bottom: 27 15 Table 2. Thermo-mechanical properties of materials E [GPa] ν T g [ C] CTE [ppm/ C] Polyimide 6.0 0.41-21 Silicon 112.4 0.280-2.6 Gold 77.2 0.420-14.4 Copper 110 0.343-21 ACF 1 0.665 0.25 117.4 below T g : 113 above T g : 5977 ACF 2 0.797 0.25 114.8 below T g : 79.4 above T g : 2812

3. THERMAL CYCLING TEST Thermal cycling test was performed to evaluate the resistance against thermal fatigue. In this study, test condition G of JESD22-A104C is used [6]. Temperature profile of the test is from -40 C to 125 C. Holding time at low and high temperature is 15 minutes. The packages are electrically failed when Au bump and Cu electrode are disconnected, and this phenomenon occurs as the contact area between Au bump and Cu electrode is decreased. Decreasing contact area leads to increasing contact resistance. Therefore, we measured the contact resistance between 1 st flex substrate and chip to detect the failure of the packages. 4. MOIRÉ EXPERIMENTS Excessive warpage of the packages causes several reliability problems such as inducing mechanical peel stress, disconnection to next level package, and increasing the possibility of die cracking [7]-[10]. Therefore, it is essential to investigate the warpage of the packages to enhance their reliability. This is a basic principle of Moiré technique. As two grating (reference and specimen grating) with similar frequency are interfered, the intensity of light are constructed or deconstructed. This constructed and deconstructed pattern is called as Moiré fringes. When reference or specimen grating is deformed, it is amplified by the deformation of Moiré fringes. (a) (b) Figure 3. Schematic diagram of (a) shadow Moiré system [11], and (b) Twyman/Green intreferometry [12]. Shadow Moiré is one of the geometric Moiré, and its principle is illustrated in figure 3 (a). In this method, real reference grating is needed to measure the out-of-plane deformation. Another grating is the shadow of real reference grating on the specimen. Moiré fringes are produced by superposition of these two gratings [13]. The out-of-plane displacement W can be determined by g W( x,y ) = N ( x,y ) tan a + tanb z = N z( x,y ) where g is the pitch of real reference grating, and N z is the fringe order at each point in the fringe pattern. Figure 3 (b) shows the principle of Twyman/Green interferometry. This method is also used to measure the out-of-plane deformation like shadow Moiré. The laser beam is divided into two parts by beam splitter. One part of the laser beam is incident to the reference mirror, and then, reflected. Another incident laser beam is also reflected from the specular surface of the specimen. After this process, the wave front shape of reflected laser is different from that of incident laser due to inflated surface of the specimen. Moiré fringes are produced by the interference of these two reflected lasers [12]. The relationship between out-of-plane displacement W and fringe order N z is λ W( x,y ) = N z( x,y ) (2) 2 where N z is the fringe order at each point in the fringe pattern, and λ is the wave length of the laser. gl D (1)

4.1 The shape of whole field and the chip The shape of whole field and the chip of CIF and COF packages were observed by using shadow Moiré. To use this method, it is needed that uniform reflectivity of the specimen surface. However, in case of COF packages, the reflectivity of the chip surface is different from that of flex substrate surface. In this study, therefore, the bottom side of the specimen which has the substrate surface only was observed. 4.2 The warpage of the chip The warpage of the chip in CIF and COF packages were measured by using improved shadow Moiré and Twyman/Green interferometry. The principle of improved shadow Moiré is same as shadow Moiré. The difference between these two methods is that real reference grating which has finer pitch than that used for shadow Moiré is used. If the chip which has a specular surface is exposed, the warpage of the chip can be measured by using Twyman/Green interferometry. However, in case of COF packages, it cannot be measured directly because the warpage of chip is larger than about 10µm. In case of normal COB (chip-on-board) packages, the warpage of the chip and temperature show linear behavior. The warpage of the chip is linearly decreased as temperature increased under T g of ACF [14]. Therefore, if the warpage behavior of the chip in COF packages shows similar to that in COB packages, the warpage of the chip in COF packages at room temperature can be extrapolated by the values at higher temperatures. 5. FINITE ELEMENT ANALYSIS In-plane Moiré interferomety is used to observe in-plane deformation of conventional thick packages. However, it is difficult to observe in-plane deformation by this optical method due to thin thickness of CIF and COF packages. Therefore, finite element analysis was performed alternatively by using ABAQUS to observe the stress distribution of CIF and COF packages. In case of conventional thick packages structure, it can be neglected the effect of pattern layer which has smaller thickness than the chip and substrate [15]. However, in case of COF packages, the thickness of pattern layer and Au bump is about one fifth of total thickness of the packages. Therefore, we cannot neglect the effect of pattern layer in thin packages. In this study, not only pattern layer but Au bump was modeled for FEA. 6.1 Thermal cycling test 6. RESULTS In this study, we evaluated the resistance of CIF and COF packages against thermal fatigue through thermal cycling tests. From the tests, we obtained the change of contact resistance as the number of cycle increases (Figure 4). (a) (b) (c) Figure 4. Thermal cycling test results of (a) CIF, (b) COF, and (c) both packages.

As shown at Figure 4, the contact resistance of both packages increases as the number of cycle increases. The contact resistance of CIF packages increases more and shows larger variation than that of COF packages. If the delamination between the Au bump and Cu electrode is occurred, the contact resistance increases dramatically. Since the result of contact resistance increase is small, it is not regarded as delamination. 6.2 Moiré experiments 6.2.1 The shape of whole field and the chip We observed out-of-plane Moiré images of CIF and COF packages through shadow Moiré (Figure 5). Original image π/2 π 3π/2 CIF COF Figure 5. Out-of-plane Moiré images of CIF and COF packages. Phase shifted (π/2, π, and 3π/2) images from original image were also observed. From these images, we can obtain 3- dimensional information of the packages by using phase shifting method. Standard view Top view XZ plane YZ plane CIF COF Figure 6. 3-dimensional, XZ, and YZ plane cross section images of CIF and COF packages. Figure 6 shows 3-dimensional, XZ, and YZ plane cross section images of the packages. From these images, we have known that the warpage shape of CIF and COF packages was different. In case of CIF packages, the warpage shape was like a cup. On the other hand, that of COF packages was symmetrical to XZ plane, and bends upward. Figure 7 shows YZ plane schematic diagram of CIF and COF packages. The chip of CIF packages bended upward. However, that of COF packages bended downward.

(a) Figure 7. Cross section schematic diagram of (a) COF, and (b) CIF packages. (b) The reason to these differences comes from structural difference between CIF and COF packages. The 1 st flex substrate had primitive curvature like thin film. Therefore, the warpage shape of whole field was upward both CIF and COF packages. After completing COF assembly process, the package was cooled from 180 C to 25 C. ACF between the chip and 1 st flex substrate contracted significantly as temperature decreased due to its high coefficient of thermal expansion (CTE). The 1 st flex substrate contracted more than the chip because its CTE is higher than that of the chip (see Table 2). Therefore, the chip of COF packages bended downward. However, it was needed two more flex substrates and flex-to-flex (FOF) assembly to fabricate CIF packages. The thickness of ACF between the chip and 3 rd flex substrate is about 2.5 times higher than that between the chip and 1 st flex substrate. When CIF packages were cooled from an assembly temperature, ACF between the chip and 3 rd flex substrate was cured and contracted more than that between and 1 st flex substrate and the chip. Therefore, the chip of CIF packages bended upward opposite to the result of COF packages. Furthermore, from this result, we have known that the warpage of the chip can be minimized by reducing thickness of ACF between the chip and 3 rd flex substrate. 6.2.2 The warpage of the chip 6.2.2.1 The warpage behavior of the chip We observed the warpage behavior of the chip in COF packages through Twyman/Green interferometry. The temperature of the specimen increased from room temperature to 120 C. Figure 8. The warpage behavior of the chip in COF packages. Figure 8 shows the warpage behavior of the chip in COF packages. It is negative linear to temperature under certain temperature. From this temperature, the warpage does not show large variation, and then, it restarts to decrease linearly. We can extrapolate the warpage of the chip at room temperature from the region that the warpage linearly decreases as increasing temperature. In addition, it shows two different behaviors from normal COB. First, the warpage shape is reversed above certain temperature. Second, it is unlike normal COB, the warpage of the chip is not convergent above T g of ACF. To define these phenomena obviously, further experiments using the specimens with various thicknesses of the chip and substrate are needed. 6.2.2.2 The warpage of 1 st flex substrate and the chip We obtained out-of-plane original and phase shifted (π/2, π, and 3π/2) Moiré images of COF packages through improved shadow Moiré (Figure 9). Figure 10 shows 3-dimensional image of COF packages measured by using phase shifting

method. Original image π/2 π 3π/2 Figure 9. Out-of-plane Moiré images of COF packages obtained by using improve shadow Moiré. Standard view Top view Figure 10. 3-dimensional images of COF packages. We observed the warpage of the chip in COF packages during increasing temperature through Twyman/Green interferometry (Figure 11) and calculate the warpage. 41 C 45 C 47 C 50 C Figure 11. Moiré images of the chip in COF packages at each temperature. The warpage of the chip at room temperature was obtained by extrapolating the values at higher temperature. These values and the warpage of 1 st flex substrate are listed in Table 3. Table 3. The warpage of 1 st flex substrate and the chip of COF packages (unit: µm). Specimen Warpage of 1 st flex Warpage of the chip substrate (1) (2) (1) - (2) 1 25.9 17.7 8.2 2 26.1 17.2 8.9 3 22.4 17.5 4.9 Average 24.8 17.5 7.3 As the results, the warpage of 1 st flex substrate was larger than that of the chip in all cases. The difference between them is 7.3 µm. Therefore, we can estimate the warpage of the chip in CIF packages by subtracting 7.3 µm from the warpage of 1 st flex substrate of the packages which was also obtained by using improved shadow Moiré and phase shifting method (Table 4).

Table 4. The warpage of 1 st flex substrate and the chip of CIF packages (unit: µm). Specimen Warpage of 1 st flex substrate Estimated warpage of the chip 1 33.6 26.3 2 22.9 15.6 3 25.2 17.9 Average 27.2 19.9 As the results, the absolute value of the chip warpage of CIF packages was larger than that of COF packages. However, they were not significantly different. 6.3 Finite element analysis We performed FEA to investigate the stress distribution around the chip of CIF and COF packages. Both packages were modeled a quarter of themselves by imposing symmetric boundary condition with C3D8T three-dimensional quadratic brick elements. The specification and thermo-mechanical properties of the packages are listed Tables 1 and 2. Modeled images Meshed images Deformed images CIF COF Figure 12. FEA results (a) Figure 13. XZ plane cross section images of (a) CIF, and (b) COF packages. (b) Figure 14. Stress distribution along the chip.

In Figures 12 and 13, the deformation shapes of the chip in both packages were the same as them obtained by using Moiré experiment. The chip of CIF packages bended upward, and that of COF packages bended downward. Figure 14 shows stress distribution from the center to end of the chip. The stress magnitude increases dramatically near the edge of the chip where the Au bump is located. The stress of CIF packages showed higher value than that of COF packages. The possibility of crack initiation which can lead the delamination between the chip and substrate is the most highest at the edge of the chip. Most of the chip stress is induced due to curing of adhesive [16], and thick adhesive layer induces more chip stress than thin adhesive layer [17]. Therefore, this result also can be explained by the thickness of ACF between the chip and 3 rd flex substrate. 7. CONCLUSIONS COF and CIF packages with embedded silicon chip have the advantages of compact size, flexibility, and high performance. In this paper, we evaluated reliability of CIF and COF packages through thermal cycling test, optical method, and FEA. To investigate the thermal resistance of the packages, thermal cycling tests were performed. By using optical method (i.e., Moiré technique), we observed the warpage shape of the whole field and the chip of the packages. Finite element analysis was performed to obtain stress distribution around the chip. Both CIF and COF packages were reliable for thermal fatigue. However, the contact resistance increment of CIF package was higher than that of COF packages. From the Moiré experiments, it was observed that the warpage shape of these packages was different. The chip of COF packages bended upward, and that of CIF packages bended downward. The absolute value of the chip warpage of CIF package was larger than that of COF package. FEA results showed that the stress magnitude of COF package was lower value than that of CIF package along the chip. Overall experiments, CIF packages showed similar reliability with COF packages. However, we have known that the warpage of the chip is reversed after packaging process. The reason of this phenomenon is that the ACF between the chip and 3 rd flex substrate is thicker than that between 1 st flex substrate and the chip. Therefore, we expect that minimizing warpage and reliability enhancement of CIF packages can be realized by reducing the design parameter (thickness of ACF between the chip and 3 rd flex substrate). ACKNOWLEDGMENTS This research was supported by a grant(2009k000180) from Center for Nanoscale Mechatronics & Manufacturing, one of the 21st Century Frontier Research Programs, which are supported by Ministry of Education, Science and Technology, KOREA REFERENCES [1] A. M. Lyons et al., A New Approach to Using Anisotropically Conductive Adhesives for Flip-Chip Assembly, IEEE Transactions on Components, Packaging and Manufacturing Technology Part A, Vol. 19, 5-11 (1996). [2] J. S. Rasul, Chip on paper technology utilizing anisotropically conductive adhesive for smart label applications, Microelectronics Reliability, Vol. 44, 135-140 (2004). [3] K. L. Suk, H. Y. Son, C. K. Chung, J. D. Kim, J. W. Lee, and K. W. Paik, Embedded Chip-in-Flex (CIF) Packages using Wafer Level Package (WLP) with Pre-Applied Anisotropic conductive films (ACFs), The 59th Electronic Components and Technology Conference, San Diego, U.S.A, 26-29 (2009). [4] S. J. Ham, S. B. Lee, Measurement of Creep and Relaxation Behaviors of Wafer-Level CSP Assembly Using Moiré Interferometry, ASME, 282 (2003).

[5] K. C. Chang, Y. M. Kwon, I. Kim, H. Y. Son, K. S. Choo, S. J. Kim, and K. W. Paik, Theoretical Prediction and Experimental Measurement of the Degree of Cure of Anisotropic Conductive Films (ACFs) for Chip-On-Flex (COF) Applications, Journal of Electronic Materials, Vol. 37, 1580-1590 (2008). [6] JEDEC Standard, JEDEC Solid State Technology Association (2005). [7] H. Ding et al., Warpage Measurement Comparison Using Shadow Moiré and Projection Moiré Methods, IEEE Transactions on Components and Packaging Technologies, Vol. 25, 714-721 (2002). [8] J. B. Han, Deformation mechanism of two-phase solder column interconnections under highly accelerated thermal cycling condition: an experimental study, ASME Journal of Electronic Packaging, Vol. 119, 189-196 (1997). [9] S. Michaelides and S. K. Sitaraman, Die Cracking and Reliable Die Design for Flip-Chip Assemblies, IEEE Transactions on Advanced Packaging, Vol. 22, 602 (1999). [10] D. G. Yang et al., Vertical die crack stresses of Flip Chip induced in major package assembly processes, Microelectronics Reliability, Vol. 40, 1533-1538 (2000). [11] S. Y. Yang, Y. D. Jeon, S. B. Lee, K. W. Paik, Solder reflow process induced residual warpage measurement and its influence on reliability of flip-chip electronic packages, Microelectronics Reliability, Vol. 46, 512-522 (2006). [12] D. Post, B. Han, P. IFju, High Sensitivity Moiré, Springer-Verlag, New York (1994). [13] B. Han, Thermal stresses in microelectronics subassemblies: quantitative characterization using photomechanics methods, Journal of Thermal Stresses, 583-613 (2003). [14] J. H. Park, C. K. Chung, K.W. Paik, and S. B. Lee, Effect of High Glass Transition Temperature on Reliability of Non-Conductive Film (NCF), Key Engineering Materials, Vols. 22, 517-520 (2006). [15] J. H. Lim, M. Han, J. Y. Lee, Y. Y. Earmme, S. B. Lee and S. Y. Im, A study on the thermomechanical behavior of semiconductor chips on thin silicon substrate, Journal of Mechanical Science and Technology, Vols. 22, 1483-1489 (2008). [16] S. Walwadkar, P. W. Farrell, L. E. Felton, and J. Cho, Effect of die-attach adhesives on the stress evolution in MEMS packaging, Proc. 36 th Int. Symp. Microeletron. (IMAPS 03), Boston, MA, 847-852 (2003). [17] S. Walwadkar, J. Cho, Evaluation of Die Stress in MEMS Packaging: Experimental and Theoretical Approaches, IEEE Transactions on Components and Packaging Technologies, Vol. 29, 735-742 (2006).