IME Technical Proposal. High Density FOWLP for Mobile Applications. 22 April High Density FOWLP Consortium Forum
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1 IME Technical Proposal High Density FOWLP for Mobile Applications 22 April 2014
2 Packaging driver for portable / mobile applications Key drivers/needs Smaller form-factor lower profile, substrate-less Higher performance higher speed, more I/O Higher integration multi chip integrated platform Low cost less processing step, low cost materials Packaging solutions options Stacked chip approach Side-by-side Current Conventional PoP, with TMV Substrate based side-by-side package Proposed package PoP with conventional FOWLP PoP with high density FO Thin core /coreless subst. with side-by-side die within package Multi-chip integrated on low cost high density WLP -No substrate -Lower profile -Short interconnect -Wafer level process -Lower cost Low cost, high density, integrated packaging solutions is needed
3 Price per pin(c$) High Density Multi-Chip Packaging : Cost Comparison Low Cost Flip-Chip BGA with substrate Conventional Fan-Out WLP 300mm, double RDL IME s High Density Fan-Out WLP 300mm, single RDL Cost Effective Because : Removing Flip-chip BGA substrate Minimizing No of RDL layers with Fine L/S (2um/2um) Integrating Multi-Chips with Wafer Level Processing High Density ,500 3,000 5,000 I/O counts
4 I/O Count Fan-Out Wafer-Level Technology: RDL size vs I/O count RDL- 1 st Fan-Out WLP (L/S: 2 µm/2 µm) Current Fan-Out WLP (L/S: >5 µm/5 µm) Mold-1 st Fan-Out WLP (L/S: <5 µm/5 µm) Total Silicon Die Area (mm 2 )
5 IME approach on High Density FOWLP Mold-first FOWLP RDL-first FOWLP Formation of RDL and UBM on Carrier Chip placement on molding tape on mold frame Sacrificial layer Carrier Wafer level molding Release from mold frame RDL and bumping processing Die-to-Wafer Bonding Wafer Molding Support Carrier Removal & bumping Singulation Target App Smart phone Package 15 mm x 15 mm, I/O ~1000, Thickness ~450 µm Benefits Existing infrastructure in FOWLP manufacturing Challenges Die shift, wafer warpage, RDL L/S < 10 µm/10 µm Singulation Target App Tablet Package 20 mm x 20 mm, I/O ~2000, Thickness ~450 µm Benefits Fine Pitch RDL with L/S 2 µm/2 µm Challenges Require support wafer
6 Test Vehicle Specs from Industry Feedback TV 1 TV 2 Mold-1 st FOWLP* RDL-1 st FOWLP* Specifications RDL L/S 5 µm/5 µm, 2 layers Package size : 15 mm x 15 mm Package I/O count: ~1000 No of chips: 2 chips /package Reliability : MSL3, TCOB 1000 Specifications RDL L/S 2 µm/2 µm, minimum 2 layers Package size : 20 mm x 20 mm Package I/O count: ~2000 No of chips: 3 chips / package Reliability: MSL3, TCOB 1000 Note: * Spec to be finalized after member s inputs
7 Chip-to-Mold non-planarity Mold tape and Pick & place process Spin-coated dielectric / laminated dielectric films for surface planarity Challenges & Proposed Solution Die shift causing misalignment Improved lithography techniques to compensate die shift Establish Design guidelines based on tool, material & process tolerance to minimize die shift Topography with multi-layer fine RDL PR and photo-dielectric with higher planarity and smaller via opening Cu density uniformity and incorporating Cu dummy structures Sacrificial and carrier removal process Reliability of large FOWLP Creep fatigue analysis and life prediction modeling Solder joint design enhancement Wafer warpage and moldable UF void Mold Compound material, process and design optimization Overmold and die thickness Molding void prediction by mold simulation and design optimization Routability & SI/PI design Routing of 2K-3K I/O and reduce RDL layer SI/PI and PDN design for multi-layer fine RDL Develop EDA methodology for PDK Challenge Proposed solution
8 Project objective Development of high density fan-out wafer level package with fine pitch multi-layer redistribution layer technology, including the following: Design of Test Vehicle High I/O FOWLP with fine RDL routability Electrical design, characterization, and PDK development Integrated high-q inductor and antenna Mold-first and RDL-first fabrication process flow Fabrication process development Lithography process development Photo-resist and dielectric materials Modeling and Characterization Die shift and moldable underfill void analysis and prediction Structural, material and process analysis for wafer warpage Board level reliability for large FOWLP 1/4 global model & submodel S1 Test vehicle assembly build, Reliability & FA Test vehicle fabrication and assembly build Package and board level reliability testing Failure mechanism analysis S2
9 IME High Density FOWLP Consortium IME 300 mm Fab, FOWLP engineering line Mold 1 st & RDL 1 st fabrication process flow Design guidelines for reliable FOWLP EDA Flow and Fan-Out PDK Demonstration test vehicle Reliability, FA OSAT Member s Inputs Product Roadmap Technology, Design requirements Performance, reliability requirements Advanced materials, process and equipments IDM/ Fabless Design, modeling and materials IME Equipment Fine RDL development High Density FOWLP Consortium Foundry Materials Member benefits 1. End-to-End solution for High Density, Low cost FOWLP for mobile/tablet applications 2. Fan-Out Technology platform for supply chain members to drive and co-develop next generation FOWLP 3. Extensive foreground data availability based on Member s requirements.
10 Deliverables Low cost multi chip, high I/O FOWLP package solution with 2 µm/2 µm RDL line/spacing Innovative wafer level fabrication for mold 1 st and RDL 1 st approach Test vehicle design SI/PI prediction with multi-layer RDL Parasitic RLC extraction for fine RDL EDA flow with PDK and Routing Analysis Integrated high-q inductor and antenna Fabrication: Mold 1 st & RDL 1 st Manufacturable process flow for fine L/S(2 µm/2 µm) RDL Litho process for die shift and topography compensation Identify material for carrier and adhesive of RDL first process Modeling and design solutions Design guideline to minimize die Shift < 3 µm, wafer warpage < 0.5 mm Solution for void free moldable underfill for RDL 1 st process Stress analysis of multi-layer fine RDL Design guidelines for reliable FOWLP of < 20 mm x 20 mm for TCOB 1/4 global model & submodel Assembly, reliability and FA Assembly flow for 20 mm x 20 mm FOWLP Package level reliability to meet MSL3 Board level reliability to meet TCOB of S cycles and JEDEC drop test Failure mechanism of board level reliability 1/8 global model & submodel PBGA solder joint distribution 2D model (2D) S2
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