Demonstration of 20µm Pitch Micro-vias by Excimer Laser Ablation in Ultra-thin Dry-film Polymer Dielectrics for Multi-layer RDL on Glass Interposers Yuya Suzuki, Jan Brune, Rolf Senczuk, Rainer Pätzel, Ryuta Furuya, Fuhan Liu, Venky Sundaram, Rao Tummala : Zeon Corporation, Research and Development Center, 1-2-1, Yako, Kawasaki-ku, Kawasaki-shi, Kanagawa, 210-9507, Japan : 3D Systems Packaging Research Center, Georgia Institute of Technology, 813 Ferst Drive, Atlanta, GA 30332, USA : Coherent LaserSystems GmbH & Co. KG Hans-Böckler-Str. 12 37079, Göttingen, Germany : Ushio Inc., 2-6-1 Otemachi, Chiyoda-ku, Tokyo 100-8150, Japan ysuzuki3@mail.gatech.edu Abstract This paper describes the first demonstration of 8-10µm diameter micro-vias at 20µm pitch in ultra-thin dry-film polymer dielectrics to achieve high-density and low-cost redistribution layers (RDL) on panel-based glass and organic interposers. A polymer dielectric dry-film, ZEONI F ZS10 0, at 10µm thickness was double side laminated on thin and low CTE glass and organic substrates. Micro-via arrays at 20µm pitch were formed by 248nm KrF excimer laser ablation using mask projection scanning, and metallized by a semi-additive process (SAP) using electroless and electrolytic copper plating, with no chemical-mechanical polishing to form fully filled via structures. Fully-filled micro-vias at 20um were achieved using processes scalable to large panels for low-cost and high-density 2.5D and 3D interposers. Introduction High-density interposers require high-density multi-layer re-distribution layers (RDL) with fine pitch wiring and fine pitch micro-vias at the same pitch as the on-chip I/Os. The onchip I/Os are projected to decrease to 20um pitch in the next few years. Silicon interposers, capable of wiring at this pitch, have been developed and commercialized using back-end of line (BEOL) processes with ultra-thin silicon dioxide or nitride dielectric layers using damascene/dual-damascene processes or liquid photo-sensitive dielectric materials [1, 2]. However, silicon interposers fabricated on 300 mm wafers suffer from high cost limiting their use in high-performance applications. Low-cost interposers on large and ultra-thin glass and organic panels have been demonstrated by Georgia Institute of Technology Packaging Research Center (Georgia Tech PRC) and its industry partners [3]. In this research, cost is projected as a function of panel size leading to as much as 8X cost reduction over 300 mm Si interposers [4]. This paper focuses on one of the most challenging aspects in panel-based multi-layer RDL, i.e., formation of small micro-vias and via to via registration from layer to layer, which is essential to escape route ultra-small bump I/O pitch. Current organic substrates utilize CO 2 lasers to form micro-vias of 40-50µm in diameter [5]. The limiting factors to further decrease via diameter are the long wavelength (10.2 and 10.6µm) and the large beam spot size of CO 2 lasers (60µm). Nd-YAG lasers have their characteristic wavelength at 1064nm with high pulse intensity, and can be converted to third harmonic wavelengths of 355nm or fourth harmonic wavelengths of 266nm, which are in the ultraviolet (UV) spectrum. These UV lasers can form smaller micro-vias due to the small size of the focused beam and shorter wavelength. Kyocera demonstrated high-density organic interposers with 20-25µm diameter micro-vias, using Nd-YAG lasers [6-8]. To achieve even smaller dimensions, new advances have been proposed and reported such as trench filling processes and thin-film processes. Atotech and Amkor have developed embedded trace technology called Via 2, to demonstrate 10µm wide conductors with 10µm diameter micro-vias with trench filling processes by excimer laser and copper plating processes respectively [9, 10]. However, trench filling processes require expensive chemical-mechanical polishing (CMP) after copper plating, leading to higher process cost. Shinko recently demonstrated 10µm diameter vias using liquid photosensitive thin film processes, adopted from wafer level processing [11], but this process is limited by the availability of highresolution photo-sensitive dielectric materials and their properties, and also by the high cost of wafer tools and singlesided processing. The Georgia Tech glass interposer RDL approach aims to extend semi-additive metallization processes on large panels for highest wiring density at low cost. The authors have previously reported the feasibility of 10µm diameter microvias in 10µm thin dry-film dielectric by excimer laser ablation [12]. Excimer laser ablation has several benefits in forming ultra-small micro-vias, such as high absorption by polymers, minimal thermal damage and compatibility with mask projection for mass via formation [13]. This paper goes beyond previously published work to form arrays of 8µm micro-vias at 20µm pitch. These ultra-small and fine pitch vias were fabricated by excimer laser mask projection ablation, followed by copper plating in a 5-10µm thick dryfilm polymer material, ZEONIF TM ZS100 (ZS100). The first section of this paper describes the properties of the low loss and low moisture absorbing, high-performance dielectric material used in this study. The second section describes the initial exploration of ultra-small micro-via formation by excimer laser ablation. In this section, excimer lasers with different characteristic wavelengths were investigated for fabricating micro-vias below 10µm diameter. After selecting the optimum wavelength, mask projection ablation of via arrays at 20µm pitch was performed using a 248nm excimer laser ablation process. The third section focuses on via metallization with electroless copper plating followed by electrolytic copper plating, to fabricate fully Cu-filled via structures. In the final section, the integration of ultra-small micro-vias with ultra-fine width conductor traces in 10µm 978-1-4799-8609-5/15/$31.00 2015 IEEE 922 2015 Electronic Components & Technology Conference
thin dry-film dielectrics is described to demonstrate the capability of the technology for panel based interposers. Ultra-thin Dry-film Dielectric Material To achieve fine pitch wiring and via structure, selection of dielectric materials is important. Dielectric materials for interposer RDL application need to satisfy many properties, such as electrical, thermal, mechanical and chemical properties. In this study, ZS100 (Zeon Corp.) was selected for meeting these requirements. Major properties of the material are summarized in Table 1 [14]. ZS100 has both a low dielectric constant (Dk) and a low electrical loss (Df), which are beneficial for high-speed transmission. Low moisture absorption of the material contributes to high-reliability of the package, especially when the package gets thinner. Table 1. Properties of ZS100. Properties Method Unit parameter Dk (10GHz) Cavity resonance - 3.0 Df (10GHz) Cavity resonance - 0.006 Tg TMA C 162 CTE TMA ppm/ C 25 Ra with Eless Optical profiler nm < 100 copper Peel strength 30µm thick N/cm > 7 copper Modulus Tensile test GPa 7 Water absorption 100 ºC, 1 hr in hot water wt% 0.2 Ultra-small Micro-via Formation by Excimer Laser Ablation Serial lasers such as CO 2 and Nd-YAG UV lasers are widely used in current package substrates for micro-via formation, but face several challenges in scaling to ultra-small via diameters below 10µm and pitches below 50µm. The first challenge is the power distribution within the laser beam, which induces thermal damage around vias. The second and more significant challenge for serial laser processes is their positional accuracy, limited to approximately ±5µm, which limits the layer-to-layer via registration multi-layer fine pitch RDL. Photosensitive dielectric materials have been developed and can achieve less than 10µm diameter vias with lithographic processes. However, such photosensitive via processes have challenges of limited availability of photosensitive dielectric materials, especially in dry-film format, and process scalability to large panels. In this paper, excimer laser ablation processes were explored to form ultrasmall RDL vias. The advantages of the excimer laser process are: 1) high absorption by polymer materials (Fig. 2) to generate chemical interactions for efficient material removal, 2) minimal thermal damage to the dielectric material, enabling clean and small vias, 3) the availability of projection tools for high through-put and large panel scaling, and 4) mask projection processes enabling higher positional accuracy between the vias. ZS100 is dry-film polymer dielectric material which is compatible with traditional wet-chemical processes. It should be noted that ZS100 has smooth interface (Ra<100nm) with copper deposited by electroless plating, which is highly beneficial to fine wiring formation due to less undercut of wiring structures. Fig. 1 shows fine pitch wiring on ZS100 by semi-additive process (SAP) [15]. Figure 2. Transmission characteristics of polymers [16]. Figure 1. Fine pitch 3µm routing structures on ZS100 Polymer Dielectric. Efficient light absorption of excimer laser irradiation into polymers can be achieved by matching the wavelength of the laser source to the peak absorption of the polymer. This minimizes thermal effects and damage around the vias during laser ablation. Three excimer laser sources with different characteristic wavelengths were used in this study to understand the effect of laser wavelength on via size resolution and via shape; ArF (193nm), KrF (248nm) and XeCl (308nm) from Coherent Laser Systems GmbH & Co. Fig. 3 shows the schematic of a typical excimer laser mask projection system for mass via formation. Since a mask projection process was used, the laser spot size was defined by the mask features, thus eliminating the need to focus the beam to less than 10µm spot size. For the initial assessment, 923
the mask opening size was set to form vias of 10µm diameter. The laser fluence (energy density) at the substrate was set to 1 mj/cm 2. The sample size was 3 inch x 3 inch with 10µm thick dry-film dielectric ZS100 laminated on 18µm thick blanket copper layers. Table 2 summarizes the formed via shapes with the three excimer lasers. As seen in the figure, both the 248nm and 308nm lasers created vias with good circularity and diameter close to the target of 10µm. In contrast, the vias ablated by the 193nm laser had distorted shapes and via diameters larger than 20µm. excimer laser source attanuator homoginizer Figure 3. Schematic of excimer laser systems. lens mask objective lens sample Table 2. Ultra-small vias formed at three excimer laser wavelengths (Target: 10µm). Figure 4. Etch rate of ZS100 at three different excimer laser wavelengths [17]. To investigate the excimer laser ablation of ultra-small micro-vias below 10µm, mask openings of 6µm were selected for laser trials. Table 3 shows the micrographs and profiles of the resulting vias. Consistent with the initial experiments discussed earlier, the samples processed with the 193nm laser had larger (12µm) and distorted via openings. In this case, samples processed with the 248nm and 308nm lasers also had slightly larger via size (7µm) than targeted, but the shape of the vias was circular without any distortion. However, the profile of the vias indicated that the vias formed by the 308nm laser were not fully open down to the copper pad. On the other hand, vias formed by the 248nm laser were open with a bottom diameter of 4µm. Based on these studies, the 248nm KrF excimer laser was selected for further optimization of the multi-layer RDL structures. Table 3. Ultra-small vias (top view and profile) formed by three different excimer lasers (Target: 6µm). The etch rate of the ZS100 polymer for each of the three laser wavelengths was evaluated and the results are shown in Fig. 4 [17]. It was revealed that the etch rate of ZS100 polymer at 193nm was much lower than that at 248nm and 308nm wavelengths. A potential reason for this lower etch rate is the lower ablation efficiency with the 193nm laser. ZS100 polymer has strong light absorption around 250-300nm wavelength and much weaker absorption at 200nm. The reduced absorption at 193nm in ZS100 can lead to the conversion of the incident energy into thermal damage, as indicated by the distorted via shape and larger than designed diameters. For fine pitch via formation, samples were prepared with ZS100 deposited on top of copper pads with 4-6µm copper thickness, fabricated using dry-film lithographic processes and semi-additive plating. 10µm Thick ZS100 dry-films were laminated on both sides of the panel by vacuum lamination at 100ºC. The surfaces of the copper pads were roughened by standard chemical treatments before the lamination process to enhance polymer-to-copper adhesion. The panels were hot pressed for 90 seconds at 3MPa pressure to planarize the surface of the dielectric. After lamination, the samples were thermally cured in an oven, by ramping up from room temperature to 180ºC, and holding at 180ºC for 30 minutes. Fig. 5 shows the stack-up of the sample used for fine pitch RDL via formation. The thickness of the polymer dielectric on the copper pads was 4-5µm because ZS100 flows during the 924
lamination process and the copper pads are fully embedded in the polymer layer. Via Metallization by Copper Plating Processes Since the ZS100 polymer dielectric is compatible with traditional wet-chemical based electroless copper seed layer processes, metallization of the micro-via arrays was carried out by electroless copper plating followed by electrolytic copper plating. The first step in the plating process was a chemical desmear, with an aqueous solution of permanganate and potassium hydroxide, to oxidize and remove scum inside the vias. After desmear, a 0.5µm thick copper seed layer was deposited with Pd-catalyzed electroless plating, followed by electrolytic plating to achieve the target copper thickness. For ultra-fine pitch interposers, complete filling of RDL vias during electrolytic copper plating is a critical requirement to form stacked-via structures for highest wiring density. Conformally plated vias force a staggered via design, effectively reducing routing density and limiting the pitch down scaling as shown in Fig. 7. Figure 5. Schematic of the RDL structure used for laser ablation of ultra-small vias. stacked staggered Via arrays with 20µm center-to-center pitch were created in this sample using 248nm excimer laser ablation through mask projection, forming hundreds of vias at one time. Fig. 6 shows the top view and cross section view of the vias after laser ablation. Via arrays with 8µm diameter at 20µm pitch were successfully fabricated. Figure 7. Stacked and staggered RDL via structures. Direct current electrolytic plating with a chemistry tailored for via filling, InPro A300 (Atotech GmbH), was performed at a constant current density of 0.5 A/dm 2 for 40 minutes. After the plating process, the sample was cross-sectioned to confirm complete via filling, as shown in Fig. 8. It was confirmed that the vias were fully filled, with a low surface copper thickness of 3-4µm. Since the thickness of copper on top was less than the typical thickness of the dry-film photo-resist (15-20µm) used for SAP, this technology can be applied to form a combination of fine pitch micro-vias and metal wiring in one step by SAP, without any chemical-mechanical polishing for surface copper thickness reduction, leading to low-cost interposers. Figure 6. Top view and cross-sectional view of 248nm excimer laser ablated via array at 20µm pitch. Figure 8. Cross section view of fully-filled vias at 20µm pitch. 925
Fine-pitch RDL Wiring and Vias by Semi-additive Processes Multi-layer RDL structures with fine pitch wiring and ultra-small vias were then fabricated by laminating ZS100 thin dry-films on both sides of glass and organic core materials and applying excimer laser via ablation and SAP metallization. The process flow is listed below and shown in Fig. 9: 1) Lamination of 10µm thick ZS100 on core materials 2) Drilling of micro-vias (10µm diameter, 50µm pitch) by 248nm excimer laser 3) Plating electroless copper seed layer on ZS100 4) Applying photo lithography for patterning [15µm thick dry-film negative photo resist and UX- 44101 (Ushio Inc.) were used for the process] 5) Plating electrolytic copper (1.0 A/dm 2, 40 min) to fill micro-vias and to form lithographic patterns 6) Stripping photo resist 7) Removing copper seed layer by micro-etching Core 1 2 3 4 Figure 9. SAP sequences of the samples with fine pitch micro-vias and wirings. In this study, 3 inch x 3 inch size panels were used, and Fig. 10 shows the cross section of the fabricated samples. Vias with 10µm diameter were completely filled by plated copper and 3.5µm conductor widths with 4.5µm spacing and 7µm copper thickness were successfully fabricated. 5 6 7 Figure 10. Cross section of the filled via (10µm in diameter) and fine pitch wiring (3.5µm width line and 4.5µm space). Conclusions This paper presents the first demonstration of 8µm diameter micro-vias at 20µm I/O pitch fabricated with excimer laser ablation in ultra-thin, dry-film polymer dielectrics. Several wavelengths of excimer lasers were investigated in this study for via size and shape. It was found that 248nm excimer lasers are the best to form the smallest vias, less than 10µm with excellent circularity. After excimer laser processing, standard electroless and electrolytic copper plating processes were utilized to form fully-filled vias. These laser via advances coupled to semi-additive plating processes, ultra-thin dry-film dielectric such as ZS100 and excimer laser mask projection ablation resulted in integrated test-vehicles to successfully demonstrate fine pitch multi-layer RDL structures with no CMP. These studies are expected to enable high-density, panel-based glass interposers capable of 20µm I/O pitch at much lower cost than 2.5D silicon interposers. Acknowledgments This collaborative research is part of the Low-cost Glass Interposer and Package (LGIP) consortium at Georgia Tech PRC. The authors would like to thank to all the member companies for their financial and technical support. References [1] L. Chenting, L. Clevenger, F. Schnabel, J. Fen Fen, and D. Dobuzinski, "Planarization of dual-damascene postmetal-cmp structures," in Interconnect Technology, 1999. IEEE International Conference, 1999, pp. 86-88. [2] H. Y. Li, H. M. Chua, F. X. Che, A. D. Trigg, K. H. Teo, and S. Gao, "Redistribution layer (RDL) process development and improvement for 3D interposer," in Electronics Packaging Technology Conference (EPTC), 2011 IEEE 13th, 2011, pp. 341-344. [3] R. R. Tummala, "2.5D Interposers; Organics vs. Silicon vs. Glass," Chip Scale Review, vol. 17, pp. 18-19, 2013. [4] E. D. Blackshear, M. Cases, E. Klink, S. R. Engle, R. S. Malfatt, D. N. de Araujo, et al., "The evolution of buildup package technology and its design challenges," Ibm Journal of Research and Development, vol. 49, pp. 641-661, Jul-Sep 2005. 926
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