Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip

Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip SzePei Lim (Presenter), Jason Chou, Maria Durham, and Dr. Andy Mackie Indium Corporation 1

Outline of Presentation Roadmaps and challenges for flip-chip assembly Characteristics of ultralow residue fluxes Rheology Viscosity Residue level Thermogravimetric analysis (TGA) Solderability Wetting Holding die in place Movement during reflow (MDR) Compatibility with MUF/CUF

Semiconductor Roadmap: Packaging Challenges in 2010s Many challenges impact flip-chip assembly Taken from: International Technology Roadmap for Semiconductors (ITRS) 2013 http://www.itrs.net/links/2013itrs/2013tablesummaries/2013ap._summarytable.pdf

Roadmap Challenges: Mobile Devices Old and current solder bump technology Single Chip Package Technology Requirements for Mobile Devices Year of Mass production = 2014 2016 2018 2020 Units Transistor (T1) MPU 1/2 Physical Gate Length after etch 18 15 13 11 nm Wafer Die thickness - Extremely thin packages (minimum) 10 5 5 5 microns Cost per I/O for OSAT production (minimum cost) 0.36 0.34 0.32 0.3 (USD$/pin/100) Chip Area 100 100 100 100 mm^2 Mobile Device Package pin count (maximum) 207-1100 218-1150 252-1150 278-1150 number of I/O Packages Package profile or thickness (minimum) 0.22-0.40 0.20-0.35 0.19-0.35 0.19-0.35 mm Junction temperature - Tj (maximum) 105 105 105 105 degc Operating temperature - ambient (maximum) 45 45 45 45 degc Critical points: - Thinner substrates - Thinner die - Finer pitch - Lower cost More delicate packages and worse yield loss in assembly Table data from: International Technology Roadmap for Semiconductors (ITRS) 2012/13 http://www.itrs.net/.reports.html

Substrate Warping Challenge ITRS package thickness shrinkage calls for thinner substrates and thinner die Thinner packages warp more Taken from: K. Lee, "Mobile platform packaging challenges," inemi workshop, Nagoya, Japan 2009, pp. 9 and 10

The End of Flip-Chip Flux Cleaning? Package Design Changes Pitch shrinking to 100microns and below Die-substrate clearance down to 60microns and below Substrates thinner and subject to warping Causing Flux Cleaning Challenges: Finer pitch makes it difficult to completely remove flux residues: Conductive residues may lead to ECM Can block flow of CUF and MUF leading to voiding Can interfere with CUF and MUF adhesion causing delamination Cleaning process: Increases substrate warpage after reflow and Dendrites caused by electrochemical migration (ECM) of poorly-cleaned flux Move to ultralow before underfill, leading to cracked solder jointsresidue no-clean flux Adds significant costs

Ultralow Residue (ULR) Flip-Chip Flux Characteristics Rheology Viscosity Residue level Thermogravimetric analysis (TGA) Solderability Wetting Holding die in place Movement during reflow (MDR) Compatibility with MUF/CUF

Viscosity Test Method Equipment: Brookfield Cone and Plate Model: DV3THBCB Parameters: Spindle: CP-51 Temperature: 25 C RPM s: 20 RPM Viscosity is just one aspect of rheology

Comparative Viscosities as a Function of Time Viscosity controls dipping and die-holding during reflow

Importance of Rheology for Fine-Pitch Dipping Process Rheology (viscosity / tack) must be tuned to the process needs, especially for fine pitch, without sacrificing the ability to hold die in place: - High viscosity can lead to bridging - Low viscosity can lead to flux wicking and die-surface contamination Flux rheology and exact needs will vary with the flipchip design

TGA Test Method Equipment: TA Instruments SDT Q600 Parameters: Method: Ramp 10 C/min Sample size: 10mg ± 1mg Nitrogen gas: 100ml/min TGA is an indicator of relative flux residue levels

TGA: Ultralow Residue (ULR) and Standard Residue Flux Types TGA is unrepresentative of real situations for flux. The exposed surface area is much smaller in TGA than for real flip-chip applications. In reality, flip-chip fluxes will have lower residue levels than shown here. Standard reflow peak maximum Standard Flux NC-826 NC-26-A ULR fluxes allow underfill to flow without blockage and voiding

Wetting Test Method 1. Print flux onto metallized surface 2. Place spheres onto flux deposit 3. Reflow in nitrogen 4. Measure reflowed height deposit 5. Calculate percent spread

Wetting Test Comparison Wetting must be controlled, and balance between - Excessive: leading to bridging - Poor: leading to non-wetting or weak solder joints with voids GOOD NC-26-A and NC-826 balance wetting onto OSP

Wetting: Ultralow Residue Fluxes NC-26-A Competitor watersoluble (WS) flux NC-26-A shows zero voiding and zero bridging on OSP Excessive solderability

MDR Test Method Correlates with die-skew Measure movement of reflowed deposit from original position of sphere Calculate amount of movement during reflow For more details, contact Indium Corporation s Technical group Good wetting Good (Low) MDR Moderate wetting Moderate MDR Uneven wetting Poor (High) MDR Die skew Good Bad

Movement During Reflow (MDR) GOOD Good, but residue too high NC-26-A and NC-826 are comparable to WS flux for die holding

CUF Compatibility: Test Method Deposit flux on substrate 1. Using FC to dip transfer flux onto Cu leadframe 2. Spread a thin film of flux on glass slide Heat on hot plate @240 o C for 10-15sec Deposit underfill Cure underfill at recommended condition Post reflow treatment Control (no baking) Baking at 180 o C for 1hr Baking at 180 o C for 3hr 10 temp cycle at 125 o C/65 o C (dwell time 1.5min) Delamination evaluation 1. Visual and Scotch tape for samples on Cu leadframe 2. Cross-section SEM for sample on glass slide

SEM X-section Check on Flux Thin-Film Before thermal cycle After thermal cycle No baking No baking Cut here Bake 180 o C 1hr Bake 180 o C 1hr NC-26-A has good compatibility and no delamination Bake 180 o C 3hr Bake 180 o C 3hr

Flip-Chip Flux: Criteria for Dipping / Mass Reflow Assembly Processes Flip-Chip Performance Criterion Solder joint yield Excessive CUF epoxy bleedout CUF and MUF voiding Potential for flux/underfill (CUF and MUF) delamination Assembly process cost Pick up small die from flux dipping tray Hold large die in place for mass reflow Flux bridging with fine pitch bumps / copper pillar Flux contaminating die surface after reflow Solder joint cracking: between reflow and underfilling Suited for low clearances (<60um) and <100um pitch copper pillar Standard Residue Flux No-Clean ULR Flip-Chip Flux Known problem Area of concern Known solution to problem Near Zero Residue (NZR) Flux** **Designed for TCB Water Wash Water Soluble Flux (perfectly cleaned) Indium ultralow residue fluxes meet multiple needs for flip-chip assembly

ULR Flip-Chip Flux Product-Specific Attributes High-yield soldering to copper OSP Designed for copper-pillar Dipping with minimal bridging No wetting onto die surface Holds large die in place during reflow Customer-proven residue compatibility with CUF and MUF without delamination Indium ultralow residue fluxes are customer-proven in copper pillar flip-chip processes

Portfolio of No-Clean Semiconductor Fluxes Indium Corporation Semiconductor Grade Flux Materials Aspect Condition Flip-Chip Flux NC- Flip-Chip Flux NC- Flip-Chip Flux NC- 704-24-8 Developmental Developmental 699-34-1 749-030A** 510 26-A 826 Material Material Target Final Device Chip type and usage MEMS / flip-chip general use Flip-chip Flip-chip Flip-Chip Flip-Chip Flip-Chip MEMS MEMS Primary Application Usage in chip assembly MEMS and <60µm Flip-chip and pitch standard flipchichip copper-pillar flip- Copper pillar <= 100µm pitch > 100µm pitch Copper pillar <= 100µm pitch with TCB Copper pillar <= 100µm pitch with TCB Copper pillar <= 100µm pitch with TCB <1mm2 devices with 4-8 I/Os 60-80µm diam >1mm2 devices with 8-24 I/Os 60-80µm diam Reflow Type <100ppm oxygen in nitrogen is standard for inert reflow Mass reflow Mass reflow / TCB Mass reflow TCB TCB Mass reflow Mass reflow / TCB Mass reflow Method of Application Usage in tool Dipping / printing Dipping Dipping Spraying Spraying Dipping Dipping Dipping Residue Level Varies with reflow profile / ULR ULR LR NZR NZR ULR NZR ULR die size and clearance Solder Alloy Compatibility Eutectic (SnPb37) and Pbfree (tin/silver) Both Tin/silver Tin/silver Tin/silver Tin/silver Tin/silver Tin/silver Tin/silver Surface Issues/incompatibilities - - - - Rapid OSP removal Target for OSP - - Metallizations removal Polymer compatibility Underfill types Unknown Unknown Compatible with majority of CUF and MUF Still to be proven. Reflow / flux "cure" process will govern compatibility Still to be proven. Reflow / flux "cure" process will govern compatibility Still to be proven. Likely to be excellent. Compatible with MUF for rapid (<5sec / unit) assembly (Target) Compatible with majority of CUF and MUF (Target) Halogen-free Ion Chromatography Yes Yes Yes Yes Yes (target) Yes (target) Yes Yes SIR Testing IPC-J-STD-004A Pass Pass Pass Pass Pass (target) Pass (target) Pass Pass Status of Flux Volume Volume Scaled-up and Lab phase only - - Volume Scaling up Manufacturing manufacturing manufacturing ramping manufacturing Customer Approval Yes: multiple Yes Yes Yes - - Yes Yes Customer Volume Usage Yes: multiple Small volume for specific devices Ramping Not yet - - Small volume for specific devices Ramping (+) Conforms to IEC 61249-2-21 Portfolio of ultralow residue fluxes can meet multiple needs for MEMS and flipchip assembly

Semiconductor Fluxes: Major Commercial Usage Q3 2014

Other Semiconductor Assembly Materials Fluxes: Flip-chip fluxes Water-soluble Halogenated / halogen-free Spraying/jetting/dipping Ball-attach fluxes Waferbumping (bump-fusion fluxes) Spheres: High-reliability, low silver solder spheres SACM Solder pastes: High temperature, Pb-free solder paste technology BiAgX Type 6, 7 substrate and wafer bumping solder pastes Thermal interface materials: Metal TIM 1,2 Liquid metals

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