Flip chip bumping technology Status and update

Nuclear Instruments and Methods in Physics Research A 565 (2006) 290 295 www.elsevier.com/locate/nima Flip chip bumping technology Status and update M. Juergen Wolf, Gunter Engelmann, Lothar Dietrich, Herbert Reichl Fraunhofer IZM, Gustav-Meyer-Allee 25, 13355 Berlin, Germany Available online 13 June 2006 Abstract Flip chip technology is a key driver for new complex system architectures and high-density packaging, e.g. sensor or pixel devices. Bumped wafers/dice as key elements become very important in terms of general availability at low cost, high yield and quality level. Today, different materials, e.g. Au, Ni, AuSn, SnAg, SnAgCu, SnCu, etc., are used for flip chip interconnects and different bumping approaches are available. Electroplating is the technology of choice for high-yield wafer bumping for small bump sizes and pitches. Leadfree solder bumps require an increase in knowledge in the field of under bump metallization (UBM) and the interaction of bump and substrate metallization, the formation and growth of intermetallic compounds (IMCs) during liquid- and solid-phase reactions. Results of a new bi-layer UBM of Ni Cu which is especially designed for small-sized lead-free solder bumps will be discussed. r 2006 Elsevier B.V. All rights reserved. Keywords: Packaging; Flip chip; Bumping; Electroplating 1. Introduction Assembly and packaging technology continue to change rapidly. In the last decade packaging has changed from simple single-die packaging to a complex system integration technology which represents an integral prerequisite for the manufacturing of new electronic products. Assembly and packaging needs are driven by market application requirements as well as silicon technology. Cost will drive technology trade-offs for all market segments. System in Package (SiP) technology has rapidly evolved from specialty technology used in a very narrow set of markets to a broad market base. The primary driver for SiP technology has been the need for more compact, more highly integrated electronics. Permanently growing integration density and increasing complexity of integrated circuits lead to further reduced I/O pitches. A general roadmap, forecasted by ITRS [1], of selected parameter for devices (memory, mp and ASICs) regarding I/O counts, pitch frequency and power dissipation is presented in Table 1. The selection of the interconnection technology for a specific application depends on topological, electrical and Corresponding author. E-mail address: juergen.wolf@izm.fraunhofer.de (M. Juergen Wolf). thermal considerations as well as reliability requirements, manufacturing and testing issues. The application of chip and wire bonding, which is the most commonly used interconnection technology today, is limited in terms of high I/O number, pad configurations and smallest pitches. Flip chip (FC) technology offers several advantages especially for high dense interconnects because the whole chip surface may be used for a large number of I/O pads in area array configuration. Shortest interconnection lengths result in excellent electrical performance of interconnects as well. 2. Flip chip and bumping technologies FC technology in contrast to chip and wire needs an additional process on wafer and/or substrate level the bumping [3 5]. Depending on the selected joining process different bump configurations are used (Fig. 1). An overview about currently used bump metallization for different applications is given in Table 2. For the metallization of the I/O pads, different bumping techniques have been developed. The most important are evaporation, electroplating, mechanical stud bumping and solder paste printing on wettable metallization like Ni/Au, as well as solder dispensing, immersion and solder transfer 0168-9002/$ - see front matter r 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2006.05.046

M. Juergen Wolf et al. / Nuclear Instruments and Methods in Physics Research A 565 (2006) 290 295 291 Table 1 Forecasted evolution of packaging parameter [1] Year of prodution technology 2004 2007 2010 2013 2016 Technology node hp90 hp65 hp45 hp32 hp22 Chip pad pitch (mm) Wire bond ball 40 30 25 25 25 Wire bond wedge 30 25 20 20 20 Area array flip clip (cost performance, high performance) 150 120 100 90 80 Peripheral flip chip (hand held, low cost, harsh) 60 30 20 20 15 Package pincount maximum Low cost 122 500 160 660 208 777 270 1011 351 1314 Cost performance (microprocessor/controller) 500 1600 600 2140 780 2782 1014 3616 1318 4702 High performance (microprocessor/controller) 3000 4000 4009 5335 7042 Harsh 500 660 642 812 1074 Chip frequency (MHz) Chip to board (off-chip) speed (high performance, for peripheral buses) 2500 4883 9536 48626 36379 On-chip (high performance) 3990 6740 12,000 19,000 29,000 Allowed maximum power (W) High performance with heatsink 158 189 218 251 288 Cost performance 84 104 120 138 158 Battery (low cost/hand-held) 2.2 2.5 2.8 3.0 3.0 process, the allowed joining temperature, the melting point of the solder, the integrity of the interfaces between the bump and the adjoining bond pad metallization, the bumping process compatibility and reliability requirements. To preserve the structural integrity of all assembly parts, the temperature hierarchy in the package processing must be taken into consideration as well. All bump variations listed above are well established on 4 00 8 00 wafers at Fraunhofer IZM and available for specific customer requests. Fig. 1. Overview of FC approaches. techniques. Each technique meets different requirement in terms of bump sizes, pitches, metallization, etc. Solder paste printing meets the requirement regarding low cost but this process is limited to minimal bump pitches of 150 mm today. Wafer bumping by electroplating however, has the largest potential for realizing highest I/O densities with a pitch range from 200 to 25 mm. It is particularly suited for high volume production of bumped wafers at a highquality standard. As the value of wafers increases, the relatively high processing costs are less and less perceptible. The realization of bumps using electroplating can be divided into fundamental process steps, which are sputtering of the plating base, photoresist patterning, electroplating, differential etching, and, if required, a final solder reflow as shown in Fig. 2. The selection of the suited bump metal and under bump metallization (UBM) depends mainly on the assembly 3. Bumping process by electroplating Typically, circuit device wafers have aluminum alloy pads and an inorganic (e.g. SiO 2,Si 3 N 4, SiON) or organic passivation opened over the pads. InP or GaAs semiconductors for photonic and RF applications are using gold pads. By an initial sputter-etching step, the wafer surface is cleaned of contamination and metal oxides. After backsputtering an adhesion layer of Ti:W(N) with a thickness of 100 230 nm is sputtered on the whole wafer, followed by a second layer of either 300 nm Cu or 200 nm Au as a plating base. The specific addition of nitrogen (N 2 ) during deposit of Ti (5 wt%) W (95 wt%) enhances the diffusion-barrier property. A Ti:W(N)/Au bump structure on aluminum pads has shown no degradation after annealing at 400 1C (1 h). With optimized sputter conditions, a low-stress deposition and a good homogeneity of layer thickness are achieved without any damage of CMOS structures [2]. Spin coating is used to deposit the high-viscous photoresist onto the wafer in the desired layer thickness.

292 ARTICLE IN PRESS M. Juergen Wolf et al. / Nuclear Instruments and Methods in Physics Research A 565 (2006) 290 295 Table 2 Overview of different FC bump constructions Bump Wafer Wafer size UBM Bumping technology Application Au Si GaAs 4 00 8 00 3 00 6 00 Ti:W/Au Al/Au Au/Au Electroplating stud TAB/TC FC adhesive Opto RF consumer, display Electroless Ni Si 4 00 8 00 (12 00 ) Ni/Au Electroplating and immersion Au/solder FC soldering FC adhesive Consumer, Smart card priting AuSn GaAs InP Si 3 00 6 00 2 00 3 00 4 00 6 00 8 00 Ti:W/Au Electroplating FC soldering Opto RF MEMS, medical PbSn 60 Si 4 00 8 00 12 00 Ti:W/Cu/ep-Cu electroless Ni/Au Ni:V/Cu Cr/Cu Electroplating printing printing, ECD FC soldering Memory, RF telecommunication sensors, MEMS Ti/Ni PbSn 5 Si 6 00 8 00 Cr/Cu Ti:W/CU Evaporation ECD FC soldering Automotive, processor harsh AgSn (Cu) Si GaAs 4 00 8 00 12 00 3 00 6 00 Ti:W/Cu/ep-Cu Ti/NiV CrCu, Electroplating printing FC soldering Memory, telecommunication CuSn Si 8 00 12 00 Ti:W/Cu/ep-Cu Ti/NiV Electroplating printing FC soldering Memory, telecommunication Fig. 2. Bumping process flow using electroplating. Layers of more than 45 mm can be realized by multi-spin coating with a good thickness homogeneity on all standard wafer sizes (4 00 8 00 ). The used positive resist (AZ series) system shows a high transparency in the near UV spectrum, therefore a high depth-to-width aspect ratio and steep slopes of the generated structures are possible even in thick films. To dry the spin-coated resist film it is prebaked before printing. Then the wafer is aligned and exposed in the pad regions, which later will be covered by the bump structures. The exposed areas dissolve during the development in an alkaline fluid and the resist pattern appears. A final postbake is made to stabilize the photoresist for the following electroplating process. Especially for fine pitch

M. Juergen Wolf et al. / Nuclear Instruments and Methods in Physics Research A 565 (2006) 290 295 293 bumping, a fine-tuning of the exposing, developing, and baking procedures is inevitable to get a high lithographic yield. Besides the resist patterning, another important aspect for the suitability of the photoresist system for bumping is an easy removal after the metal deposition. The bump metallurgy must not be corroded by the remover, and mechanical damage must absolutely not occur due to a swelling effect of the resist, which is not given by all resist systems. Today a number of commercial electroplating baths for different metals are available. The bath chemistry must be compatible to the photoresist system and should be insensitive to out-bleeding. Exceptionally cleaned makeup ingredients ensure deposits with a high purity and consequently well-defined electrical and mechanical properties. For solder bumping, a low co-deposition rate of organics is required to guarantee a low volume of outgassing during the reflow and bonding process. For this reason, relatively matt depositing electrolytes with a small amount of organic additives are preferred. Furthermore, the deposits have to show a well-defined bump shape and solder-alloy composition, low internal stress, non-porosity, as well as a negligible number of defects caused by dendrite formation, pittings or particle encapsulation. These attributes as a whole have to be adjusted by a suitable combination of all relevant deposition parameters like concentration of electrolyte components, current density and agitation strength. In particular cases, the optimization depends on the specific pattern layout as well. Figs. 3 and 4 show plated Au bumps and fine pitch solder bumps. Fig. 4. PbSn60 solder bumps on ATLAS read out circuit (25 mm size, 50 mm pitch). 4. Bump reliability The demand for Pb-free and high-density FC interconnection technology is growing rapidly. Lead-free FC solder joints require an increase in knowledge in the field of UBMs, solder materials, board metallization as well as in the interactions between these elements. Common UBMs Fig. 5. BSE images of bumps with UBM 1 (1.5 mm Ni/150 nm Cu) and UBM 2 (1.5 mm Ni/500 nm Cu) after solid-phase reaction with Sn solder at 150 1C/1000 h. Fig. 3. Fine pitch Au-bumps. have been tested with various lead-free solder systems to study the formation and growth of intermetallic compounds (IMCs) during liquid and solid-phase reactions [3]. Due to a high rate of IMC formation related to the consumption of the UBM these UBMs are often not recommended for lead-free applications at elevated tem-

294 ARTICLE IN PRESS M. Juergen Wolf et al. / Nuclear Instruments and Methods in Physics Research A 565 (2006) 290 295 perature (150 1C) for devices with small solder joints. For such applications it would be advantageous to use UBMs showing a limited formation of IMCs at the interface UBM/solder to maintain the plasticity of the interconnect and the adhesion of the UBM to the diffusion barrier. A number of different UBM solder configurations (e.g. Cu PbSb60, Cu SnAg, NiV/Cu SnAg, Cr Cu/Cu SnAg, TiW/NiV) are investigated and results are reported in Refs. [4,5]. Fig. 6. FIB images of the interface UBM/solder with UBM 1 and UBM 2 after 90 s liquid-phase reaction at 250 1C. 5. Cu Ni bi-layer UBM for high reliable lead-free solder joints There are several possibilities to slow down the process of formation of IMCs occurring during liquid- and solidphase reactions between UBM and lead-free solder. Materials showing slower formation of IMCs than others may be chosen as UBM as it is true for Ni in comparison to Cu. In this case the process of UBM consumption is slowed down but it is not stopped. The problem that a Ni UBM tends to detach easily from the diffusion barrier layer after its total consumption due to IMC growth remains. The lifetime of a single-layer UBM (e.g. Cu) can be prolonged by increasing the thickness of the UBM. It is also possible to use alloy solders slowing down the UBM consumption as well. As the control of a multi-component bath for electroplating is difficult it is not opportune to electrodeposit Sn Ag Cu alloys as solder material. Fig. 7. SE images of the interface UBM/solder of UBM 1 and 2 after liquid-phase reaction at 250 1C with Sn in comparison to an electrodeposited Ni UBM with SnCu solder.

M. Juergen Wolf et al. / Nuclear Instruments and Methods in Physics Research A 565 (2006) 290 295 295 A bi-layer Ni/Cu UBM for small-sized lead-free solderbumps was investigated to stabilize the formation of IMC and to increase the bump reliability. Fig. 5 shows cross-sections prepared from bumps after the chips had undergone thermal aging at 150 1C (1000 h) with UBM 1 (1.5 mm Ni/150 nm Cu) and UBM 2 (1.5 mm Ni/500 nm Cu). For UBM 1 a consumption of UBM was observed during solid-phase reaction connected to a growth of interfacial IMCs between UBM and solder. For UBM 2 no changes were observed at the interface UBM/solder. Fig. 6 shows both UBMs after liquid-phase reaction at 250 1C for 90 s (reflow conditions). Using UBM 1 a (Ni,Cu) 3 Sn 4 layer is formed in the early state of liquidphase reaction. Solder is in contact to the Ni layer initiating and allowing further growth of a Ni 3 Sn 4 or (Ni,Cu) 3 Sn 4 formation. In the case of UBM 2 a thin (Cu,Ni) 6 Sn 5 layer covering the Ni layer is suitable to prevent the formation of Ni 3 Sn 4. A closed layer of (Cu,Ni) 6 Sn 5 is formed and prevents the consumption of the Ni layer of the bi-layer UBM. The Cu layer serves as sacrificial layer forming (Cu,Ni) 6 Sn 5 IMCs during reflow. This (Cu,Ni) 6 Sn 5 IMC layer is suitable to block interdiffusion between Ni and the solder during solid-state aging. Liquid-phase reaction for both UBM constructions compared to Ni were also studied up to total duration of 900 s (Fig. 7). A 1.5 mm thick electrodeposited Ni UBM is already consumed after 900 s and spalls into the solder. With UBM 1 the appearance and growth of Ni 3 Sn 4 IMCs were observed. UBM 2 withstands multiple reflow up to a total time of 900 s where only a slight degradation of the UBM becomes visible [6,7]. 6. Summary Electroplating for bump formation is the technology of choice for high-density FC applications with a high yield. With this technology different solder compositions and metal structures can be realized. Compared to solder paste printing, pitches of approx. 150 mm (state-of-the-art), bump sizes of 10 mm diameter and 20 mm pitch are currently seen as a limitation for electroplating. Sensitive areas on device wafers (e.g. sensors) can be protected by a temporary layer during bump processing. Small-sized solder bumps (diametero20 mm) need an improved UBM construction. For lead-free solders (SnAg, SnCu, Sn) an UBM stabilization effect can be achieved by an adjusted bi-layer UBM of Ni Cu. Lead-free bumps with AuSn are well suited for flux-free FC assembly especially for photonic and RF applications [8]. This process can be easily implemented with electroplating as well. High stand-off bump construction (e.g. pillar bumps) at fine pitch can only be realized by electroplating. New bump construction (e.g. 3-axes compliant bumps) and nano-interconnects are under development for TCE matching chip-substrate and lowtemperature assembly. Acknowledgements The authors would like to thank the team members of the department High Density Interconnect & Wafer Level Packaging of Fraunhofer IZM. Special thanks to C. Jurenka, I. Kuna, M. Lutz, N. Ju rgensen, K. Samulewicza J. Ro der for support in wafer processing. References [1] www.itrs.org, TWG A&P. [2] L. Dietrich, et al., Wafer bumping technique using electroplating for high-dense chip packaging, in: Third Internat Symposium on Electronic Packaging Technology (ISEPT 98), Beijing, China, 17 20, August 1998. [3] M. Li, et al., J. Mater. Res. 17 (7) (2002) 1612. [4] Se-Y. Jang, M.J. Wolf, W.S. Kwon, K.W. Paik, UBM (under bump metallization study) for Pb-free electroplating bumping: interface reaction and electromigration, in: Proceedings of ECTC 2002. [5] M.J. Wolf, et al., Micromater. Nanomater. 3 (2004) 234. [6] C. Jurenka, G. Engelmann, M.J. Wolf, Effect of the Cu thickness on the stability of a Ni/Cu bilayer UBM of lead free microbumps, in: Proceedings of ECTC 2005, pp. 89 93. [7] G. Engelmann, M.J. Wolf, Microsystem Technol. (2005) 207. [8] M. Hutter, et al., Assembly and reliability of flip chip solder joints using miniaturized Au/Sn bumps, in: Proceedings of ECTC 2004, pp. 49 57.