Copper Wire Bonding Technology and Challenges By Dr Roger Joseph Stierman Date: 21 & 22 October 2013 Venue: SHRDC, Shah Alam, Selangor *2 days training package RM 3,000 per pax [*] * includes hotel accommodation at Carlton Holidays Shah Alam Email: halim@shrdc.org.my Tel: 03-5513-3560 (Ext 66) Co-organized by Semitracks Inc.
OVERVIEW The drive to reduce costs in semiconductor and integrated circuits remains a key challenge for the industry. As a result, the industry is pushing to use copper wires and copper pillar bumping in an increasing array of applications. Copper wire also has the advantage of low resistivity. However, copper is not without problems, such as a high coefficient of thermal expansion, intermetallic formation, and oxidation problems, just to name a few. This has created a number of challenges related to the bonding and packaging of these components. Copper (Cu) Wire Bonding Technology and Challenges is a 2-day course that offers detailed instruction on the technology issues associated with copper wire and copper bonding. We place special emphasis on current issues like Copper bond formation, bumping, and tools for package analysis. This course presents metallurgical principles that are key to the understanding and use of Copper wire bonding in semiconductor (IC) packaging assembly and reliability. Phase diagrams that are pertinent to the solid solutions, phases, and intermetallic compounds (IMC) formed in the Copper wire bond process will be presented. Copper wire Oxidation/reduction potentials will be discussed, as the first steps toward resolving corrosion resistance issues, either in package design or failure analysis. Modifications to common failure analysis methods will likewise be highlighted. This course is a must for every manager, engineer, and technician working in semiconductor packaging, using semiconductor components in high performance applications or non-standard packaging configurations, or supplying packaging tools to the industry. By focusing on current issues in copper technology, participants will learn why advances in the industry are occurring along certain lines and not others. Our instructors work hard to explain semiconductor packaging without delving heavily into the complex physics and materials science that normally accompany this discipline. COURSE OBJECTIVES 1. How to read & interpret phase diagrams important to Copper (Cu) wire bonding technolgy 2. Guidelines to modify current failure analysis techniques for Copper technology. 3. Copper (Cu) Technolgy Process control: Prediction and identification of potential corrosion products from environmentaltesting, field failures, and how to interpret failure analysis results 4. Methods to apply these principles to process and material changes toward robust Copper (Cu) wire bonding processes. 5. Participants will gain methods to apply these principles to process and material changes to lower cost and produce increased reliability for Copper (Cu) Technolgy. 6. Participants will be able to make decisions about how to construct and evaluate new Copper (Cu) packaging designs and technologies. 7. The participant will see several case studies associated with copper (Cu) wire bonding. 2
COURSE OUTLINE I. Basics of Al, Au, and Cu a. Melting & Solidification b. Phase Diagrams & Intermetallic Compounds c. Oxidation & Corrosion d. Diffusion & Welding e. Binary/Ternary Phase Diagrams and How to Interpret II. Important Cu Alloy Systems (Intermetallic Growth Rates & Phases) a. Al-Au, b. Al-Cu, c. Cu-Sn, d. Sn-Ag-Cu, e. Pd-Cu on Al III. IC Bonding a. Free Air Ball Formation b. Wire Bonding (i. Loop Design, ii. Loop Parameters) c. Flip-Chip Soldering (i. Free air balls d. Cu-Pillar Bump e. Bond Pad Issues (i. Metal Layers, ii. Via Design) IV. Package Mounting Soldering a. Pad & Lead Cleanliness (i. Surface Contamination Test methods) b. Pad & Lead Finishes: IMC formation (i. Cu/Cu, ii. Cu/Ni) c. Interactions with molding compound V. Copper Wire Reliability and Environmental Tests a. FIT rates b. Arrhenius Equation c. Moisture tests (i. HAST Testing 2. Copper Oxidation, 3. Degradation, ii. Voltage-Biased Tests ) iii. Autoclave d. Thermomechanical tests (i. Temperature Cycling, ii. Flex Tests/Drop Tests) e. Mechanical and Electrical Tests f. Electromigration g. Special Cases: Failure Analysis Methodology (i. Deprocessing Chips with Cu wires/cu pillars, ii. Identification of corrosion failures, iii. Identification of oxidation failures) h. Test Vehicles/Test Chips 3
VI. Thermomechanical Stresses a. Solder Bump Stress b. Solder Joint Stress c. Die Corner Stress d. Low-K Dielectrics VII. Case Studies, Q&A Session Participants learn basic but powerful aspects about the semiconductor packaging. This skill-building series is divided into four segments: 1. Basic Semiconductor Copper (Cu)Wire Bonding Metallurgy: Participants will study the phase diagrams that are most useful to IC packaging and learn about basic metallurgy topics such as melting, solidification, intermetallic compounds, oxidation, corrosion and welding. 2. Important Copper Alloy Systems in IC Packaging: The course presents metallurgical principles with selected alloy and materials systems that are key to the understanding and analysis of semiconductor (IC) packaging assembly and reliability. 3. IC Mounting and Copper (Cu) Wire Bonding: Participants will learn about alloy mounts and Ag-filled die attach. Additionally, they'll learn about wire bonding, flip-chip soldering, and package mounting. Phase diagrams are used as a basis for examining what solid solutions, phases, and intermetallic compounds (IMC) should be expected in an assembled or PC-board mounted IC package, and where the phases should form in a well-built system. Oxidation/reduction potentials are the first steps toward resolving corrosion resistance issues, either in package design or failure analysis. Since assembly techniques join metals by soldering or thermo-compression/thermosonic methods, the behavior of melting and solidification and the formation of solid solutions and IMCs, as read from the phase diagrams, is presented as an important predictive and diagnostic tool. 4. Copper (Cu) wire Reliability and Environmental Tests: The last part of the class brings together the basic principles and selected alloy systems to analyze the results of reliability testing, interpret the observed failure modes to identify root causes, and predict behavior for materials or process changes implemented to lower costs and/ or improve reliability. The course covers moisture tests, thermomechanical tests, electromigration, and failure analysis methodology. 4
ROGER JOSEPH STIERMAN Dr. Roger Stierman is an independent consultant who focuses on packaging issues and analysis techniques. Roger received a B.S. in Physics from Loras College and M.S. and Ph.D. degrees in Metallurgy from Iowa State University. During his 25-year career at Texas Instruments, he developed processes for semiconductor package assembly and characterized semiconductor packaging materials such as die attach, mold compounds, polymer overcoats, wire bond and flip chip connections, flip chip underfills, and package-to-pwb attachment. As manager of the Semiconductor Packaging Lab, he delivered training for physical failure analysis methods including precision cross-sectioning, SEM/EDS, X-Ray, tensile and 4-point bend testing, microhardness, RIE/ICP etching, ion milling and laser decapsulation. Currently, he is a consultant on semiconductor packaging failure analysis for Omniprobe Inc. 5