Xilinx CN Package Qualification Updates for MRQW 2015 Kangsen Huey Space Product Marketing Manager January, 2014
CF (IBM) vs CN (Kyocera) Packages Page 2
Comparison between IBM (CF) and Kyocera (CN) Packages Original IBM CF Package New Kyocera CN Package Silicon and Substrate Remain the Same All design tools and timing files remain the same Package pin assignment and Design place & route are preserved BME capacitors used remain the same parts (Tin-Lead Terminals) Assembled at IBM at Bromont Canada CGA with IBM 90/10 solder columns High Lead Flip Chip Solder Bump High Lead Solder for Capacitor Attach SiC Lid (Electrically Non-Conductive) Assembly Related Changes Assembled at Kyocera at San Diego CGA with 6-Sigma 80/20 solder columns Eutectic Flip Chip Solder Bump Eutectic Solder for Capacitor Attach Al-SiC Lid (Electrically Conductive) TIM and Underfill Material (IBM Specific) PCB Land Pad diameter = 07 mm TIM and Underfill Material (Kyocera) PCB Land Pad diameter = 08 mm Page 3
CN Package Qualification Summary Virtex-5QV is the CN qualification vehicle V5QV has the largest die, the largest package, the most solder bumps, and the highest pin counts among all Virtex-4QV and Virtex-5QV packages 3 assembly lots built from 3 wafer lots are required for qualification Virtex-4QV families of devices are automatically qualified by Virtex-5QV qualification results Qualification tests include: QML Group A, B, C, D, E Destructive Physical Analysis (DPA) Temperature Cycles (TC) Biased-HAST High Temperature Storage (HTS) Qualification has completed in January, 2015 Qualification Report to publish around the end of January Qualification data will be submitted for MIL-PRF-38535 class Y certification Target for QML-Y for Virtex-5QV in 2016 Page 4
Virtex-5QV CN Package Qualification Status Lots Quantity Status Note Assembly 3 all parts Completed at Kyocera Group A 3 all parts Completed Group B 3 3 / lot Completed Group C 3 47 / lot Completed 1,000hrs@125 o C Group D 3 45 / lot Completed Group E 3 22 / lot Completed DPA 3 5 / lot Completed Temp Cycle 3 15 / lot Completed Biased-HAST 3 15 / lot Completed HTS 3 15 / lot Completed 501 parts consumed to conduct CN package qualification tests Page 5
Assembly Builds Pre-Qualification at Kyocera conducted Multiple engineering built for process optimizations XQDaisy-CN1752 build completed as process validation Material Characterization Moisture Sensitivity Level (MSL) = 1 Out-Gassing per ASTM E-595 meets TML < 10% and CVCM < 01% requirement Standard Assembly process utilized for Qualification Builds 3 assembly lots built from 3 wafer lots with a total of 600+ parts assembled All required assembly monitoring tests (internal/external visuals, die pull, CSAM, Lid shear) conducted Time separation required between assembled lots to account for material and process variations Lot #1 assembly lot built in April 2014, lot size > 200 Lot #2 assembly lot built in June 2014, lot size > 200 Lot #3 assembly lot built in July 2014, lot size > 200 Page 6
CN Qualification Test Status Update Group A Electrical Tests Completed 100% electrical test with full functional vector sets at 3-Temperatures on 100% production units for all lots Lot #1, Lot #2, and Lot #3 have all completed Group A tests All qualification units are ready for reliability tests Parts designated for customer shipments, have completed electrical screening tests All shippable parts stay as LGA in inventory Columns will be added when backlogs are booked Group B Completed Physical Dimensions, Internal Visual, Die Pull tests Other assembly inline tests also serves as Group B requirements Lot #1, Lot #2, and Lot #3 have all completed Group B tests Page 7
CN Qualification Test Status Update Group C Life Tests Completed 47 units per lot, 1,000 hours at Ta = 125 o C Lot #1, Lot #2, and Lot #3 have all passed Group C tests Group D Tests Completed Includes Group D1, D3, D4, and D5 tests (15 units per each subgroup) Lot #1, Lot #2, and Lot #3 have all passed Group D tests Group E Tests Completed 22 units per wafer lot tested for 1 Mrad(Si) total dose Lot #1, Lot #2, and Lot #3 have all passed Group E tests Page 8
CN Qualification Test Status Update Destructive Physical Analysis (DPA) Completed 5 units per lot MIL-STD-1580 DPA requirement Lot #1, Lot #2, and Lot #3 have all passed DPAs Biased-HAST (Highly Accelerated Stress Test) Completed 15 units per lot 130 o C, 85% Humidity, 2 atm, 35 V, for 96 hours Level 1 precondition (soak + 3x reflow) performed prior to HAST Lot #1, Lot #2, and Lot #3 have all passed the 96 hours test Continue to run HAST to 192, and 500 hours for data collection All 3 lots have passed 192 hours point, will reach 500 hours in March Page 9
CN Qualification Test Status Update HTS (High Temperature Storage) Completed 15 units per lot 150 o C, for 1,000 hours after 3x reflow Lot #1, Lot #2, and Lot #3 have all passed the 1,000 hours test Continue to run HTS to 2000 hours for data collection Lot #1 completed 2,000 hours Lot #2 & #3 will reach 2,000 hours in April Temperature Cycle Test (T/C) Completed 15 units per lot TM1010, Condition C (-65 o C to +150 o C), 500 cycles required Level 1 precondition (soak + 3x reflow) performed prior to T/C Lot #1, Lot #2, and Lot #3 have all passed 500 cycles Continue to run T/C to 2,000 cycles for data collection Lot #1 done 2,000 cycles Lot#2 & #3 will reach 2,000 cycles in March Page 10
Post-T/C Inspections CSAM & Cross-Section conducted after 500 & 1000 Temp Cycle tests CSAM top scan Showed no delamination No voids in underfill Cross-Section examinations Detailed examinations done on multiple bumps at corners and center of the packages No cracks on solder bumps, underfill, die, and substrate observed No flux residue observed Page 11
Board Level Reliability (BLR) Tests 6-Sigma Solder Column Attach Utilize 6-Sigma QML-V production process for V-grade devices BLR parts now in column attachment process (40+ to be used for BLR) Two type of Parts (no-cga-rework and with-multiple-rework) to address effects for column reworks BLR test shall complete in mid-2015 This is a reliability demonstration test, and does not gate CN qualification Xilinx has used 6-Sigma columns for ~10 years with Virtex-II family 6-Sigma has done V4QV and V5QV column replacements for many customers Many Xilinx customers have already qualified V5QV with 6-Sigma columns FR-4 PCB pad diameter will be 08mm 08mm pad diameter is per 6-Sigma specification (IBM spec is 07 mm) Page 12
Xilinx Space-Grade Roadmap V4 Release V5 Design, Qual, & Release ADQ Flow 10k Hr Lifetest 38535 Class Y (JC13/G12) 10k Hr Lifetest V5 Radiation Characterization (XRTC & NASA/GSFC) V5QV class Y Certification QML V5QV QML Product Offering CN Pkg Qualification Next Gen RT FPGAs 2008 2009 2010 2011 2012 2013 2014 2015 2016 Page 13
Why RT for Next Gen Space Parts Flip-Flops Distributed RAM FPGA Overhead Block RAM Configuration RAM # 12T SRAM Cell needed for 100% Configuration RAMs Implemented at 65nm for V5QV (25% silicon growth) RH-BD requires the same spacing Z for all smaller nodes (28nm, 20nm, 16nm) New generation products are much larger than V5QV and need more Configuration RAM, implementing 12T-Cell no longer effective in silicon architecture Rad-Tolerant (RT) approach is more suitable for next generation Space FPGA Xilinx is evaluating 20nm and 16nm technologies Will offer a single technology node for next generation Space parts Z Page 14
Missions with Virtex-5QV Orion 2014 / 2018 Launch Iridium Next (66+6+9) (2015 Launch) Formosat-5 (2015 Launch) OSIRIS-REx (2016 Launch) LCRD (2017 Launch) DLR H2 Comm Sat (2017 Launch) Page 15 NovaSAR Glonass-K Grace Follow-On 2017 Launch
Summary Reprogrammable FPGAs enable platform designs, hardware/ip re-use, hardware consolidation The best solution for faster development time with lower costs Reduces project risk and maintains schedule Rich resource of Logic Cells, DSPs, and Connectivity hard IPs suitable for High bandwidth data processing High throughput IO connectivity Reduction of BOM In-Orbit Updates/Optimizations/Repairs V5QV is the most optimized RH-BD FPGA for Space Payload Applications Elevates Users from Programmable Logic Designs to Programmable System Integrations Page 16
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