Wire Bonding Integrity Assessment for Combined Extreme Environments

Similar documents
10 Manor Parkway, Suite C Salem, New Hampshire

Wire-bonds Durability in High-temperature Applications M. Klíma, B. Psota, I. Szendiuch

Cal-Chip Electronics, Incorporated Thick Film Chip Resistors - RM Series

Power Electronics Packaging Revolution Module without bond wires, solder and thermal paste

Silicon Wafer Processing PAKAGING AND TEST

Failure Modes in Wire bonded and Flip Chip Packages

BAR STRAIN GAGE DATA SEMICONDUCTOR BAR STRAIN GAGES DATA SHEET

curamik CERAMIC SUBSTRATES AMB technology Design Rules Version #04 (09/2015)

SP3S-AQ2-01 AIR QUALITY SENSOR S March, 2004

AN Handling and processing of sawn wafers on UV dicing tape. Document information. Sawn wafers, UV dicing tape, handling and processing

SLID bonding for thermal interfaces. Thermal performance. Technology for a better society

Challenges for Embedded Device Technologies for Package Level Integration

Nondestructive Internal Inspection. The World s Leading Acoustic Micro Imaging Lab

1/2W, 0612 Low Resistance Chip Resistor (Lead / Halogen Free)

Effects of Fretting Corrosion on Au-Sn Plated Contacts in Electronic Cable Interconnect

Dallas Semicoductor DS80C320 Microcontroller

Using Argon Plasma to Remove Fluorine, Organic and Metal Oxide Contamination for Improved Wire Bonding Performance

Micro-tube insertion into aluminum pads: Simulation and experimental validations

Cu Pillar Interconnect and Chip-Package-Interaction (CPI) for Advanced Cu Low K chip

IMPACT OF LEAD-FREE COMPONENTS AND TECHNOLOGY SCALING FOR HIGH RELIABILITY APPLICATIONS

Choosing the Correct Capillary Design for Fine Pitch, BGA Bonding

1/2W, 0805 Low Resistance Chip Resistor (Lead / Halogen free)

Quality and Reliability Report

IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION

Quality in Electronic Production has a Name: Viscom. System Overview

New Technology for High-Density LSI Mounting in Consumer Products

Interlayer Dielectric (ILD) Cracking Mechanisms and their Effects on Probe Processes. Daniel Stillman, Daniel Fresquez Texas Instruments Inc.

Effect of Die Bonding Condition for Die Attach Film Performance in 3D QFN Stacked Die.

National Semiconductor LM2672 Simple Switcher Voltage Regulator

28nm Mobile SoC Copper Pillar Probing Study. Jose Horas (Intel Mobile Communications) Amy Leong (MicroProbe) Darko Hulic (Nikad)

Innovative MID Plating Solutions

Visit

Three-Dimensional Molded Interconnect Devices (3D-MID)

System Level Effects on Solder Joint Reliability

Material Selection and Parameter Optimization for Reliable TMV Pop Assembly

surface. As heat and ultrasonic energy soften the wire and pad metallization the bonding tool deforms the bonding wire against the bond pad and forms

Recent Advances in Die Attach Film

YOUR Strategic TESTING ENGINEERING CONCEPT SMT FLIP CHIP PRODUCTION OPTO PACKAGING PROCESS DEVELOPMENT CHIP ON BOARD SUPPLY CHAIN MANAGEMENT

Reference Only. 2.Part Numbering (ex) NF Z 5B BW 2R9 L N 1 0 L

Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications

Figure 1 Copper vs Gold Wire Savings

Motorola PC603R Microprocessor

Fraunhofer IZM Berlin

Study of anisotropic conductive adhesive joint behavior under 3-point bending

State of the Art,Inc. High Reliability Thick & Thin Film Resistive Products

Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes. Jason Chou and Sze Pei Lim Indium Corporation

SGS-Thomson M17C1001 1Mb UVEPROM

Low Profile 0.5mm Pitch Connectors For FPC

Long-term reliability of SiC devices. Power and Hybrid

Component Palladium Lead Finish - Specification Approved by Executive Board 1997-xx-xx August 22 Version

Automotive Electronic Material Challenges. Anitha Sinkfield, Delphi

Discrete Capacitor & Resistor Issues. Anthony Primavera Boston Scientific CRM 11/13/06

Plasma for Underfill Process in Flip Chip Packaging

EXPERIMENTAL RESEARCH OF COPPER WIRE BALL BONDING

Composition/wt% Bal SA2 (SABI) Bal SA3 (SABI + Cu) Bal

DEVELOPMENT OF LEAD-FREE ALLOYS WITH ULTRA-HIGH THERMO- MECHANICAL RELIABILITY

Rockwell R RF to IF Down Converter

High Stability Resistor Chips (< 0.25 % at Pn at 70 C during 1000 h) Thick Film Technology

Critical Review of US Military Environmental Stress Screening (ESS) Handbook

Hitachi A 64Mbit (8Mb x 8) Dynamic RAM

VTT TECHNICAL RESEARCH CENTRE OF FINLAND. LTCC Packaging & Smart System Integration Horten Kari Kautio

NANO SCRATCH TESTING OF THIN FILM ON GLASS SUBSTRATE

RF System in Packages using Integrated Passive Devices

20 W Power Resistor, Thick Film Technology, TO-220

CHARACTERISATION OF INTERFACIAL CRACKING IN MICROELECTRONIC PACKAGING

Reliability Qualification Report

Reference Only. Chip Ferrite Bead BLM31 SZ1 Murata Standard Reference Specification [AEC-Q200]

The Nordic Electronics Packaging Guideline. Chapter A: Wire Bonding

Reference Only. Chip Ferrite Bead BLM31 SH1L Murata Standard Reference Specification [AEC-Q200]

Fig 1. Typical application for thick film on ceramic substrates (simplified)

AN IGBT Module Reliability Application Note AN April 2015 LN32483 Author: Dinesh Chamund

High Current Thermal Fuse

Assembly of planar array components using anisotropic conducting adhesives: a benchmark study. Part I - experiment

Hot Pin Pull Method New Test Procedure for the Adhesion Measurement for 3D-MID

FLIP CHIP CHIP ON BOARD SMT ENGINEERING OPTO PACKAGING SUPPLY CHAIN MANAGEMENT TESTING YOUR INNOVATIVE TECHNOLOGY PARTNER PRODUCTION CONCEPT

Platinum Temperature Sensors

Packaging Technologies for SiC Power Modules

Development of an Low Cost Wafer Level Flip Chip Assembly Process for High Brightness LEDs Using the AuSn Metallurgy

A New Thermal Management Material for HBLEDs based on Aluminum Nitride Ceramics

MTS Semiconductor Solution

High Temperature Circuit Reliability Testing Updated February, 2003

MATERIAL NEEDS AND RELIABILITY CHALLENGES IN AUTOMOTIVE PACKAGING UNDER HARSH CONDITIONS

Critical Barriers Associated with Copper Bonding Wire. William (Bud) Crockett Jr.

Low Temperature Co-fired Ceramics (LTCC) Multi-layer Module Boards

nicrom e l e c t r o n i c

Final Year Project Proposal 1

Preprint - Mechatronics 2008, Le Grand-Bornand, France, May

Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes

Key words: microprocessor integrated heat sink Electronic Packaging Material, Thermal Management, Thermal Conductivity, CTE, Lightweight

Making the most out of SiC. Alexander Streibel, Application Engineer

Quality and Reliability Report

Study of the Interface Microstructure of Sn-Ag-Cu Lead-Free Solders and the Effect of Solder Volume on Intermetallic Layer Formation.

Effects of Design, Structure and Material on Thermal-Mechanical Reliability of Large Array Wafer Level Packages

Chips Face-up Panelization Approach For Fan-out Packaging

DC-DC Converters MI-J00

Chapter A: Wire Bonding

Reference Only. Spec. No. JENF243D-0006K-01 P 1/ 8

Features. = +25 C, 50 Ohm System

Copper Wire Bonding Technology and Challenges

PRELIMINARY. HTHA (Z1-Foil)

Transcription:

Wire Bonding Integrity Assessment for Combined Extreme Environments Maria Mirgkizoudi¹, Changqing Liu¹, Paul Conway¹, Steve Riches² ¹Wolfson School of Mechanical and Manufacturing Engineering, Loughborough University, Loughborough, LE11 3TU, UK ²GE Aviation Systems - Newmarket, 351 Exning Road, Newmarket, Suffolk, CB8 0AU, UK M.Mirgkizoudi@lboro.ac.uk

Outline IeMRC Annual Conference 2012 Background Problem Identification Research Focus Experimental Details Experimental Approach Test Samples & Wire Bonding Wire Bonding Characteristics Experimental Design Results Discussion Conclusions Acknowledgements

Background IeMRC Annual Conference 2012 Wire bonding: 40 years of reliability background. Harsh environment applications raise concerns about reliability under combined extreme loadings. New industry requirements

Problem Identification The main concerns in assembly and packaging: Low cost Small size Functional density Integration density Fundamentals of failure under complex and harsh conditions Unit to compare Best Middle Worst Cost WB - FC, TAB Manufacturability WB FC* TAB** Flexibility for changes WB - FC, TAB Reliability FC WB, TAB - Performance FC TAB WB, TAB Major Interconnection Technology Comparison¹ ¹Harman, G., Wire bonding in microelectronics materials, processes, reliability and yield, McGraw-Hill, 2 nd Edition, 1997 *Flip Chip **Tape-automated bonding

Research Focus IeMRC Annual Conference 2012 a The effects of combined thermal and vibration loadings on wire bonding performance - the rational: Temperature and vibration are prime causes of failure within electronic circuits. Research on behaviour of wire bonded devices limited only in normal operation conditions. Knowledge gap in testing and qualification of electronics under combined harsh conditions. Wire bonding performance under those combined conditions has not been fully characterised.

Experimental Approach Investigation of: 1. Bond strength & mechanical integrity 2. Electrical resistivity changes 3. Microstructural defects induced 4. Wire orientation role on wire degradation 5. How loop geometry is affected by the conditions applied Analysis methods: 1. Wire pull & ball shear testing 2. Electrical resistance measurements 3. Metallographic observation

Test Samples & Wire Bonding Alumina (Al 2 0 3 ) ceramic substrates with interconnected components and embedded heating element Silicon chips Au thick film conductor tracks Pd-Ag solder connection pads Thick film resistor sensors Heating element

Test Samples & Wire Bonding Al 2 0 3 Ceramic Substrates with Au thick film pads Wire Bonding: Au ball-wedge bonding. The gold pads were wire bonded by pairs of two: one pair using low loop height and, one using a larger loop height Low loop height Au Pad Al 2 0 3 ceramic base Large loop height a) b) Schematic representation of the two wire bonding profiles for the a) low loop height and, b) large loop height.

Test Samples & Wire Bonding 48-pin Dual-in-line (DIL) High Temperature Co-fired Ceramic (HTCC) Wire Bonding: Au ball-wedge bonding Two wire loop heights X & Y direction wire bonding to allow testing on two axes at the same time Au track Low loop height Low loop height Large loop height Large loop height Schematic representation of the wire bonding profile for the two loop heights

Wire Bonding Characteristics h1, h2 L Ball Bond Wedge Bond Schematic representation of the wire bonding structure, a) top view and, b) side view. Description Wire Diameter () 25 µm Ball Diameter () 75 µm Low Loop (h1) ~200 µm Large Loop (h2) ~300 µm Pitch size 300 µm Distance between ball & wedge bond (L) Wire bonding characteristics 2000-2300 µm

Experimental Design Phase 1: Understanding the parameters TEST 1: (verification of the testing system) Stage 1: Thermal Test ONLY: Elevated temperature up to 180 C* Stage 2: Vibration Test ONLY: Sine fixed frequency at 300Hz Acceleration at 10g rms *Temperature increase by power input TEST 2: (combined thermal & vibration test) Stage 1: Elevated temperature up to 180 C. Sine fixed frequency at 500Hz. Acceleration at 10g rms. Stage 2: Elevated temperature up to 180 C. Sine fixed frequency at 1500Hz. Acceleration at 20g rms. Stage 3: Elevated temperature up to 180 C. Sine fixed frequency at 2000Hz. Acceleration at 20g rms.

Experimental Design Phase 2: Factorial design Test replicates and duration: Each test replicated 3 times (one for each axes) Total duration of each test: 3hours Process Parameter Level Run No. Temp. Freq. Accel. 1 - - - 2 + - - 3 - + - 4 + + - 5 - - + 6 + - - 7 - + + 8 + + + Orthogonal Array and Control Factors Assignment The design consists of 3 factors each at 2 different levels: Each level (high (+) and low (-)) of the factors represented as follows: Temperature level: 250 C (+) and 180 C (-) Frequency level: 2000 Hz (+) and 500 Hz (-) Acceleration level: 20 G (+) and 10 G (-)

Experimental Design Phase 3: High temperature-vibration testing based on Aviation Standards Stage 1 Temperature exposure at 25 C, 180 C and, 250 C (3 hours) Stage 2 Sinusoidal vibration testing (vibration test procedure for airborne equipment) Stage 3 Temperature exposure (25 C, 180 C, 250 C) (3 hours) & sinusoidal vibration testing (3 axes)

Electrical Characterization Resistance (mω) 20 19.5 19 18.5 18 17.5 17 16.5 16 15.5 15 14.5 14 13.5 13 12.5 12 11.5 11 10.5 10 Before Testing 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Sample No. After testing Electrical resistance changes for the a) low loop and, b) the large loop wires before ( ) andafter( ) testing Resistance (mω) 23 22.5 22 21.5 21 20.5 20 19.5 19 18.5 18 17.5 17 16.5 16 15.5 15 14.5 14 13.5 13 12.5 12 11.5 11 10.5 10 Before Testing 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Sample No a) b) After testing

Bond Strength IeMRC Annual Conference 2012 Wire Orientation on the Vibration System Ball Bond Shear Failure Load, grms 120 C 500Hz 10grms 250 C 500Hz 10grms 120 C 2000Hz 10grms 250 C 2000Hz 10grms 120 C 500Hz 20grms 250 C 500Hz 20grms 120 C 2000Hz 20grms 250 C 2000Hz 20grms Y X Z All bonds Mean 48.73 32.03 49.61 42.50 49.25 37.28 50.46 50.85 SD 8.63 3.00 10.92 9.87 12.50 15.82 8.32 16.78 Mean 50.26 30.13 56.92 44.29 47.07 28.72 51.06 44.48 SD 8.08 3.07 2.54 13.74 12.45 6.13 8.78 15.78 Mean 43.61 41.92 54.55 40.49 58.16 32.97 53.39 44.53 SD 11.35 9.36 4.66 10.80 2.34 9.38 4.06 14.36 Mean 47.38 34.98 53.73 42.35 51.76 32.99 51.70 46.54 SD 9.62 7.96 7.30 11.17 10.84 11.20 7.06 15.25 Shear load mean values and standard deviation for bonds after testing MIL-STD 883H

IeMRC Annual Conference 2012 Metallographic Observations Observations from failed balls after shear testing Ball shear Observed in all cases Ball shear and partial ball lift off Ball shear and partial metallization lift off After testing at: 250 C, 500 Hz, both 10G and 20 G

IeMRC Annual Conference 2012 Metallographic Observations SEM analysis of failed bonds & wires Wire Failure distortion due to low frequency-high associated Interconnectionacceleration failure vibration combined with high on temperature 250 C with loading short circuiting the silicon at chip

Metallographic Observations Observations from deformed wires after testing Wires tangled to one direction X axis orientation 250 C and 120 C 500 Hz Both10Gand20G Wire bend Y axis orientation 250 C 500 Hz 20 G Wires tangled sideways Z axis orientation 250 C 500 Hz Both10Gand20G

Metallographic Observations Observations from deformed wires after testing Short circuit X axis orientation 250 C 500 Hz 20 G Ball lift off X & Z axes orientation 250 C 500 Hz Both 10 and 20 G

Conclusions IeMRC Annual Conference 2012 The findings of this study on Au ball bonded devices include: An appreciable decrease in the electrical resistance after testing which could be attributed to annealing of the wire. The shear force to failure of the ball bonds is reduced after testing particularly at higher temperature and low frequency vibration. Distortion of the larger wire loops is more severe when testing at low frequencies. The effect of wire orientation in respect to the direction of the vibration should be considered when vibration is involved in the testing regime.

Conclusions IeMRC Annual Conference 2012 Further tests are planned to extend the vibration/temperature regime and also to examine the effect on wire bond pull strengths,whereannealingofthewireabovetheballbond may result in changes in performance under combined vibration/temperature conditions. On real devices, the combined vibration/temperature exposure needs to be extended to generate end of life failure modes, where changes in electrical characteristics can be measured and failure analysis undertaken.

Acknowledgements IeMRC Annual Conference 2012 GE Aviation Systems (Newmarket, UK) for providing the testing samples and valuable technical guidance. Inseto Limited (Andover, UK) for technical support and guidance through the wire bonding process. MTC (Ansty Park, Coventry, UK) for providing the facilities and assistance for the shear & pull testing.

Thank you Any Questions?