IME roprietary ERC 12 roject roposal Embedded Cooling Solutions for 3D ackaging 15 th August 2012 age 1
Technology & ower Dissipation Trends IME roprietary Cannot continue based on Moore s law scaling alone. Technology trend: System level integration in package to deliver more than Moore ower dissipation trends in the past shows steady increase for thermal power requirements, while maximum junction temperature limit remains fixed for Si devices. Furthermore, demand for ever smaller package size continues. age 2 Source: ITRS
Motivation Addressing on-uniform Temperature Spread (Vertically and Laterally) IME roprietary on-uniform Vertical Temperature Spread in die stack [1] [2] If top cooled : 90% on-uniform Horizontal Temperature Spread [3] 10% 1. Die stacks have an increased heat dissipation density. Removing heat from within the stack is a well-known challenge. 2. In particular, conventional back-side cooling has a limited effect on stacked hotspots 2. 3. Furthermore, we can expect up to 200% speed gain from targeting hotspots 4 age 3 Source : [1] IME; [2] IBM, ITHERM, 2008; [3] Bryan Black, Intel; [4] Tritt, T.M.: Thermoelectric materials, phenomena, and applications:a bird s eye view. MRS Bull. 31 (2006)
roposal: Embedded Thermoelectric Cooling IME roprietary Goal: Active non-volatile cooling between stacked layers, to target hotspots Thermoelectric rinciple: Direct conversion of applied current to temperature difference for cooling Thermal erformance Characteristics 1 For efficient power management target hotspots umping ower: >150W/cm^2 (thin-film TE advantage) Temperature Differential : 60 C Cooling capable of generating thermal resistance < 0 C/W Increases system cooling load, but may reduce perpackage-level cooling load Mechanical erformance Characteristics Reduction in ackage Thermal Resistance with embedded TEC (Source : 1 extreme) Compact low-profile size Solid-state with high reliability (no mechanical wear/dirt contamination) Multiple interfaces mismatch age 4 Thin Film Thermolectric erformance Advantage over Bulk TEC (Source : 1 extreme)
roposed 3D Die Stack with Integrated TEC Integrated at Die-Level (with Hotspot Heater & Diodes) IME roprietary Solder Bumps Cu illar : Homogenous Stack Cu illar : Heterogenous Stack Q Q Q Q Q Q High-conductive Substrate High-conductive Substrate High-conductive Substrate roposed Thermoelectric Structures for Integration TE at Die Front-Side with Bi-directional Operation Test Hotspot Heater & Diode Diode Hotspot Heater Diode Hotspot Heater illar A illar B illar A illar B Apply current to A->B for cooling in top direction. Apply current B->A for cooling in bottom direction. age 5
Challenge Approach Targeted Cooling within Stack Challenges IME roprietary Wafer-level TE Thin Film Fabrication Sb 2 Te 3 Bi 2 Te 3 process development : lift-off challenge in sputtering process; meeting n-type and p type composition requirements Algorithms Top die cooling: Able to direct top die cooling to top, if top side cooling is available. Middle die cooling: Adjoining dies TEC can pump heat out in both top and bottom directions. Bottom die cooling: Able to pump heat to bottom Via-MiddleTSV Fabrication TSV fabrication (etch, plating, etc) RDL Fabrication Low temperature-cure/low-stress dielectric incorporation Cu illar/bumps Fabrication Substrate Cu pillar forming: 100um diameter; 200um pitch; 100um height Chip-stacking process development Hotspot Heater/Diode Fabrication rocess development for high heat flux heater in precise area rocess development for isolated diode High-conductive Substrate Fabrication Integration into assembly process flow age 6
roject roposal* IME roprietary Objective: Development and characterization of embedded thermoelectric cooling system in diestack for next generation of 2.5D/3D devices, including the following: Development of embedded thermoelectric cooling in stacked-die package to target hotspot cooling rocess development of TE thin-film fabrication integration at wafer-level Co-design of TEC operating algorithim Electrical and Thermal analysis on multivariable (heat transfer/power input) for efficient operation Mechanical structural design and failure mechanism analysis of package interconnects and component integration Heatspreader Substrate Applications: Advanced mobile/wireless applications (smartphones, tablets, ultrabooks) without convective cooling (silent operation) Cost-performance devices (laptops, desktops, etc.) age 7 * To be finalized with members input
IME roprietary Thermoelectric Design, Modeling and Analysis of TEC unit arametric analysis of TEC unit for optimum cooling efficiency Characterization of TE material property and geometry (on figure of merit ZT) Effects of interconnection materials on electrical and thermal contact resistivities (e.g. semiconductor-metal interfaces, solder bump, Cu pillar bump with solder cap) Investigation of cooling capability on TE material bias current (e.g. optimum steady current level for max. cooling load, temperature change with periodic or pulsed current, etc) Development of equivalent circuit for TEC unit (e.g. macro modeling behavior, parametric extraction of different effects, such as Joule heating, eltier cooling and Seebeck effect, etc) (Source: A. Shakouri, 2005 ) (Source: A. M. ettes, 2007 ) (Source: S. Lineykin, 2005 [3]) (Source: IME) age 8
TEC lacement in 3D Die Stack IME roprietary Behavior modeling of TEC placement for optimum cooling efficiency Transformation of the thermoelectrical cooling system into an equivalent pure electrical circuit to reduce computational complexity Intelligent installation (i.e. min. units and optimum locations) of TECs to dissipate heat away in high heat flux regions Global search of effective thermal conductive paths in 3D die stack using the equivalent system network model erformance evaluation of different TEC topology arrangement (e.g. top die, middle die and bottom die cooling, multistage cooling [5], etc) to optimize coefficient of performance (CO) age 9 (Source: A. Bar-Cohen, 2009 ) (Source: M. Hodes, 2012 )
otential of localized low power sensing and control circuitries for thermal management of non-uniformly distributed, time varying hot spots (e.g. standby ASIC processed only at need) Bi-directional switch array for biasing TEC in top die or bottom die cooling mode IME roprietary Flexible Thermoelectric Cooling Control System in 3D Die Stack with Experimental Characterization Cooling efficiency enhancement by individual control of TECs (Source: M.. Gupta, 2010 Standby Active Active Standby High-conductive Substrate TEC TEC Standby Circuitry TEC idle (Source: R. D. Harvey, 2007 [7]) Active Circuitry TEC on age 10
IME roprietary Structural Modeling and Failure Analysis of 3D ackage Structural modeling and failure mechanism of the interconnections Effect of interconnection geometry (e.g. UBM size, Cu pillar geometry, etc) Effects of interconnection materials (e.g. solder bump, Cu pillar bump with solder cap) Bump failure characterization (i.e, shear testing) and correlation with modeling Understanding of delamination mechanism (especially for TEC under Cu pillar bump case) Method for stress reduction for 3D chip stacking Chip stacking process simulation Compliant-rigid interconnection structures, including variable Cu pillar e.g. rectangular pillar UBM and stress buffering design Substrate CTE, landing pad / lead Stress interaction of heatspreader-lid-to-die-stack stresses Warpage analysis and fracture mechanics analysis of TIM attachment and structural adhesive for FCBGA with and without heatspreader lid Slide 11 Integrated TE and Die Interconnect ions (Source: IME) Stress results for chip stacking (Source: IME) Heatspreader lid to Die Stress Modeling (Source: IME) Maximum stress at IMC/UBM interface
Thermoelectric Microfabrication Wafer-Level rocess TE process development Material sputtering process parameters IME roprietary Materials: (Sb, Bi) 2 Te 3 Target thickness: ~1um established Target contact area: 3x3um and larger feasible Controlling lift-off for sputtering process Focus on controlling target composition of n-type/p-type leg rocess Setup Feasibility rocess Integration Compatibility : with Cu RDL in development Wafer-level Thermoelectric Microfabrication (Source: Fraunhofer Institut hysikalische Messtechnik) TE process characterization Characterization of TEC coupled units Resistance; EDX Temperature/Q vs. input current Slide 12 (Source: IME)
Redistribution Layer Fabrication IME roprietary Redistribution process development Multiple layers of redistribution metal layers Sputtered seed, electroless seed Low temperature cure & low stress dielectric Dielectric and Cu adhesion on thermoelectric material Diode Diode Hotspot Heater Hotspot Heater RDL + UBM rocess illar A illar B illar A illar B Diode Diode Hotspot Heater Hotspot Heater illar A illar B illar A illar B Slide 13 (Source: IME)
Assembly rocess and Reliability Assessment Assembly / process development and characterization Cu pillar assembly / solder bumps assembly Solder cap (or solder bumps) coplanarity and solder wetting Selection of flux and solder wetting Flux dipping process and solder shorting Chip stacking assembly process development Underfill process development Between stacked chips (100um spacing between dies, 2-3 dies high) Stacked-die to substrate finish (OS, eiau, SO) or Alumina Heatspreader Lid Attachment on stacked-die process development ackage assembly and sample build for thermal and reliability characterization IME roprietary Reliability assessment (stacked-chip samples) Moisture sensitivity test (MSL3) Temperature cycling (TC1000) Chip stacking assembly process for various chip-stack arrangements (Source: IME) Slide 14 Lid-attach process (Source: IME)
Members inputs roject Flow Finalize project scope / test vehicle specifications IME roprietary Scope lanning Modeling rocess and assembly Characterization Final reliability Thermal Design Mechanical Design Electrical Design ackage Component/Assembly Material Investigation TE Layer rocess Development & Characterization Thermal and Electrical Co-Analysis TSV/Diode/Heater Mask Layout Thermal/Electrical Test Methodologies TSV wafer with diode and heater fabrication Stack Assembly rocess Development Thermoelectric Layers/Bumps Fabrication Highly Conductive Substrate Fabrication Final Test Vehicle Build Experiment thermal characterization Reliability age 15 Failure analysis and report writing
ossible Research Outcomes IME roprietary Thermoelectric and Structural Analysis for Embedded Thermoelectric Coolers in 3D ackage Heat transfer analysis modeling and characterization for selected material set and test vehicles Development of equivalent electrical circuit for TEC for use in stacked-die modeling. Interconnection fatigue life prediction ackaging component effect on the test vehicle stress Development of Thin-Film Thermoelectric Films at Wafer-Level rocess integration of (Sb, Bi) 2 Te 3 thin film fabrication on via middletsv wafer Subsequent dual RDL and UBM formation Assembly of Stacked-Die ackage Solder Bumping or Cu illar with Solder Cap Fabrication Chip-stacking process development High conductive substrate integration in assembly Heatspreader lid-attach process development Underfill and TIM application process development Operational Characterization and Guidelines for Hotspot Cooling in 3D ackaging using Embedded TEC Targeted hotspot cooling and control ackage-level thermal characterization for benchmarking Reliability Assessments & F/A for Embedded TE 3D ackage Temperature cycling Moisture Sensitivity Level 3 Failure analysis Slide 16
Slide 17 IME roprietary