Accelerating the next technology revolution Roadmap in Mask Fab for Particles/Component Performance Frank Goodwin, Vibhu Jindal, Patrick Kearney, Ranganath Teki, Jenah Harris-Jones, Andy Ma, Arun John Kadaksham, Stefan Wurm SEMATECH Copyright 2009 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.
Lithography Scaling EUVL Wavelength 13.5 nm (plasma source), 4x reduction All materials absorb 13.5 nm, so high vacuum enclosure and reflective optics Single exposure and extendable to below 11 nm Multiple exposure requires additional processing tools Design rules which support multiple exposure limit reduction of chip area, limits yield of devices per wafer
EUV Lithography EUV projection optics are reflective Differs from conventional refractive optics use in current production lithography systems Courtesy of Carl Zeiss SMT AG EUV masks are fundamentally different from traditional optical masks 40 to 50 Mo/Si (3nm/4nm) bi-layer coating for high reflectance with Ru (2.5nm) cap Requires low surface roughness; on the order of a few atoms Stringent flatness and curvature requirements No pellicle protection Mask must have no resolvable defects
EUV Mask Blank Challenges: Substrate and Blank Absorber/ARC Stack Optical Properties at EUV Properties at Inspection Wavelengths Particle Defects Etch Performance Ru Cap Particle Defects Film Loss from Etch Metrology Multilayer Particle Defects Uniformity Reflectivity and Centroid Wavelength Metrology (Defect Detection) This is where the difficultly lies!! ` Substrate Thermal Properties Particle and pit defects Subsurface polishing damage Flatness and Surface Roughness Metrology (Defect Detection) Backside Coating Electrical Properties Handling Defects
Challenges for EUV Technology Rankings of the top critical issues to be resolved with EUV Lithography Defect free masks E2012» 0 at sizes > 100nm M2013» 0 at sizes > 80nm E2013» 0 at sizes > 50nm E2014» 0 at sizes > 35nm Zero is a very small number
Typical EUV Mask Defects Ref: T. Kamo et al., Proc. of SPIE 7823 SEMATECH Confidential
SEMATECH s EUV Mask Defect Strategy Define what a defect is Printability Find them Inspection Eliminate as many as possible Process Optimization Mitigate the rest Repair, Pattern shift
SEMATECH s Industry Support Printability: define defects Substrates Blanks Absorber Programmed Native Inspection: find defects Substrates Blanks Patterned Masks pits bumps particles phase amplitude particles hard particles molecular Deliverable: Tools to create defect source Pareto Input to define how and what priority to reduce defects Elimination/Mitigation of Printable Defects Overall Reduction Mitigation Clean SEMATECH s Defect Reduction Program Repair Deliverable: Enable HVM Quality Masks Commercialize Success! Masks suitable for HVM
SEMATECH s Defect Analysis Approach Defect inspection Detection capability of inspection tools down to 35nm defect size Enhanced technique, with defect decoration, extends detection down to 10nm particle size Available failure analysis metrology (X-sectional and compositional analysis) FIB/SEM w/eds and AFM are the primary work horses for defect analysis down to 30nm AES and TEM used for even smaller defect sizes Fully integrated process ML film deposition and material cleaning on site All processes run and tools located in class 100 or class 10 environement Enables definitive isolation of defect sources
Defect Reduction Program Strengths Knowledge Characterization Modeling (Film growth / Deposition) Identification of Defect Sources / Mitigation Techniques FA Capability Defect Printability Native and Programmed Defects Actinic Imaging on wafer and with inspection tool Implementation Shield cleaning and texturing Target growth and surface conditioning Tool modification E-chuck evaluation Insitu cleaning and gettering Ion source Substrate turret / robot
SEMATECH Champion Data M1350 M7360 Dense Scan Achieved 12 defects @ 45 nm or 8 defects @ 50 nm from M7360 inspection 10 pits (from substrate), 1 handling defect, 1 defect from deposition 65% reduction in defects from last year champion data (23 defects @50nm)
Defect Pareto Total Defects C SAB SiOx Shields Others Si Ru Mo 0 10 20 30 40 50 60 70 80 90 Defect data off of a standard mask blank process run With the improvements all particle type defects have been reduced with the exception of C defects Majority from handling components of the deposition tool Specifically they originating from degradation of the valve door and static seals of the front-end
Partnered with ASNA Collaborative relationship ASNA works with SEMATECH to develop seal technology to resolve problems identified on the IBD handler SEMATECH supports ASNA development work with access to test chamber and advanced metrology
Evaluation test benches Test Chamber: UHV chmber Turbo pump with vacuum expected to be in low to mid 10E-8Torr Transfer Module: Clean sample handling Robot arm with stainless steel end effectors Load Locks: Pumped with combination of Roughing and Cryo pump. Typical pressure 5-9E-7Torr Hold up to 5 witness plates quartz substrates Metrology Chamber can be equipped with condensation particle counter Failure analysis EDS Auger electron spectroscopy Flow based technique for component evaluation with quick turn around. Developed at CNSE Capability to measure each particle down to 10 nm Information on Quick Fail/Pass check Test bench Operation and measurements possible at low pressure to 10Torr Clean baselines Downstream measurement Equipped with particle impactor plates Utilize impactor to provide samples for FA analyis
ASNA Program Status The two test benches are working and operational Able to support testing with 4 VAT valve types Monovat valve L Series valve 26 series valve 10 series valve Mechanical and durability testing Demonstrated detection capability down to 10nm Continue to work together to develop advanced metrology techniques Filler morphology, composition, size distributions, and distribution through bulk Distribution of base material and additive material from edge to the center of bulk Concentration of pores and sizes
EUV Mask Defect Summary Defects are created throughout the mask-making process Blank Defects Substrate Defects Deposition Defects Transport Defects Inspection: Find <50 nm diameter and <0.5 nm tall/deep particles or pits New techniques are required below 35 nm C l e a n D e p o s i t i o n P R E < 100 % D e c o r a t i o n Substrate Substrate Substrate Characterization: Determine composition of 30 nm defects to identify root cause Today: Auger: TEM: Need a new, high speed analytic technique down to 10 nm Review: Determine which defects print Requires an actinic tool since some defects are invisible using other techniques
EUV Mask Technical Gaps Challenges with mask defects continue: Incoming Material Substrate defects Multi-Layer Deposition Cleaning, handling, and deposition defect adders EUV Mask Use Use in wafer fabs without pellicles Durability and lifetime SEMATECH has developed unique capabilities to address mask blank defects Multilayer and cleans process tools on site Access to state of the art defect detection and FA analysis tools Multilayer deposition and cleaning process expertize Technical resources to develop fundamental understanding of tools and processes Experienced team of FA and metrology engineers SEMATECH remains focused on enabling the semiconductor industry to achieve HVM quality EUVL mask
Thank You
Accelerating the next technology revolution Research Development Manufacturing SEMATECH Confidential