Development of System in Package In recent years, there has been a demand to offer increasingly enhanced performance for a SiP that implements downsized and lower-profile chips at lower cost. This article describes the policy shift for the development of SiP and design/simulation technologies. * SiP: System in Package Introduction The evolution of cellular phones, DSCs/DVCs, and other such digital audiovisual (AV) equipment has been fueling increased demand for higher levels of external added values such as reduced size and lower-profile design features in addition to enhanced internal performance such as multiple functions and advanced features. As a result, it has become necessary for semiconductor devices to offer enhanced performance and to have architectures that allow downsizing and lower-profile configuration. As a solution package to satisfy the demand, the SiP was developed. The SiP was initially intended to be a supplementary package utilized to help migrate the functional block that integrates several semiconductor elements to form a system on a motherboard to the SoC (System on Chip) that implements these integrations on a single semiconductor device. However, given the recent trend of shorter product life cycles, which demand reduced time to market and more cost-effective development, the products that can assimilate benefits by SoC design and the products that cannot are obviously being divided. As a result, the SiP, considered on the basis of conventional technologies, has come to be applied for specific applications in which SiP is more suitable compared to SoC because of the required characteristics, delivery date, and costs (Fig.1 *1 ). Figure 1 Evolution of SiP and SoC 2005 No.1 FIND Vol.23 3
Policy Shift for the Development of SiP One of the reasons why the SiP has rapidly diffused over the last few years is its high degree of flexibility in fabricating an all-in-one package at low cost with multiple existing chips for which further development has already been discontinued. This advantageous feature has been satisfying the demand for downsized and lower-profile packages and thus offers greater benefits in terms of time to market and development cost over SoC. This high degree of flexibility has been supported by the rapid progress in package assembly technologies including thin wafers and stacked MCPs (multichip packages). As of 2001, the development of basic technology for 25m thickness was completed for thin wafer technology. *2 At the product level, the routing production of packages mounted with 60m-thick chips is currently underway. In the future, continued technological improvements may be expected in order to keep up with increasing wafer diameters. In terms of stacked MCP technology, in order to provide proper wire connecting space, a technology to insert dummy chips, adhesive films, or other spacer materials between chips, as well as bumpbonding technology using various flip chips processing based on Au-Au interconnection or Au-solder interconnection is now commonly used. In addition, a technology to stack multiple packages was also recently established and is gradually being applied to actual products. In terms of components, fine-pitch technology for interposers has been improved greatly, and the added values obtained through higher-density integration in a given wiring space and thin substrates have become essential for package assembly technology. Fig.2 presents typical products based on these technologies. Despite the successfully established assembly technologies, SiP is required to provide equivalent or higher performance compared to SoC, and the demands that cannot be fulfilled solely by the assembly technologies begin to increase. In addition, since the higher degree of package assembly flexibility has made the wiring configuration of interposers more complicated, any electrical characteristic defects become more apparent and the total costs including component costs increase in some cases. In order to solve these problems, SiP development policy is on the way to shift from a conventional assembly technology base to a design technology base. Figure 2 Typical Products 4 FIND Vol.23 No.1 2005
SiP Design Technology/Simulation Technology The characteristics of SiP depend on the configuration of incorporated chips and the design technology for the interposers incorporating the chips. Fig.3 illustrates a typical flow for the development of interposers, focusing on the design technology during the development of SiP. Based on the input information regarding the size of the chips incorporated in a package, the coordinates of the pad, the chip configuration, and other connection data, a model of the required virtual package is created. Using this virtual model, in order to determine the external configuration of the interposer, prior verification is conducted for factors that could cause problems in package fabrication; these factors include possible heat generation from chips, chip-to-chip and chip-to-interposer connections, as well as possible stresses exerted on the chips and interposers during the bonding process or the molding process. Subsequently, verification of the electrical characteristics takes place to determine the internal configuration or the internal wiring of interposers, thereby selecting the definitive interposer specifications. Implementing this flow allows prior verification of the thermal characteristics of the package, the presence of any structural problems, and the electrical characteristics. As such, it contributes to significantly reducing the development time and cost. Through the evolution of these technologies and the feedback of the verification results to the process steps, the offering of the chip devices designed with the specifically optimized pad arrangement for SiP has already started. Adopting the optimized chips helps simplify the wiring configuration in the interposers and thus minimize costs and any defects in the characteristics caused by the complicated interposers. Individual items for prior verification are detailed below. Figure 4 Typical Thermal Simulation maximum operating temperature 125) and a memory chip (allowable maximum operating temperature 100) are embedded in combination, the heat-generating temperature of the package must be limited to 100 or low. This makes it necessary to take into account the possible effects of heat Figure 3 Substrate Design Flow Thermal Simulation As thin wafer technology and stacked MCP technology evolve, the number of chips incorporated in a package increases and the thermal resistance of the entire package becomes larger as a result. For the SiP that allows the incorporation of different types of chips, they can be mounted in a combination that operate at different temperatures and in this way, the upper limit of the thermal resistance of the entire package is determined by the chip with the lowest limit temperature. For example, when a logic chip (allowable 2005 No.1 FIND Vol.23 5
generation from other chips when selecting the proper chip configuration, and the prior identification of the thermal resistance of a package is an important step for the development of SiPs. Fig.4 illustrates a typical thermal simulation. One popular approach to reducing the temperature of heat generated due to the thermal resistance of a package involves the addition of dummy balls known as thermal balls directly under the chip. The illustration on the left-hand side of Fig.4 shows the simulation of a normal configuration, and that on the right illustrates a simulation with added thermal balls. As is evident, the addition of dummy balls contributes to reduce the higher temperature region. In this way, through the prior verification of a package for the attainment of proper characteristics, chip configuration and ball arrangement can be possible. Three-Dimensional Wiring Simulation The incorporation of multiple chips can create a more complicated wiring configuration with a higher degree of flexibility. For devices that contain chip-to-chip interconnection and chip-to-interposer connection in combination (thus requiring a three-dimensional wiring configuration), problems involving short-circuited wires, short-circuited edges, and other defects have developed that cannot be properly verified using conventional two-dimensional wiring diagrams. In addition, the rapidly advancing thin wafer technology has resulted in smaller space in the height direction of the wire required for wire connection, leading to a higher probability of defect occurrence. This indicates the importance of prior verification that checks the geometry of wire three-dimensionally and optimizes the chip stacking position and pad arrangement. Moreover, given the current trend of the advancing fine-pitch design of both the Figure 5 Typical 3D Wiring Simulation Figure 6 Typical 3D Wiring Simulation (Capillary Behavior) chip and the interposer, consideration must be given to the actual capillary size and even its behavior. As such, it is an indispensable step in the development of SiP to verify the wire bonding process and determine the wiring configuration. Figs.5 and 6 illustrate typical 3D wiring simulations. Fig.5 illustrates the results of a 3D wiring simulation of a shortcircuited wire that actually occurred in a package. The simulation succeeded in reproducing the closest possible arrangement to the actual short-circuited wire, demonstrating that the shortcircuited wire could have been avoided if prior verification was properly conducted. Fig.6 provides the result of verification of the short-circuited wire in the actual package together with the capillary behavior. In this case, the possible causes of the shortcircuited wire could not be identified through verification of the 3D wiring, though the simulation of capillary behavior successfully reproduced the contact with the wire. This indicates that any problem involving the wiring process that is unidentifiable on the drawing can be properly verified. Stress Simulation As the number of stacks is increased through thin wafer technology, chips can be exposed to a variety of stresses. In particular, the overhang region formed by the combination of different chip sizes is considered more likely to break due to the bonding load in the wire bonding process and/or the sealing pressure in the 6 FIND Vol.23 No.1 2005
molding process. This makes it an indispensable check item in the development of SiP in order to verify possible stresses exerted on the chips in individual assembly processes and ensure that no breakage or malfunction occurs due to chip thickness, component material, or other factor. Fig.7 presents the result of a stress simulation for possible load exerted on the chip during the wire bonding process. The symbols and on the graph indicate the actual measurements, with showing freedom from any problem and showing the occurrence of a broken chip. The straight line depicts the result of verification on the stress applied to the chip based on the parameters of chip thickness and overhang. This simulation does not take into account the deflection of the chip according to chip thickness, though the figure shows that the straight line obtained by the simulation helps properly segregate the region that is very likely to break. Utilization of stress simulation technology allows identification of the solder joint reliability after mounting onto the motherboard. As such, stress simulation technology may be widely applied in various fields, including reliability checking. Electrical Characteristics Simulation The SiP, which forms a system in a package, allows the transmission of signals among the multiple incorporated chips. This relation can hold when a digital signal sent out from a chip is correctly transmitted to another chip through several wiring routes. In actuality, however, a complicated wiring configuration or the incorporation of different types of chips can cause the digital signals to be exposed to various noises, which may lead to possible malfunctions such as inverted logic or delayed signals. In addition, given the current trend for electrical characteristics comparable to those of SoC, it is also an indispensable item utilized to identify the required electrical characteristics through prior verification. Fig.8 illustrates a simulation of the electrical characteristics. The normal wiring using existing chips involves longer wiring in the interposer, though the wiring length may be reduced by one-half to one-third by optimizing the chips. For both cases, normal and optimized, electrical simulation results are presented in the figure. As is evident, optimization contributes to reducing the distortion of waveforms, thus demonstrating the benefit of optimization. This may be explained by the fact that the factors affecting the impedance can be reduced with the shorter wiring length and also the omitted passage through the via holes of the interposer *3. Figure 7 Typical Stress Simulation Future Conventionally, the SiP has been targeted for the development of consumer products including cellular phone and digital AV equipment. The advantages demanded here were higher degree of package fabrication flexibility due to the utilization of existing chips and faster delivery and lower prices as a result of the reduced development processes. However, in order to keep up with the changing market demands, it is now demanded that the SiP be aimed to offer multiple functions and higher performance for the specific applications in which only the SiP can satisfy the demands. As a result, in addition to the assembly technologies that have been continuously improved, various simulation technologies have become important to allow identification of characteristics even in the package design phase. In the future, it will be important to incorporate passive components and/or analog parts in the SiP and integrate into packages a variety of know-how on the design that has been applied to the motherboards, thereby enhancing the stability of system quality. The development of such packages cannot be achieved only in the framework of conventional Jisso/package departments, it requires the cooperation of device design and/or wafer process departments. Strengthened connections with the set makers (our customers) should also be considered important. In addition, the development of environmentally conscious packages without the use of lead or halogen as ever and morecustomized packages are also important. It is expected that further enhancement of assembly technology will be demanded more than ever in the future. 2005 No.1 FIND Vol.23 7
Figure 8 Typical Electrical Characteristics Simulation [Bibliography] *1: A. Takashima, et al.:packaging technology of accelerating SiP, NE/ND Hardware Conference 2002, *2: K. Teshirogi, et al.:about the work of 50um or less on the process development, SEMICON Japan 2002, Recent status of Thin Wafer Chip (die) Mounting Prospect of Less Than 50 um in Thickness, pp.47-80 (2002) *3: K. Ozawa, et al.:electric characteristics of SIP (System in Package), Journal of Japan Institute of Electronics Packaging, Vol.6, No.4, pp.326-331 (2003) 8 FIND Vol.23 No.1 2005