TGV and Integrated Electronics

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TGV and Integrated Electronics Shin Takahashi ASAHI GLASS CO., LTD. 1

Ambient Intelligence Green Energy/Environment Smart Factory Smart Mobility Smart Mobile Devices Bio/Medical Security/Biometrics 2

Glass and Electronics Designing /Decorative material Opening material Laboratory glass Display devices Optical component Human interface devices EDO KIRIKO www.edokiriko.or.jp 3

GLASS FOR SEMICONDUCTOR PACKAGING 4

Glass for Semiconductor Packaging g Image Sensor MEMS Integrated Passive Devices Photonic Devices 2.5D/3D Integrated Packaging Interposer Glass for Diverse Packaging 5

Comparison Substrate Core Characteristic Ideal Properties Substrate Core Electrical Physical Thermal - High resistivity - Low loss, Low K - Smooth surface - Thin and Large size availability - High Conductivity good fair poor Organic Si Glass Mechanical Chemical Reliability - High Strength, High modulus -Low warpage - Resistance to process chemicals - CTE matched Si and PCB Cost - At 25um pitch I/O Today s technologies are too expensive... Looking for Third Option. 6

Motivation for Glass Interposer Large glass core Low warpage Good electrical properties with low loss, low dielectric constant and high resistivity 7

Many Challenges for Glass Interposer Technical Challenges (driven by Industrial Consortia) - Productive TGV formation - Fine wiring - Micro bumping & Interconnection - Assembly - Inspection - Demonstration - Characterization and Reliability - Low cost technical concept Glass PWB Memory Stack Logic Die TGVs Industrial Challenges - Process Integration - Supply chain - Standardization - Low cost and higher yield - Volume 8

Key Challenges Gen. 0 Early Stage 2010-2013 Gen. 1 TGV Wafer 2014-2016 Gen. 2 TGV Panel 2016 ~ TGV formation TGV Metallization Performance & Reliability Supply Chain (Wafer Supply Chain (Panel Process) Process) Inspection & Assembly Low Cost Entire Process Design with Industry Partners Performance & Reliability Lower Cost 9

RECENT RESEARCH ACTIVITIES FOR GLASS INTERPOSER 10

Glass is only the beginning g Pitch: 120um, Diameter: 60µm(TOP) (Thickness: 300um) Pitch: 150µm, Diameter: 65µm(TOP) (Thickness: 500um) 500µmt for Thick Glass for Thin Glass Pitch: 100um, Diameter: 60µm(TOP) (Thickness: 180um) Pitch: 50um, Diameter: 25-30µm(TOP) (Thickness: 100um) 11

Glass Interposer Manufacturing Process Flow 1. Glass hole formation 2. Cu plating & CMP 3-1. Dielectric forming 3-2. Seed deposition & Photo litho 3-3. Cu/Au/Ni plating & Seed etching 4. 12

Cu Metallized Via and Fine Cu Wiringi 300um thick 60umΦ TGV L/S=2um/2um Fine Cu wiring fabricated by SAP (semiadditive process) 13

High Frequency Test B) S21(dB Frequency(Hz) Highly bulk resistance of TGV resulted in insertion loss less than - 0.12dB at 20GHz. 14

Reliability Test Fully filled Cu vias -40C to 85C with a dwell-time of 30 min. at each temperature (MIL standard 833) Glass Schematic of daisy-chain PI Cu Resistance e(ω) 4.00 1_ 1 3.50 1_2 1_3 3.00 2_1 2.50 2_2 2_3 2.00 2_4 1.50 2_5 3_1 1.00 3_4 0 200 400 600 800 1000 Cycle No significant resistance changes after 1000 cycles Double side thick polymer worked as buffer to relax stress created by CTE mismatch 15

Conformal Cu Plating Electrical Test 354nmTiW; 1950nmCu (both sides) + thin Cu layer plated Daisy-chain via test: 5000 vias = 45 Ohm 2500 vias = 23 Ohm Single via resistance sta of 15-18mOhm Metallized glass vias 16

Conformal Cu Plating Thermal Cycle Test Conformal vias 3 step cycling (-55C ; RT; 125C) Measurement of daisy-chain based on 100 vias Only 4 of 250 measured lines (each consist of 100 vias) show an open circuit 3 daisy-chains are measured without significant changes, which consist of 5000 vias Daisy-Chain- 5000 vias [Ohm m] 220 210 200 190 180 170 Sample 1 Sample 2 Sample 3 Resistivity of 160 150 0 500 1000 1500 2000 AATC (-55 / +125) [Cycle] 17

Conductive Paste Filling Benefit: Using CTE matched Cu for higher reliability and hermetic seal of TGV Capability for 50um diameter via filling with 130um via pitch CTE matched Cu 18

TOWARD TGV PANEL (FUTURE CHALLENGES) 19

Future Challenges Panel Level How to use? Who can use? Large size TGV substrate for Wide range of application Interposer, Wafer Level Further Test Data as a Package Production Technology RF, MEMS, Sensor 20

Roadmap for TGV Commercialization 500~ mm TGV Panel Panel base process: >500mm 30~100um thin glass Pre/Post process harmonization is under development 20 0um (40um) Substrate Size 150-200 mm φ Technology Today 6 8 (12) inch glass wafer with through holes 300 ~ 500um thick glass wafer Metallization by partner (optional) Compatible with Wafer Level Process Interposer, other electronic devices TGV Wafer Better yield & productivity 6 8 (12) inch glass wafer with through holes Metallization (optional) Compatible with Wafer Level Process RF, MEMS, Sensor and others 40-7 70um (150um m) TGV Diamete er (Pitch) 2014 2015 2016 2017 21

Message TGV Wafer: Stepping into Individual Development from Basic Research Needs further reliability test results. TGV Panel: It can be the low cost solution for future interposer (needs infrastructure) TGV will create the Diverse Packaging not only for the interposer. 22

Nano/Micro Fabrication Technology Platform Nano Imprint Dry Etching Wet Etching Glass Forming Glass Drilling ultra thin glass (50um thick glass) Super-polishing Ra 0.2 nm 23

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