Encapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga ) Henry M.W. Sze, Marc Papageorge ASAT Limited 14th Floor, QPL Industrial Building, 138 Texaco Road, Tseun Wan, Hong Kong Phone : 852-2439 8700; Fax : 852-2407 4056 Email : henry_sze@qplhk.com ABSTRACT Market demand for thin, small and light electronic packaging is on the increase in recent years. This is primarily driven by space limitation in portable computing and consumer products. Fine pitch ball grid array (fpbga ) offers competitive alternative in package miniaturization to true chip scale packaging to meet such demands. This paper outlines encapsulation technique selection, characterization and reliability for fpbga. Both transfer molding and liquid encapsulation techniques were evaluated. Transfer molding technique was selected due to better encapsulation thickness control and lower array warpage. Mold simulation followed by actual mold process characterization was performed. Package reliability equivalent to or surpassed existing PBGA was achieved. The reliability results are outlined in this paper. 1.0 INTRODUCTION According to a semiconductor market research survey (BPA, 1997), 95% of integrated circuit packages had I/O of less than 100 in the year 1996. It is estimated that about 90% of integrated circuit packages in the year 2006 will have I/O count of less than 100. This represents a potential electronic packaging market in applying ball grid array technology to satisfy this increasing market demand in electronic package performance and miniaturization. Such demands are reflected on a recent survey (ETP, 1997) that chip scale package (CSP) will grow from 7 million units to 3.5 billion units in the year 2001. With market demand in high performance in smaller package, using near-chip and chip scale packages in these low I/O integrated circuit packages will satisfy these demands. Fine pitch ball grid array (fpbga ) is a LBGA/LFBGA family by JEDEC s definition. It is a near-chip scale package type. This is a cost-effective packaging option for integrated circuit devices for low I/O count ranging from 24 to 208 and for medium I/O count up to 400. This will meet today s market requirement for increase performance in small, light, and thin package configurations. Fine pitch BGA (fpbga ) utilizes established PBGA technology. It offers low risk for new product introduction and high potential for reduced time to market capability. It also offers die design revision flexibility without changing substrate design for surface mount. Moreover, it offers reliability equivalent to or surpasses current PBGA package reliability. ASAT LTD.,Hong Kong Page : 1
There are two major differences in assembly process flow (Figure 1) between PBGA and fpbga. They are the encapsulation process and the singulation process. ASAT s fpbga package utilizes a saw process to singulate multiple units from a large array whereas PBGA employs either punch or routing process on a single unit. Array package for fpbga is a challenge for encapsulation due to its thin mold profile, multi-chip arrangement and large array area. This paper outlines how the encapsulation process is selected and characterized. The package reliability performance is also included in this paper. Die Attach fpbga PBGA Wire Bond 1) Thin Mold Profile < 1.0mm 2) Large mold cavity 3) Multi-chip (4 to 48) Encapsulation 1) Mold thickness > 1.0mm 2) Small mold cavity 3) Multi-chip (3 maximum) Solder Bumping Multiple units in large array format singulated using a saw process. Singulation Single unit by either a routing process or a punch process. Figure 1 : Ball Grid Array Package Assembly Process Flow 2.0 ENCAPSULATION SELECTION Transfer molding and liquid encapsulation are the most common encapsulation techniques in BGA assembly today. Direct comparison of these two techniques is given in Table 1 below. Based on the information given, transfer molding is the obvious choice for array package encapsulation technique. Table 1 : Comparison between Transfer Molding and Liquid Encapsulation Transfer Molding Liquid Encapsulation 1. Thickness control Excellent Fair 2. Array warpage control Good (low shrinkage compound) Fair (glob top material) 3. Tooling cost Medium Low to none 4. Productivity (UPH) High Medium 5. Water adsorption (85%/85%RH/72 hrs) 0.3% 0.6% Encapsulation thickness control is superior in transfer molding methods when compared to liquid encapsulation. This is because epoxy thickness is predefined accurately by the mold cavity. Liquid encapsulation is less accurate in thickness control due to epoxy shrinkage of glob top material and machine dispensing accuracy. Assembly process benchmarking was conducted to characterize both encapsulation methods for array warpage control. Array warpage using liquid encapsulation was found to be four times greater than transfer molding. This is due to higher shrinkage properties of the glob top material. ASAT LTD.,Hong Kong Page : 2
The average warpage for transfer molding is 60 microns compared to 280 microns for liquid encapsulation on the same array size. This would create potential manufacturability and quality problems for solder sphere placement process as well as singulation process. Based on the above comparison, it is obvious transfer molding is the preferred encapsulation technique for array warpage control and finished product quality. 3.0 ENCAPSULATION CHARACTERIZATION Transfer molding of any cavity size and die configuration can be characterized by computational fluid dynamics (CFD) using commercially available simulation software packages. It is a useful engineering tool in establishing initial understanding of system variables effect on any physical and chemical process. Transfer molding process of array package such as fpbga can be characterized first by using such simulation software package. There are three significant factors to be evaluated in this array package simulation. They are die thickness, die size and die array arrangement. These were defined as critical factors at initial stage of product quality planning. They are critical because they may affect encapsulation process yield as a result of thin mold profile and large mold cavity size requirement of fpbga package. Having a thin mold profile would require die thickness to be thin. In today s semiconductor assembly industry, incoming wafer with 200-mm diameter and 450 µm thick is common. Wafer thickness requirement for thin profile transfer molding application can be first established using mold flow simulation software. Two die thickness with different die array configurations formed basis of mold flow simulation (FICO, 1997). Die with thickness greater than 410 µm is considered as thick. Die with thickness smaller than 410 µm is considered as thin. Figure 2 shows two different die array configurations to be used in the simulation. The effect of die thickness on mold compound flow can be noted in Figures 3 and 4. Figure 2 : Die Configurations for Mold Flow Simulation ASAT LTD.,Hong Kong Page : 3
Figure 3 : Mold Flow Pattern for Thick Die Configuration (4 Up Array) Figure 4 : Mold Flow Pattern for Thick Die Configuration (20 Up Array) Thicker die would reduce effective flow area above and around the die due to increased flow resistance. Figures 3 and 4 show exactly the modeled case. Mold compound flow was found to be slower in the area above the die when bottom gate is used compared to top gate. This unbalanced flow phenomenon was resulted from the die being thick in relation to the mold cavity. Therefore, a high possibility of external voids could occur above the die. This is as shown in Figure 5 where external voids are predicted. In order to eliminate encapsulation voiding, thinner die of (< 410 µm) is required for thin profile (< 1.0mm) molding. Simulation results using die thickness of less than 410 µm are shown in Figure 6 and 7. Both figures showed balanced flow front in comparison to Figures 3 and 4. The analysis was conducted for both top and bottom gating with similar results. Figure 8 shows no void occurrence above the die. This was confirmed by actual molding using thin die of less than 410 µm. ASAT LTD.,Hong Kong Page : 4
Figure 5 : Mold Voids Prediction for Thick Die Configuration Figure 6 : Mold Flow Pattern for Thin Die Configuration (4 Up Array) Figure 7 : Mold Flow Pattern for Thin Die Configuration (20 Up Array) ASAT LTD.,Hong Kong Page : 5
Figure 8 : Mold Void Prediction for Thin Die Configuration 4.0 PACKAGE RELIABILITY Package level reliability can be classified into six levels according to JEDEC standard (test method A112-A). Table 2 shows various JEDEC levels that the package can be classified under. This indicates floor life moisture susceptibility prior to surface mount operation. It is normally expected that semiconductor first level assembly operations would achieve at least a JEDEC level 3 classification for their products. Table 2 : JEDEC Moisture Sensitivity Level Classification JEDEC Floor Life Soak Requirement Level (Time) Time Condition 1 Unlimited 168 Hours 85 C / 85% RH 2 1 Year 168 Hours 85 C / 60% RH 3 168 Hours 192 Hours 30 C / 60% RH 4 72 Hours 96 Hours 30 C / 60% RH 5 24 Hours 48 Hours 30 C / 60% RH 6 6 Hours 6 Hours 30 C / 60% RH ASAT' fpbga utilizes existing PBGA assembly technology using the same construction material as PBGA. It is expected that fpbga package reliability will be able to meet at least equivalent to PBGA s JEDEC level 3 classification. It is also possible that it may surpass PBGA s JEDEC level 3 classification due to the smaller body size of fpbga (6mm to 15mm) in comparison to PBGA (23mm to 35mm). Table 3 shows ASAT s package level reliability achieved to date. It is as predicted that the fpbga package performed to minimum JEDEC level 3 classification. ASAT LTD.,Hong Kong Page : 6
Table 3 : Package Level Reliability Data (13mm 144, 10mm 100, 8mm 64 & 6mm 36) Condition Results (Fail / Pass) MSL 2 85 C / 60% RH / 168 Hrs 0 / 385 (5 lots) MSL 3 30 C / 60% RH / 192 Hrs 0 / 308 (4 lots) Autoclave 121 C / 100% RH / 168 Hrs / 1 ATM 0 / 693 Temperature Cycle -65 C to 150 C, 1000 cycles 0 / 693 Thermal Shock -65 C to 150 C, 300 cycles 0 / 693 HTSL 150 C, 500 Hrs 0 / 693 HAST 130 C / 85% RH / 50 and 200 Hrs 0 / 693 5.0 CONCLUSION fpbga package is a near chip-scale package. It was developed from existing PBGA assembly technology using the same construction material. The challenge for encapsulation was in its thin mold profile and multiple chip configurations. Transfer molding methodology is the preferred choice for fpbga. This is due to enhanced encapsulation thickness control and reduced array warpage for a given area compared to liquid encapsulation method. When thin die of less than 410 µm is used, the transfer molding process is favored. This is due to a balanced flow front, reduced flow turbulence and zero voiding. The package level reliability for the fpbga achieved a minimum of JEDEC level 3 and passed all the required environmental tests. 6.0 REFERENCES Advanced IC Packaging Markets and Trends, Electronic Trend Publication, California, November 1997. BPA Survey, ESEC Road show Booklet, October 1997. Mcllellan, N., Papageorge, M., Fan, N., CSP Reliability : Meeting the Challenges, Advanced Packaging, February 1998. Roerdink, G., ASAT CSPBGA Simulation Report, Fico Molding Systems BV, November 1997. Sze, H., FPBGA Molding Process Evaluation, ASAT Internal Report, January 1998. ASAT LTD.,Hong Kong Page : 7