A Cofired Bump Bonding Technique for Chip Scale Package Fabrication Using Zero X-Y Shrinkage Low Temperature Cofired Ceramic Substrate

A Cofired Bump Bonding Technique for Chip Scale Package Fabrication Using Zero X-Y Shrinkage Low Temperature Cofired Ceramic Substrate Minehiro Itagaki, Nobuhiro Hase, Satoru Yuhaku, Yoshihiro Bessho and Kazuo Eda Matsushita Electric Industrial Co., Ltd. Device Engineering Development Center 1006, Kadoma, Kadoma-shi Osaka, 571 Japan Phone: +81-6-900-9628 Fax:+81-6-906-4587 e-mail: itagaki@drl.mei.co.jp Abstract A cofired bump bonding technique was developed, which was advanced flip chip bonding technique applied to the fabrication of Chip Scale Packages (CSPs). The bumps were formed to cofire on the substrate simultaneously when the zero x-y shrinkage Low Temperature Cofired Ceramic (LTCC) substrate was fabricated. The resultant cofired bumps had an uniform shape, and could arrange in 0.25mm pitch. The interconnection between the cofired bump and the electrode of an LSI chip was carried out using a conductive adhesive. The resulting bonding resistance was about 9 mw. Key words: Cofired Bump, Bump Interconnection, CSP, and Zero X-Y Shrinkage LTCC. 1. Introduction According to the demand for downsizing of the electronic devices, the technology development of miniaturizing semiconductor packages has been made briskly. CSPs appeared in the market in 1995, and currently the amount of CSP production is increasing radically. There are several types of CSP, for example, a molded type, an interposer type, and a lead-frame type 1. Among these types, the interposer type CSP has a simple structure, and it requires only two basic technologies for fabrication of CSPs. They are a bare chip mounting technology and an interposer substrate fabrication technology. In an interposer substrate technology, a ceramic substrate is suitable for the flip chip bonding, due to its good mechanical and chemical stability, good thermal conductivity and the Coefficient of Thermal Expansion (CTE) close to that of LSI chips. In addition, the LTCC substrate consisting of glass and ceramic has an excellent flatness and can use a low resistivity conductor (such as Cu or Ag). Furthermore, the glass-ceramic material can obtain the zero x-y shrinkage substrate, so the LTCC substrate realizes the high density substrate 2-4. In a bare chip mounting technology, flip chip bonding realizes downsizing of CSP and low impedance of the interconnection between the bare chip and the interposer substrate. Among the flip chip bonding techniques, Stud Bump Bonding (SBB) technique has an excellent reliability of the interconnection due to the flexible interconnection between the Au stud bump on an LSI chip and the electrode of the interposer substrate has been realized using a conductive adhesive 5-8. In addition, the bump formation method in SBB flip chip bonding technique is using a conventional wire bonding method, so the electrodes of the LSI chip have to be assigned peripherally on the chip. Furthermore, the bumps are formed one by one on the LSI chip, so it spends much time if there are many I/O counts on the LSI chip. The bump cannot be formed on the active area of an LSI chip by the wire bonding method. On the other hand, a solder bump can be formed on any area of an LSI chip, and all bumps can be formed collectively 9. However, the reliability of the solder bump 46

A Cofired Bump Bonding Technique for Chip Scale Package Fabrication Using Zero X-Y Shrinkage Low Temperature Cofired Ceramic Substrate interconnection is not superior to that of the SBB interconnection, due to its rigid joining between an LSI chip and a substrate and of the formation of the intermetallic compound between the solder and the electrode of substrate or LSI chip10. In addition, the solder forming bumps are not designed for the environment, safety and health issues, since most of the solders contain lead. This paper describes the development of a new bump formation method for the fabrication of the area array flip chip bonded CSP using zero x-y shrinkage LTCC substrate. 2. Bump Formation Method The bumps were formed on the ceramic substrate collectively using a zero x-y shrinkage substrate technology, and also the bumps were cofired on the substrate simultaneously when the zero x-y shrinkage substrate was fabricated. Therefore, the newly developed bump is called the cofired bump. In the case of fabricating the zero x-y shrinkage substrate, the x-y shrinkage is prohibited by the frictional forces produced between the LTCC substrate material and the no shrinkage material in sintering. The glass ceramic composite is suitable for the LTCC substrate material. Therefore, the resulting sintering shrinkage produces only to the z direction by softening of the glass component in the glass-ceramic material. Properties of the zero x-y shrinkage substrate, for example a sintered density and a flexural strength, are almost equal to that of a conventional substrate. plasticizer by the doctor blade casting method. The diameters of the glass-ceramic particle is about 2µm. (2) The glass ceramic green sheets were punched out to form viaholes for the electrical connection between conductive layers. Then, the via-holes were filled with the via conductor paste. Wiring patterns were formed using internal and external conductor pastes by screen printing technique. Also, the alumina contact sheet was punched out to form via-holes for the formation of the cofired bump. Then, the via-holes were filled with the via conductor paste for the cofired bump. The via conductor paste, the internal conductor paste, and the external conductor paste for the zero x-y shrinkage LTCC substrate were used. The conductive component is Ag. The same paste as the via conductor paste was used for the cofired bump. (3) The green sheets and the contact sheets were stacked to be laminated sandwiching the glass ceramic green sheets between two alumina contact sheets with no gap. At this time, the alumina contact sheet formed the via-holes filled with the paste was used on one side of the glass ceramic green sheet laminate. Then, the lamination was performed under a pressure of 200kg/cm2, a temperature of 80 C for 1 minute. (4) The organic binder in the laminate was removed and the laminate was sintered at 900 C in air atmosphere. After sintering, alumina was removed easily from both sides of the sintered substrate, since the alumina contact sheets are not sintered at 900 C and due to the presence of a cluster of the alumina powder. However, the conductor paste for the cofired bump in the alumina contact sheet is sintered, and the cofired bumps have been formed on the zero x-y shrinkage LTCC substrate. Figure 1. Fabrication process chart. Figure 2. SEM image of cofired bumps assigned in 0.5mm pitch. Figure1 shows the fabrication process chart of the zero x-y shrinkage substrate with the cofired bumps. The zero x-y shrinkage In this way, the zero x-y shrinkage substrate with the cofired substrate is fabricated using a conventional green sheet stacking bumps was obtained. Figure 2 shows Scan Electron Micrograph method. The glass-ceramic composite consisted of CaO-B2O3-SiO2 (SEM) image of the cofired bump. Each bump has a columnar shape. glass, and Al2O3 was used as the LTCC substrate material, which The diameter of the bump is about 0.2 mm, the height is about 0.18 crystallizes labradolite in firing at above 850 C, and alumina was mm, and the pitch of the cofired bump assignment is 0.5 mm in used as the no shrinkage material. Figure 2. For the fine pitched interconnection, the cofired bump can The procedure of fabrication of the zero x-y shrinkage substrate be formed in 0.25 mm pitch. The cofired bumps assigned in 0.25 with the cofired bump can be described as follows, mm pitch are shown in Figure 3. The diameter of the bump is about (1) The glass ceramic green sheets were made of the glass-ce0.1mm. compositejournal powder,ofacrylic resin binder, a solvent, and a Theramic International Microcircuits and Electronic Packaging, Volume 21, Number 1, First Quarter 1998 (ISSN 1063-1674) 47

Intl. Journal of Microcircuits and Electronic Packaging bump on Al electrode of an LSI chip was about 50gf, the cofired bump has a strong sufficient adhesion strength. Figure 5 shows the I-V characteristic of the cofired bump material. For measuring the I-V characteristic, a bulk of the columnar shape using the cofired bump material was fabricated. As a result of voltage measurements, with currents varying from 1mA to 200mA applied to the measuring sample, the cofired bump material exhibited the ohmic conductivity. The volume resistivity of the cofired bump material was about 2.0 10-4 W cm. Figure 3. SEM image of cofired bumps assigned in 0.25mm pitch. 3. Properties of Cofired Bump The height distribution of the cofired bump, the adhesion strength of the obtained bump, and the I-V characteristic of the cofired bump material were measured. Figure 4 shows the height distribution of the cofired bump. As the result of using an alumina contact sheet of about 0.1mm thickness for fabricating the cofired bump, the average height of the cofired bump was about 0.08mm. The distribution of the height was ±5µm. Such a distribution causes the distribution of the thickness of the green sheets and the warp of the substrate. Therefore, the coplanarity of the top of cofired bumps was about 10µm. The coplanarity of the top of cofired bumps was processed less than 5µm by polishing. Figure 5. I-V characteristic of cofired bump material. 4. Cofired Bump Bonding Method The interconnection between the top of cofired bumps and the surface of the electrodes on an LSI chip was carried out using a conductive adhesive, as well as the SBB technique. Figure 6 shows the structure of the bonding portion. As the cofired bumps are formed on the substrate, and the conductive adhesive on the top of the cofired bump adhering to the surface of Al electrode of an LSI chip directly, it is necessary to coat the surface of Al electrode with a precious metal layer. Figure 4. Height distribution of cofired bump. The adhesion strength on the LTCC substrate was measured using BONDTEST-30 (Keller Technology Corporation). The adhesion Figure 6. Structure of bonding portion. strength of the cofired bump was about 100gf, when the diameter of the cofired bump was 0.1mm. As the adhesion strength of Au stud 48

A Cofired Bump Bonding Technique for Chip Scale Package Fabrication Using Zero X-Y Shrinkage Low Temperature Cofired Ceramic Substrate The flip chip bonding process chart is shown in Figure 7. The procedure can be summarized as follows, (a) cofired bumps after leveling height. (b) cofired bumps with conductive adhesive. (3) LSI chip was mounted onto the tip of the obtained bumps. The mounting load for LSI chip is less than 1g/bump since there is no damage on the chip. The properties of the conductive adhesive is shown in Table 1. Epoxy resin, which is flexible over a wide range of temperature, was used as an organic binder of conductive adhesive. This organic binder is a kind of bisphenol-a type with high molecular weight. Flake Ag powder was used as a conductive filler for high conductivity. Under a thermal stress condition, this conductive adhesive is deformed and the thermal stress is relaxed, so the flip chip bondability is kept stable. Table 1. Properties of conductive adhesive. Figure 7. Flip chip bonding process chart. (1) The zero x-y shrinkage LTCC substrate with cofired bumps was fabricated. The height of the obtained cofired bump was leveled by a polishing process. (2) Only the tips of the cofired bumps were dipped in a layer of the conductive adhesive, to transfer the conductive adhesive onto the top of each bump collectively. Figure 8 shows SEM micrograph of the cofired bumps onto which the conductive adhesive has been transferred. Organic Binder Conductive Filler Viscosity (at 25 C) Volume Resistivity Flexible Epoxy Resin Ag 30 Pa s 1.0X10-4Ω cm (4) After curing of the conductive adhesive, an electrical inspection can be carried out. If a defective LSI chip is found in the electrical inspection, it is repaired with the conductive adhesive in the curing state. The defective LSI chip can be removed easily at room temperature, and can be replaced with a new LSI chip without necessity of cleaning the tip of cofired bumps. Such an inspection and repair methods have permitted a remarkable increase in the yield of flip chip bonding. (5) The gap between the LSI chip and the substrate was filled with epoxy underfill resin for enhancement of stability of the flip chip bondability. The underfill resin was cured to complete the flip chip bonding process. The properties of the underfill resin is shown in Table 2. The epoxy resin is made of an epoxy / acid anhydride type, so it has strong adhesion force against substrates and a low moisture absorption. The temperature coefficient of expansion (CTE) can be controlled as low as about 30ppm / C with 60 % by weight filler content of globular SiO2. In spite of high filler content, a viscosity is as low as 5 Pa s. In addition, the glass transition temperature (Tg) of the underfill resin is as high as 140 C. The conductive adhesive and the underfill resin are the same materials used in the SBB technique. Table 2. Properties of underfill resin. Resin Viscosity (at 25 C) TCE Tg Epoxy-Acid anhydride 5 Pa s 30 ppm/ C 140 C Figure 8. SEM image of cofired bump with conductive adhesive. 49

Intl. Journal of Microcircuits and Electronic Packaging The interconnection between the top of cofired bumps and the surface of electrodes on an LSI chip was carried out using a conductive adhesive, and the gap between the substrate and the chip was filled by an underfill resin, as well as the SBB technique. The resulting bonding resistance was about 9 mw. This way, the bumps are formed to cofire on the substrate collectively in area array assignment, so it is available for the CSP for next generation devices. Acknowledgment Figure 9. SEM image of bonding portion. The authors would like to thank Mr. Ishida, the Head of Device Engineering Development Center of Matsushita, for his kind and appropriate suggestions for the present study. The authors also thank all other persons who participated in this study. 5. Flip Chip Bondability The bonding resistance was measured using the four probes method. The bonding resistance means the total resistance of the cofired bump and the conductive adhesive. The zero x-y shrinkage LTCC substrate with cofired bumps whose pitch is 0.5mm and the test chip with Au coated electrode were used. The thickness of the substrate and test chip was about 0.4mm, respectively. As a result of measurement, the mean value of the bonding resistance was about 9 mw, and its distribution was about ±2 mw. On the other hand, the bonding resistance was calculated. As the volume resistivity of the cofired bump is 2.0 10-4 W cm, the calculated resistance of the cofired bump whose diameter is 0.2mm and whose height is 0.1mm, is 6.37 mw. And as the volume resistivity of the conductive adhesive is 1.0 10-4 W cm, the calculated resistance of the conductive adhesive whose diameter is 0.2mm and whose height is 0.015mm, is 0.48 mw. Therefore, the calculated bonding resistance is 6.85 mw. Though, there was a little wide distribution in the measured bonding resistance, the minimum value of measured bonding resistance is almost equal to the calculated bonding resistance. It is considered that the distribution of the measured bonding resistance depends on the coplanarity of the top of cofired bumps. 6. Summary References 1. J. H. Lau, Ball Grid Array and Chip Scale Package Technology, Proceedings of the Second International Symposium on Ball Grid Array Technology, Minneapolis, Minnesota, 1996. 2. H. Nishikawa, M. Tasaki, S. Nakatani, Y. Hakotani, and M. Itagaki Development of Zero X-Y Shrinkage Sintered Ceramic Substrate, Proceedings of the 1993 Japanese International Electronic Manufacturing Technology Symposium, Kanazawa, Japan, pp. 238-241, 1993. 3. M. Itagaki, K. Miura, Y. Hakotani, S. Yuhaku, Y. Bessho, S. Nakatani, M. Tsukamoto, T. Ishida, and H. Nishikawa Zero X-Y Shrinkage Multilayered Ceramic Substrate, Proceedings of the 26th International Symposium on Microelectronics, ISHM 93, Dallas, Texas, pp. 221-225, 1993. 4. M. Itagaki, Y. Bessho, K. Eda, and T. Ishida A Zero X-Y Shrinkage LTCC Substrate Using Ag and AgPd Conductors for Flip Chip Bonding, Proceedings of the 29th International Symposium on Microelectronics, ISHM 96, Minneapolis, Minnesota, pp. 55-59, 1996. 5. Y. Bessho, Y. Tomura, Y. Hakotani, M. Tsukamoto, T. Ishida, and K. Omoya A Stud- Bump- Bonding Technique for High Density Multi-Chip- Module, Proceedings of the 1993 Japanese International Electronic Manufacturing Technology Symposium, Kanazawa, Japan, pp. 362-365, 1993. 6. Y. Bessho, Y. Tomura, T. Shiraishi, M. Ono, T. Ishida, and K. Omoya Advanced Flip Chip Bonding Technique to Organic Substrate, Proceedings of the 28th International Symposium on Microelectronics, ISHM 95, Los Angeles, California, pp. 359-364, 1995. 7. Y. Tomura, Y. Bessho, T. Shiraishi, M. Itagaki, S. Yuhaku, T. Ishida, and T. Ohbayashi Advanced Flip Chip Bonding Technique for MCM-L, Proceedings of First Pan Pacific Micro- A new bump formation method was developed using zero x-y shrinkage LTCC substrate, which is applied to the fabrication of area array flip chip bonded CSPs. The newly developed bump was formed to cofire collectively when the zero x-y shrinkage substrate was fabricated. The shape of the obtained bump was uniform, and the bumps could be assigned in 0.25mm pitch. electronics Symposium, Honolulu, Hawaii, pp. 125-131, 1996. 50

A Cofired Bump Bonding Technique for Chip Scale Package Fabrication Using Zero X-Y Shrinkage Low Temperature Cofired Ceramic Substrate 8. T. Shiraishi, K. Amami, S. Yuhaku, Y. Bessho, K. Eda, and T. Ishida Stud-Bump Bonding Technique onto an Advanced Organic Substrate for MCM-Ls, Proceedings of the 6th International Conference and Exhibition on Multichip Modules, MCM `97, Denver, Colorado, pp. 109-114, 1997. 9. Rao R. Tummala and Eugene J. Rymaszewski Microelectronics Packaging Handbook, Nikkei BP, Japanese Translation Copyright, Chapter 6, 1991. 10. M. Ono, Y. Tomura, Y. Bessho, T. Shiraishi, K. Eda, and T. Ishida Bonding Resistance of SBB Technique, Proceedings of the Second Pan Pacific Microelectronics Symposium, Maui, Hawaii, pp. 355-362, 1997. About the authors Minehiro Itagaki was born in Osaka, Japan, in 1961. He received a B.S. Degree in Applied Chemistry from Himeji Institute of Technology, Japan, in 1984 and an M.S. Degree in Process Engineering from Osaka University, Japan, in 1986. Since joining Matsushita Electric Industrial Co.,Ltd., Japan in 1986, he has been engaged in the research and development of the multilayered ceramic substrate. His current research interests include the packaging technology for Multichip Modules and Chip Scale(Size) Packages. He is a member of the Microelectronics and Packaging Society, IMAPS Japan. Nobuhiro Hase was born in Hyogo, Japan, in 1971. He received his B.S. and M.S. Degrees in Mechanical Engineering from Kyoto University, Japan, in 1994 and 1996, respectively. He joined Matsushita Electric Industrial Co.,Ltd. in 1996, and he has worked at Packaging Technology Group of Device Engineering Development Center. Satoru Yuhaku was born in Osaka, Japan, in 1943. Since joining Matsushita Electric Industrial Co., Ltd., Japan in 1959, he had been engaged in the research and development of the dielectric ceramic materials and the multilayered ceramic substrate. His current interests include the packaging technologies for Multichip Modules and Chip Size Packages. Yoshihiro Bessho was born in Okayama, Japan, in 1960. He received a B.S. Degree in Electrical Engineering from Okayama University, Japan, in 1983. Since joining Matsushita Electric Industrial Co.,Ltd., Japan in 1983, he has been engaged in the research and development of the mounting technology of LSI chip for IC cards. His current interests include the Flip Chip mounting technology for Multichip Modules. Kazuo Eda was born in Mie, Japan, in 1946. He received the B.S. and M.S. Degrees in Electronics from Nagoya University, Japan, 1969 and 1971, respectively. He received the Ph.D. Degree in electronics from Kyoto University, Japan, in 1980. Since joining the Wireless Research Laboratory of the Matsushita Electric Industrial Co.,Ltd., Japan in 1971, he did research and development work on electronic ceramic devices. From 1983 to 1984, he was a visiting scholar with the University of California, Santa Barbara. Since 1983, he has been engaged in the research and development of optical and microwave devices. He is a member of the Japan Society of Applied Physics. 51