Cree EZ-p LED Chips Handling and Packaging Recommendations

Similar documents
LGIT CSP Application NOTE. (Lighting)

Choosing the Correct Capillary Design for Fine Pitch, BGA Bonding

5W White SPHWHTA3N500

Mixed Attachment Technology Studies in RF & Optoelectronic Packages Requiring High Accuracy Placement

Hitachi A 64Mbit (8Mb x 8) Dynamic RAM

10 Manor Parkway, Suite C Salem, New Hampshire

Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes. Jason Chou and Sze Pei Lim Indium Corporation

Innovative MID Plating Solutions

Recent Advances in Die Attach Film

Plasma for Underfill Process in Flip Chip Packaging

Failure Modes in Wire bonded and Flip Chip Packages

LED Die Attach Selection Considerations

Features. = +25 C, 50 Ohm System

Lattice isplsi1032e CPLD

HBLED packaging is becoming one of the new, high

Rockwell R RF to IF Down Converter

National Semiconductor LM2672 Simple Switcher Voltage Regulator

IPC-AJ-820A Assembly and Joining Handbook. The How and Why of All Things PCB & PCA

Cree XLamp ML-B LEDs. Table of Contents. CLD-DS39 Rev 7I. Product family data sheet

KGC SCIENTIFIC Making of a Chip

BONDING OF MULTIPLE WAFERS FOR HIGH THROUGHPUT LED PRODUCTION. S. Sood and A. Wong

Selection and Application of Board Level Underfill Materials

Quality and Reliability Report

TECHNOLOGIES FOR APPLYING FLUIDS IN SEMICONDUCTOR PACKAGING

Freescale Semiconductor Tape Ball Grid Array (TBGA) Overview

Dallas Semicoductor DS80C320 Microcontroller

Guide for Tantalum Solid Electrolyte Chip Capacitors with Polymer Cathode

bans the use of lead, mercury, cadmium, hexavalent chromium and polybrominated biphenyls (PBB) or polybrominated diphenyl ethers (PBDE).

Intel Pentium Processor W/MMX

Prime Technology Inc.(PTI), Engineering Capability

GaAs MMIC Space Qualification

UBSC/ULSC 60 + GHz Ultra Broadband Silicon Capacitors Surface Mounted

MRSI-175Ag Epoxy Dispenser

TMS320C6000 BGA Manufacturing Considerations

3 Thermally Conductive Tapes

Bonding Tool Design Choices for Wire Bondable CSP and µbga Packages

Guide for Molded Tantalum Capacitors

YOUR Strategic TESTING ENGINEERING CONCEPT SMT FLIP CHIP PRODUCTION OPTO PACKAGING PROCESS DEVELOPMENT CHIP ON BOARD SUPPLY CHAIN MANAGEMENT

Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications

Basic PCB Level Assembly Process Methodology for 3D Package-on-Package

3D-WLCSP Package Technology: Processing and Reliability Characterization

14. Designing with FineLine BGA Packages

Quality and Reliability Report

COB Application Note Ver. 1.0 Release Date : 25-Feb-17. Chip on board For Lighting

SGS-Thomson M17C1001 1Mb UVEPROM

Description. Applications

Posistor for over current protection PRG SERIES BC-E0273H PRG21BC***MM1RA SERIES

Using Argon Plasma to Remove Fluorine, Organic and Metal Oxide Contamination for Improved Wire Bonding Performance

Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply

Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip

Lead Free Surface Mount Technology. Ian Wilding BSc Senior Applications Engineer Henkel Technologies

Design for Flip-Chip and Chip-Size Package Technology

23 rd ASEMEP National Technical Symposium

Dow Corning WL-5150 Photodefinable Spin-On Silicone

FOR OFFICIAL USE ONLY

Bonded Neo Magnetization Guide

Initial Reliability Requirements

Teaching Lab Course on Electronic Packaging and Materials

An Innovative High Throughput Thermal Compression Bonding Process

Topview 5630 Red SMD LED

FIVE STAR PRODUCTS, INC. (800)

SMD Technical Data Sheet High Power Green LED LH5070GCZ1.LW01

Development of System in Package

UVTOP280-FW-SMD. Description. Maximum Rating (T CASE = 25 C) Electro-Optical Characteristics (T CASE = 25 C, I F = 20 ma)

Effect of Die Bonding Condition for Die Attach Film Performance in 3D QFN Stacked Die.

Reference Only. 2.Part Numbering (ex) NF Z 5B BW 2R9 L N 1 0 L

Following this guideline enables proper treatment of the relays during the critical phase in the relay life.

Ceramos Gen 5 Details on Handling and Processing Application Note

Challenges for Embedded Device Technologies for Package Level Integration

Anti-collapse Reflow Encapsulant Technology for FCOF. IMAPS Flip-Chip 2003, Austin TX

Tapes. Reliable. Solar Industry. for the. 3M Tapes for Solar Panel Fabrication

PCB Technologies for LED Applications Application note

Three-Dimensional Molded Interconnect Devices (3D-MID)

Guide for Conformal Coated Tantalum Capacitors

Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes

SECTION 07530CP EPDM MEMBRANE ROOFING

Development of an Low Cost Wafer Level Flip Chip Assembly Process for High Brightness LEDs Using the AuSn Metallurgy

Packaging Commercial CMOS Chips for Lab on a Chip Integration

Quality Starts With Me

Quality in Electronic Production has a Name: Viscom. System Overview

New Technology for High-Density LSI Mounting in Consumer Products

ELECTRICAL-OPTICAL CHARACTERISTICS (T C = 25 C) VALUE MIN. TYP. MAX.

Hot Pin Pull Method New Test Procedure for the Adhesion Measurement for 3D-MID

7343M/BAC3-ATVA/C5. Lamp

Modified Tool for Developmental Analysis and Real Time QRA Probe Card and Socket Results

Chip NTC Thermistor for temperature sensor and temperature compensation 0402 size

Pyramid Probe Card: P800-S Online Cleaning

Motorola PC603R Microprocessor

IMPLEMENTING PROPER PROCEDURES AND THE USE OF ADVANCED FLUX VERIFICATION TOOLS FOR A ROBUST WAVE SOLDERING OPERATION

Copper Wire Packaging Reliability for Automotive and High Voltage

Reliability of Interconnects in LED Lighting Assemblies Utilizing Metal Clad Printed Circuit Boards Stefano Sciolè BDM I.M.S.

Brazing & Soldering. Brazing, Soldering, Adhesive-Bonding and Mechanical-Fastening. Brazing 12/2/2009

Typical Properties. THERMATTACH Dielectric Thickness Thermal Material Strength Carrier Color inches (mm) Impedance Features/Typical Applications (Vac)

The Packaging and Reliability Qualification of MEMS Resonator Devices

SYGT/S530-E2 LAMP. Features. Description. Applications. Device Selection Guide. Choice of various viewing angles

Heritage Quality Performance

Bridging Supply Chain Gap for Exempt High-Reliability OEM s

1 Thin-film applications to microelectronic technology

Offshore Wind Turbines Power Electronics Design and Reliability Research

Transcription:

Cree EZ-p LED Chips Handling and Packaging Recommendations INTRODUCTION This application note provides the user with an understanding of Cree s EZ-p p-pad up (anode up) LED devices, as well as recommendations on handling and packaging. Further details regarding performance and dimensional specifications of EZ-p LED chips can be found at http://www.cree.com/led-chips/products. TABLE OF CONTENTS EZ-p LED STRUCTURE... 2 EZ-p LED CHIP HANDLING... 3 Die Ejection... 3 Collets... 4 EZ-p LED CHIP DIE ATTACH... 5 Eutectic/Solder Attach... 5 Flux... 5 Reflow... 6 Adhesive Attach... 7 EZ-p LED WIRE BONDING... 8

EZ-p LED STRUCTURE 2 A cross-sectional schematic diagram of an EZ-p LED is shown below. The EZ-p LED has a vertical structure with topside Au bond pad anode (+) terminals and an Ohmic metal cathode (-) on the bottom of the silicon substrate. The epitaxial emitting layer is metallically bonded to the silicon substrate and the surface of the emitting area is passivated. For more detailed dimensional information and operational characteristics for the full line of EZ-p LEDs please consult the specification documents at the Cree website: http://www.cree.com/led-chips/products.

EZ-p LED CHIP HANDLING 3 In general, industry standard handling procedures can be used with the EZ-p LED. Both coaxial and radial lighting sources (ring or fiber lights) are recommended for pattern recognition systems in automated pick and place or bonding processes. Low angle side lighting may also be used to provide improved contrast. The following guidelines include recommendations to maintain optimal performance: Minimize contact between metallic fixtures, equipment, tweezers, or other hard objects and the emitting surface or the edge of the emitting layer, as excessive contact force can damage the device, leading to electrical leakage and reduced optical output. If possible, avoid application of tapes or adhesives to the emitting surface. Tape residue can contaminate the textured surface, leading to reduced light extraction efficiency or poor lamp encapsulant adhesion. Die Ejection EZ-p LED chips are shipped from Cree with the epitaxial side up on the carrier tape. The application of excessive force during the die ejection process must be avoided. To minimize the risk of damage Cree recommends the following: Observe the following ejector pin minimum tip radius guidelines (Table 1) EZ-p Chip Minimum Tip Radius ( m) Chip dimension < 400 m 22 400 m Chip dimension 1000 m 50 Chip dimension > 1000 m 125 Table 1: Recommended minimum ejector pin tip radius Minimize ejector pin speed and travel Synchronize pin travel with collet motion to minimize the force applied to the chip If possible, adjust the ejection process to prevent pin penetration of the tape film

Collets Rubber collets and handling fixtures with hardness in the approximate range of 80 (Shore A), or equivalent, are recommended. Harder plastic collets may also be used, in which case minimization of die placement or bonding parameters (forces) is recommended. The selection of bonding force level should be confirmed through reliability testing. A variety of rubber and plastic collet materials, covering a range of use temperatures, are available for use with EZ-p LEDs, including Teflon, Vespel, silicone rubber, and Viton. 4 Recommended collet inner diameters (ID) for use with the corresponding EZ-p chip designs are listed in Table 2. Customers should contact the collet manufacturers for recommendations on designs specific to their application and die bonding equipment. Supplier information is provided following Table 2. For more information or questions regarding collet recommendations please contact Cree www.cree.com. Collet ID EZ-p Chip Collet ID ( m) Chip dimension < 400 m 200-210 400 m Chip dimension < 700 m 400-420 700 m Chip dimension 1400 m 750-770 Chip dimension > 1400 m 1500-1520 Table 2: Collet ID recommendations Supplier Information Micro Mechanics (www.micro-mechanics.com): Singapore, China, Taiwan, Japan Small Precision Tools (SPT) (www.smallprecisiontools.com): USA, Singapore, China, Japan

EZ-p LED CHIP DIE ATTACH 5 Eutectic/Solder Attach For all solder attach processes the following guidelines must be observed: The maximum reflow process conditions for EZ-p LEDs are 325 C for 5 seconds. This process window is adequate for the reflow of the intrinsic die attach metallization and a range of other solders, including Pb-free solders. It is recommended that temperature profiles be verified by direct measurement at the LED chip to ensure that the maximum process limits are not exceeded. If plasma cleaning is a customer consideration, Cree recommends that the devices not be exposed to Hydrogen plasmas. Addition of Hydrogen to other types of plasma should be minimized. Minimal pressure should be applied to the EZ-p chip during the soldering process. Pressure eutectic attach of EZ-p LEDs is not a Cree recommended process, however if the customer elects to use this process, then a maximum bonding force of 50 grams is recommended. Complete solder underfill of the EZ-p chip is required, especially at the edges of chips with corner bond pads, to provide a rigid support to the chip for subsequent wirebonding. Flux Recommended fluxes for EZ-p flux eutectic attach (FEA) are listed in Table 3 along with the manufacturer recommended cleaning agents. Alternative fluxes should be evaluated by the customer, as appropriate. Flux residue should be cleaned prior to encapsulation. Follow the flux manufacturer s recommended cleaning process or contact Cree for additional information (www.cree.com). Flux should be dispensed onto the substrate such that the EZ-p LED chip s anode metallization will have complete coverage. Avoid using excessive flux to prevent die movement during reflow. Flux quantity may be optimized by seating the EZ-p LED chip into the dispensed flux during die placement and minimizing the amount of flux displaced around the base of the die. The required quantity of dispensed flux may vary depending on the type of flux used and EZ-p chip size. Flux Cleaning Solution BIOACT EC7-R or 10% Alpha 2110 Alpha Metal UP78-PT1 saponifier with water. Indium Tac007 Kyzen Ionox I3302 Arakawa WHP-002/WHP-002 LED PINE Alpha series Table 3: Recommended fluxes and cleaning agents When using the intrinsic die attach metal for FEA Cree recommends the following guidelines for substrate metal finish to enable good surface wetting and uniform metal bond formation. Design Item Dimension ( m) Substrate Roughness Ra ~0.7, Rz < 2 Table 4: Substrate surface finish parameters

Temperature Reflow 6 The reflow profile for EZ-p LED chips can vary depending on the thermal mass of the leadframe or substrate. A schematic reflow profile is shown below. Cree recommends that the pre-heat, thermal soak and cooling profile conform to the flux manufacturer s recommendations. The target reflow zone for the intrinsic AuSn die-attach metallization should be limited to 300-320 C for less than 30 seconds. Reflow Soak Cool Preheat Time

Adhesive Attach 7 An electrically conductive adhesive must be used for EZ-p LED chips. It is important that the adhesive completely underfill the EZ-p LED chip, as this will ensure adequate die adhesion and will provide a rigid support to the chip during subsequent wirebonding. Adhesive should be visible around the entire periphery of the chip after die placement, especially at the edges of chips with corner bond pads, as shown below. Conductive adhesive should not contact the top surface of the chip as this can lead to electrical leakage and reduced device performance. Uniform adhesive underfill

EZ-p LED WIRE BONDING 8 EZ-p LED chips are designed for Au-ball wirebonding. Aluminum wedge bonding is not a Cree recommended process. It is important that the entire ball bond remain within the confines of the bond pad area and that no metal contact the emitting surface. Care must also be taken to prevent the wire capillary fixture from contacting the emitting surface as this can damage the LED junction. Several EZ-p LED chip designs feature bond pads adjacent to the edge of the junction mesa, therefore wirebonds must not exceed the bond pad area and lap over the edge of the mesa as this could lead to shunting leakage and/or junction damage. Correct Wrong Wrong The following guidelines should be observed for optimal wirebonding of EZ-p LED chips: Wirebonding force and ultrasonic power should be minimized Capillary geometry should be chosen to minimize the force required for ball formation Wirebonding process temperatures should be adjusted to minimize the required bonding forces/powers Absolute bonding parameters for EZ-p LED chips cannot be specified since bonding equipment and materials vary greatly. Table 5 lists suggested maximum parameters that may be used as a guideline for wirebond development. The customer is advised to optimize bonding parameters for their specific equipment, tooling, and bonding wire. Wirebonding Parameter * Bond Time Bond Force Ultrasonic Power Maximum Value 12 ms 40 g-force 100 mw * Parameters based on settings for ASM Eagle 60 Au-ball bonder using AW99 1.2 mil Au wire at 160 C bonding temperature, Gaiser 1572-17-437GM-20D capillary, 138kHz ultrasonic frequency. Table 5: Target wirebonding parameters