Thin Copper Seed Layers in Interconnect Metallization Using the Electroless Plating Process

Japanese Journal of Applied Physics Vol. 43, No. 8A, 004, pp. 5100 5104 #004 The Japan Society of Applied Physics Thin Copper Seed Layers in Interconnect Metallization Using the Electroless Plating Process Teen-Hang MEEN, Wen Ray CHEN, Chien-Jung HUANG and Chih-Jen CHIU Department of Electrical Engineering, Southern Taiwan University of Technology, 1 Nan-Tai St., Yung-Kang City, Tainan, Taiwan 70101, R.O.C. (Received October 14, 003; accepted April 1, 004; published August 10, 004) In this paper, we present a process for growing a Cu seed layer on a Ta/SiO /Si substrate using an electroless plating (ELP) process at an extremely low temperature (30 C). In this process, the activation treatment of the Ta/SiO /Si substrate was carried out by immersion in a PdCl /HCl solution prior to electroless Cu deposition. The optimum activation time for the substrate was clearly observed to be 7 min. The Cu seed layer was uniformly and smoothly deposited using a CuSO 4 concentration of 30 mm for 80 s with an average roughness of 14 nm under a thin film of 50 nm thickness. The grain size of the Cu seed layer was 34 nm. After annealing in hydrogen ambience at 50 350 C, the average roughness of the Cu seed layer was reduced to 4 nm. A proposed mechanism for the ELP of Cu seed layers on Ta/SiO /Si substrates is also presented. [DOI: 10.1143/JJAP.43.5100] KEYWORDS: copper, silicon, electroless plating, metallization, grain size 1. Introduction Scaling of ULSI circuits to critical dimensions less than 0.5 mm has focused considerable attention on the performance of metallization. Aluminum, which has been widely used for interconnection, has serious problems related to electromigration (EM), corrosion, and resistivity. Copper (Cu) improves electromigration resistance, a major concern in IC s long-term reliability, by as much as 50 times. Furthermore, copper has a lower resistivity, lower interconnection resistance-capacitance (RC) delay and higher resistance to electromigration and stress migration (SM) than aluminum. 1) The lower electrical resistance of copper leads to improved power consumption and device performance throughout the chip. Therefore, copper can be an alternative for interconnect metallization. Before bulk copper deposition on a dielectric layer, it is always necessary to deposit a thin seed layer. This provides nucleation sites for the bulk copper grain and film formations. With this conducting surface, copper atoms will stick very well to the wafer when the copper atoms migrate to the surface during electrochemical plating (ECP). If this seed layer is not present, there could be either deposition with poor uniformity or no deposition at all. Thus, an electroless plating (ELP) copper seed layer having a good bottom step coverage was used in this application. A copper seed layer can be deposited by physical vapor deposition (PVD),,3) chemical vapor deposition (CVD), 4 6) or electroless plating (ELP). 7 10) The resistivity of the copper seed layer by PVD is found near the bulk value (1:9 mcm). A major drawback of this deposition method is the poor step coverage. The CVD copper seed layer is not as dense as a high-temperature-deposited film and has higher resistivity (>:0 mcm). 11 13) This is due to the presence of high concentrations of carbon and hydrogen in the layer, which is from the growth of a gas source. One of the advantages of ELP is that it is a low-temperature process with a low tool cost, superior film uniformity, and good via/ trench filling capability. 14) An ELP thin seed layer typically improves the PVD step coverage near the via, and thus, increases the fill of a dual-damascence feature. 15) ELP deposition is normally performed at a low temperature to 5100 achieve a smooth layer surface, which is important for bulk copper deposition by electrochemical plating (ECP). A rough seed layer surface in the trench and via sidewall can cause a void during ECP bulk copper deposition. It is therefore very desirable to develop a method that can reduce the surface roughness of the seed layer on the dielectric layer. In this article, an improved technology for reducing the surface roughness of the seed layer is presented.. Experimental Procedure The substrates used in all experiments were 4 inch n-type (100) Si wafers on which a 900 A thick thermal silicon dioxide (SiO ) film was grown. Tantalum (Ta) was then deposited by electron beam evaporation (EBE) on silicon dioxide as a diffusion barrier layer and adhesion layer. These Ta/SiO /Si substrates were degreased and cleaned in acetone for 10 min by ultrasonic vibration and rinsed in deionized (DI) water. In the activation process, Ta was first wet etched with a 48% hydrofluoric acid (HF) solution for 1 minute to remove native oxides. This was then followed by the immersion of the etched substrates in an activation solution (PdCl : 0.05 g/100 ml and HCl: 0.5 ml/100 ml) for 1 9 min at room temperature. After each of the activation steps, an identical procedure using a DI water rinse was carried out to remove the residual chemical solution. Electroless Cu was then deposited on the activated Ta/ SiO /Si substrates at a temperature of 30 C. The compositions of the electroless bath are listed in Table I. The ph of the electroless bath is more than 13. The samples were finally rinsed in deionized water and dried with nitrogen gas. The surface element was analyzed by energy-dispersive X-ray diffraction (EDX, model S4100, Hitachi, Japan). The Table I. Solution compositions of electroless plating for Cu deposition. Component Concentration/pH CuSO 4 5H O 30 50 mm TEA 6 ml NaOH ph > 13 HCHO 9: 10 M DI-Water 1000 ml

Jpn. J. Appl. Phys., Vol. 43, No. 8A (004) T.-H. MEEN et al. 5101 surface roughness of the Cu seed layer was measured by atomic force microscopy (AFM, model METRIS-3345, Burleigh, USA). The sheet resistance of the electroless plating Cu seed layer was measured by a four-point probe method (model 80, 4-Dimension, USA). The grain size of the copper seed layer was estimated from its X-ray diffraction (XRD, model ATX-E, Rigaku, Japan) pattern. Evaluation was also carried out by scanning electron microscopy (SEM, model S4100, Hitachi, Japan) to study the surface of the Cu seed layer. 3. Results and Discussion The surface element of the PdCl activation process was observed by EDX, as shown in Fig. 1. For Ta/SiO /Si substrates, the palladium (Pd) content was increased with activation times up to 7 min that decreased after the maximum palladium content was reached. According to our experimental data, it is obvious that the Pd contents on Pd at % 3.5 1.5 1 0 4 6 8 10 Activation Time (min) Fig. 1. The surface element of the PdCl activation process was observed by EDX at the activation room temperature. the substrate measured by energy-dispersive X-ray diffraction (EDX) are 1.1,.15,.40,.88 and.81 at% for 1, 3, 5, 7 and 9 min, respectively. The activated surface morphologies are obtained by SEM, as shown in Fig.. According to these SEM images, one can note that the amount of Pd present on the substrate increases with activation time up to the 7 min mark. The phenomena and results are consistent with those in Fig. 1. Combining the information from Fig. 1 and Fig., the optimum activation time for the substrate was clearly observed to be 7 min because a Pd-rich surface substrate is also expected to improve the adhesion of the plated copper (Cu) film. 16) In order to understand the activation process, an equation is employed to explain a spontaneous reaction. The spontaneous reaction for the PdCl activation system is as follows Ta! Ta 5þ þ 5e EðvÞ ¼1:1 Pd þ þ e! Pd EðvÞ ¼0:915 Ta þ 5Pd þ! Ta 5þ þ 5Pd EðvÞ ¼6:815 The kinetics of the spontaneous reaction is normally determined by a Gibbs-free energy equation (1) 17) G ¼ nfeðvþ Where F is Farady s constant (or the charge for a mole of electrons), EðvÞ is the reduction potential and n is the number of electrons involved in a redox reaction. G is used to predict spontaneity under any condition, such as G < 0 representing spontaneity in the forward direction, G > 0 representing spontaneity in the reverse direction and G ¼ 0 representing equilibrium in the reaction. As G < 0 in this study, spontaneity was in the forward direction. Figure 3 shows the relationship of Cu film thickness and deposition time at a deposition temperature of 30 C. Deposition was propagated along the surfaces of the substrates. The surfaces were thoroughly covered by Cu films, which gradually increased in thickness with increasing ð1þ (a) (b) (c) (d) (e) (f) Fig.. SEM micrographs of palladium (Pd) activation Ta barrier layer with various activation times (a) 0 min, (b) 1 min, (c) 3 min, (d) 5 min, (e) 7 min and (f) 9 min at room temperature.

510 Jpn. J. Appl. Phys., Vol. 43, No. 8A (004) T.-H. MEEN et al. Cu Film Thickness (nm) 700 600 500 400 300 00 100 30mM CuSO 4 40mM CuSO 4 50mM CuSO 4 0 Average Roughness (nm) 00 175 150 15 100 75 50 5 30mM CuSO 4 40mM CuSO 4 50mM CuSO 4 Fig. 3. Cu film thickness versus deposition time with CuSO 4 concentration as a parameter for a deposition time of 80 seconds at a deposition temperature of 30 C. deposition time. The island phenomenon appears with a copper film deposited for less than 80 s. This is the reason why the copper thickness does not show up in Fig. 3. The thickness of the Cu film is increased with increasing CuSO 4 concentration. This is due to the fact that the higher reactant concentration causes a higher frequency of collision between the two reactants. This indicates that the higher the reactant concentration, the faster the nucleation. Figure 4 shows a cross-sectional scanning electron microscopy (SEM) micrograph of a sample deposited using a CuSO 4 concentration of 30 mm at a deposition temperature of 30 C for 80 s. The Cu seed layer thickness observed by SEM is consistent with that measured by the -step method. The Cu seed layer deposited by the electroless method is uniform and smooth on the Ta/SiO /Si substrate. In Fig. 4, the thickness of the Cu seed layer is clearly shown to be about 50 nm, which is comparable to that determined by on advanced copper interconnection technique. Figure 5 shows that the variation in the average roughness of the electroless Cu seed film is dependent on different deposition time at 30 C. The Cu seed layer exhibits the lowest surface roughness, 14 nm, in 30 mm CuSO 4, and this surface Cu Ta/SiO Si Substrate Fig. 4. SEM cross-sectional view of the Cu seed layer on Ta/SiO /Si with a film thickness of 50 nm at a deposition temperature of 30 C for a deposition time of 80 s. 0 Fig. 5. Variation in the roughness of an electroless Cu seed layer with different deposition times at a deposition temperature of 30 C. roughness increases with increasing deposition time. The grain size of the Cu seed layer increases with increasing deposition time. Also, the larger the grain size, the greater the surface roughness. Furthermore, the surface roughness of Cu increases with increasing CuSO 4 concentration. The frequency of collision between the two reactants increases with increasing reactant concentration, i.e., the higher the concentration of the reactant, the larger the nucleation velocity. This higher frequency can form more void nucleation and larger grain size. However, the roughness of the Cu seed layer is influenced by deposition time and growth concentration. The surface morphology of the Cu seed layer deposited for 80 s is revealed by SEM, as shown in Fig. 6. The surface of the thin film deposited in 30 mm CuSO 4 is very smooth and has an average roughness of 14 nm, as shown in Fig. 6(a). Figures 6(b) and 6(c) show that the average surface roughnesses in 40 and 50 mm CuSO 4 are 8 and 90 nm, respectively. However, the surface roughness obviously increases with increasing CuSO 4 concentration. According to the SEM micrography, one can note that the surface roughness of the substrate is consistent with that shown in Fig. 5. Figure 7 shows that the variation in the grain size of the Cu seed layer for electroless plating depends on deposition in 30 mm CuSO 4 at a deposition temperature of 30 C. The grain size of the Cu seed layer is estimated by the Scherrer equation. 18) The grain size of the Cu seed layer increases with increasing deposition time due to the agglomeration of Cu during the reaction. The smallest grain size value of 34 nm is found at a deposition time of 80 s. Furthermore, the resistivity of the Cu seed layer decreases with decreasing deposition time. At a deposition time of 80 s and with a Cu seed layer thickness of about 50 nm, a high electrical resistivity of 4.0 mcm was obtained. This was due to a large amount of defects, which result in electron scattering in the microcavity surface of this thin layer. 19) Although this deposition time decreased the electrical resistivity of the Cu seed layer, the average grain size of the Cu seed layer was

Jpn. J. Appl. Phys., Vol. 43, No. 8A (004) T.-H. MEEN et al. 5103 (a) (b) (c) Fig. 6. SEM in different CuSO 4 concentrations: (a) 30 mm (b) 40 mm and (c) 50 mm for a deposition time of 80 seconds at a deposition temperature of 30 C. Resisivity ( µ Ω. cm) 4.5 4 3.5 3.5 41 40 39 38 37 36 35 34 Average Grain Size (nm) Average Roughness (nm) 16 14 1 10 8 6 4 Annealing in Hydrogen 150 C 50 C 350 C 1.5 33 0 0 40 60 80 100 10 140 Annealing Time (min) Fig. 7. Dependence of resistivity of the Cu seed layer and average grain size on the deposition time at a deposition temperature of 30 C for 30 mm CuSO 4. Fig. 8. Dependence of average roughness on annealing time at different annealing temperatures for a deposition time of 80 s in 30 mm CuSO 4 at 30 C. The annealing processes were performed in hydrogen ambience. increased. Furthermore, this interconnection conduction depends on the resistivity of the Cu bulk layer. Thus, the Cu seed layer, with a smaller grain size on the surface can result in a better adhesive force and will favor the growth of the Cu bulk layer. The larger the grain size of the copper, the lower the boundary between the grains. The lower the grain boundary, the higher the conductivity. Thus, the resistivity was further reduced to 1.86 mcm with a greater thickness of 40 nm at more than 10 s. In this study, the value, 1.86 mcm, approaches the value of 1.70 mcm for the majority of Cu films. After the deposition of the Cu seed layer, performed at a deposition time of 80 s in 30 mm CuSO 4 annealing was performed in hydrogen ambience with different annealing times and temperatures, as shown in Fig. 8. The average roughness of the Cu seed layer decreased with increasing annealing time increased until 60 min had elapsed. This is because hydrogen has a high thermal diffusivity and easily combines with impurities, enabling it to restructure the Cu seed layer during annealing. 0) Also, the average roughness of the Cu seed layer decreased with increasing annealing temperature. After annealing for 60 min at temperatures between 50 C and 350 C, it was observed that the average roughness of the Cu seed layer was almost unchanged at around 4 nm. This may be due to the fact that the grain growth has reached saturation; hence, the average roughness remains constant. 1) Intensity (arb. units) Cu (111) Cu (00) 40 45 50 55 60 θ (deg) 350 C 50 C 150 C As-Deposition Fig. 9. XRD pattern for the Cu seed layer/ta/sio /Si structures; (a) asdeposited and after annealing at (b) 150 C, (c) 50 C and (d) 350 C for 60 min in H ambience. Figure 9 shows the typical X-ray diffraction (XRD) patterns of an annealed Cu seed layer/ta/sio /Si sample after thermal annealing for 60 min in hydrogen ambience.

5104 Jpn. J. Appl. Phys., Vol. 43, No. 8A (004) T.-H. MEEN et al. The main peaks around 43 and 51 are due to Cu (111) and Cu (00), respectively. The XRD peak intensity of the Cu (111) increased with increasing annealing temperatures up to 50 C. In annealing temperatures between 50 C and 350 C, the Cu seed layer exhibits a stronger (111) texture than the deposited one. The Cu (111) texture favors the growth of a Cu bulk layer. In addition, at annealing temperatures between 50 C and 350 C, it was observed that the Cu (111) intensity of the Cu seed layer was almost unchanged. This result implies an unchanged phenomenon for grain growth and is consistent with the finding in Fig. 8. Thus, to avoid thermal stress, an annealing temperature of 50 C was introduced to improve the quality and achieve the highest uniformity of the seed layer. The rersult reveals that the Cu seed layer produced by the electroless process is of a sufficiently high quality to be used as the adhesion layer for the fabrication of ULSI interconnection. 4. Conclusion We achieved the low-temperature growth (30 C) of an ELP Cu seed layer on a Ta/SiO /Si substrate. The deposition of Pd nuclei on the Ta/SiO /Si substrate during activation was confirmed as a spontaneous reaction. The optimum activation time for the substrate was clearly observed to be 7 min. In 50-nm-thick ELP Cu seed layers, the optimal surface roughness and grain size are 14 nm and 34 nm, respectively. Sequentially, at an annealing temperature of 50 C for an annealing time of 60 min, it was observed that the surface roughness of the Cu seed layer was reduced to about 4 nm. At annealing temperatures between 50 C and 350 C, the Cu seed layer exhibits a strong (111) texture, which favors the growth of the Cu bulk film. Various analytical techniques, such as XRD, AFM, EDX and SEM, verify the reliability and high quality of the Cu seed layer obtained by ELP. Acknowledgments This work was supported in part by the National Science Council of the Republic of China under contract number: NSC 9-16-E-18-004. 1) J. R. Lloyd and J. J. Ciement: Thin Solid Films 6 (1995) 135. ) T. Nguyen, L. J. Charneski and D. R. Evans: J. Electrochem. Soc. 144 (1997) 3634. 3) C. Wenzel, N. Urbansky, W. Klimes, P. Siemroth and T. Schulke: Microelectron. Eng. 33 (1997) 31. 4) S. Riedel, J. Rober and T. Gener: Microelectron. Eng. 33 (1997) 165. 5) S. K. Kwak, K. S. Chung, I. Park and H. Lim: Curre. Appl. Phys. (00) 05. 6) K.-K. Choi and S.-W. Rhee: Thin Solid Films 397 (001) 70. 7) Yi-Mao Lin and Shi-Chern Yen: Appl. Surf. Sci. 178 (001) 116. 8) S. W. Hong, C.-H. Shin and J.-W. Park: J. Electrochem. Soc. 149 (00) G 85. 9) J. H. Lin, Y. Y. Tsai, S. Y. Chiu, T. L. Lee, C. M. Tsai, P. H. Chen, C. C. Lin, M. S. Feng, C. S. Kou and H. C. Shih: Thin Solid Films 377 (000) 59. 10) C. J. Huang and C. J. Chiu: submitted to J. Electrochem. Soc. Aug. 003. 11) M. B. Naik, W. N. Gill, R. H. Wentorf and R. R. Reeves: Thin Solid Films 6 (1995) 60. 1) J. Torres: Appl. Surf. Sci. 91 (1995) 11. 13) H. J. Jin, M. Shiratani, T. Kawasaki, T. Fukuzawa, T. Kinoshita and Y. Watanabe: J. Vac. Sci. Technol. A 17 (1999) 76. 14) V. M. Dubin, Y. Shacham-Diamandad, B. Zhao, P. K. Vasudev and C. H. Ting: J. Electrochem. Soc. 144 (1997) 898. 15) P. C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans and H. Deligianni: IBM J. Res. Develop. 4 (1998) 567. 16) M. H. Kiang, M. A. Lieberman, N. W. Cheung and X. Y. Qian: Appl. Phys. Lett. 60 (199) 767. 17) J. Philip Bromberg: Physical Chemistry, Electrochemical Cells (Allyn and Bacon, Inc., Boston, 1980) p. 311. 18) B. D. Cullity: Elements of X-ray Diffraction, Diffraction I: Directions of Diffracted Beams (Addison-Wesley Publishing Company, Inc., California, 1959) p. 81. 19) H. H. Hsu, C. W. Teng and J. W. Yeh: J. Electrochem. Soc. 149 (00) C 143. 0) K. K. Choi and S. W. Rhee: J. Electrochem. Soc. 148 (001) C 473. 1) Hong Xiao: Introduction to Semiconductor Manufacturing technology, Thermal Processes (Prentice Hall, New York, 001) p. 11.