Conductive Paste-Based Interconnection Technology for High Performance Probe Card

Similar documents
Future HDI An HDPUG project Proposal

Interconnection Reliability of HDI Printed Wiring Boards

Lead-Free HASL: Balancing Benefits and Risks for IBM Server and Storage Hardware

Low CTE / High Tg FR-4 with High Heat Resistance

IPC-AJ-820A Assembly and Joining Handbook. The How and Why of All Things PCB & PCA

High Layer Count PCB. Technology Trends in KOREA ISUPETASYS

14. Designing with FineLine BGA Packages

Via Life vs. Temperature Stress Analysis of Interconnect Stress Test

Experience in Applying Finite Element Analysis for Advanced Probe Card Design and Study. Krzysztof Dabrowiecki Jörg Behr

NARROW PITCH (0.4mm) CONNECTORS P4S SERIES

Mastering the Tolerances Required by New PCB Designs. Brad Hammack Multek Doumen, China

Basic PCB Level Assembly Process Methodology for 3D Package-on-Package

Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications

Design for Flip-Chip and Chip-Size Package Technology

ESPANEX L Series. Technical data sheet Nishigotanda Shinagawa Tokyo, , Japan TEL FAX

Freescale Semiconductor Tape Ball Grid Array (TBGA) Overview

IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION

TGV and Integrated Electronics

Embedding Passive and Active Components: PCB Design and Fabrication Process Variations

Challenges and Solutions for Cost Effective Next Generation Advanced Packaging. H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012

Chips Face-up Panelization Approach For Fan-out Packaging

Innovative Substrate Technologies in the Era of IoTs

Fairchild Semiconductor Application Note January 2001 Revised September Using BGA Packages

Global Test solutions Conception and production of probe cards for testing microchips

Close supply chain collaboration enables easy implementation of chip embedded power SiP

WF6317. A superactive low-volatile/high heat-resistant water-soluble flux for ball soldering

9 rue Alfred Kastler - BP Nantes Cedex 3 - France Phone : +33 (0) website :

1 Thin-film applications to microelectronic technology

ThunderClad 2. TU-883 HF Very Low Loss Material. Laminates & Prepregs Mass Lamination Service Insulated Metal Substrate Materials

Excellent fit between product performance and application Next generation polyimide labels for Printed Circuit Boards

Troubleshooting. for. Printed Board. Manufacture. and Assembly IPC PE-740. Revision A December Developed by THE INSTITUTE FOR INTERCONNECTING

Highly Accelerated Thermal Shock Reliability Testing

UL PCB Recognition what is it & why do you need to know about it

Precision Engineered Parts

Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017

IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY

An Innovative High Throughput Thermal Compression Bonding Process

Component Palladium Lead Finish - Specification Approved by Executive Board 1997-xx-xx August 22 Version

Welding Processes. Consumable Electrode. Non-Consumable Electrode. High Energy Beam. Fusion Welding Processes. SMAW Shielded Metal Arc Welding

Cannon Trident Connector System

Challenges for Embedded Device Technologies for Package Level Integration

Characterizing the Lead-Free Impact on PCB Pad Craters

Lead Free Assembly: A Practical Tool For Laminate Materials Selection

M16 M20 M25 M207 M51 M100 M200

Welcome to Streamline Circuits Lunch & Learn. Design for Reliability & Cost Reduction of Advanced Rigid-Flex/Flex PCB Technology

c/bach, 2-B Pol. Ind Foinvasa Montcada i Reixac (Barcelona) SPAIN Tel FAX

ICDs (InterConnect Defects) What are they? Where do they come from? How can we make them go away? Doug Trobough Suixin Zhang

Wafer probe challenges for the automotive market Luc Van Cauwenberghe

Evaluation of Cu Pillar Chemistries

Recommended Land Pattern: [mm]

Cu Pillar Interconnect and Chip-Package-Interaction (CPI) for Advanced Cu Low K chip

Introduction of CSC Pastes

28nm Mobile SoC Copper Pillar Probing Study. Jose Horas (Intel Mobile Communications) Amy Leong (MicroProbe) Darko Hulic (Nikad)

HYPRES. Hypres MCM Process Design Rules 04/12/2016

2.54mm Pitch Board to Cable Connector

Selection and Application of Board Level Underfill Materials

ALTERNATIVES TO SOLDER IN INTERCONNECT, PACKAGING, AND ASSEMBLY

10 Manor Parkway, Suite C Salem, New Hampshire

curamik CERAMIC SUBSTRATES AMB technology Design Rules Version #04 (09/2015)

PINGYORK INTERNATIONAL INC. - PCB LAYOUT/PRODUCTION - SMT/DIP/PRODUCT ASSEMBLY PRODUCTION - SAFETY APPROVAL TEST PRESENTATION. Updated June, 2013

3D Package Technologies Review with Gap Analysis for Mobile Application Requirements. Apr 22, 2014 STATS ChipPAC Japan

Guénaël RIBETTE. General Director

Design and Assembly Process Implementation of 3D Components

Thermo-Mechanical FEM Analysis of Lead Free and Lead Containing Solder for Flip Chip Applications

2.5D and 3D Semiconductor Package Technology: Evolution and Innovation

Optimizing Immersion Silver Chemistries For Copper

Newsletter. Test Services & Failure Analysis Laboratory. April The Reality of Flip-Chip Solder Bump Electromigration Failure INSIDE THIS ISSUE

New Technology for High-Density LSI Mounting in Consumer Products

MMP - Metal Film MELF

INFLUENCE OF ELECTRICALLY CONDUCTIVE ADHESIVE AMOUNT ON SHEAR STRENGTH OF GLUED JOINTS ON FLEXIBLE SUBSTRATES

Thermo-Mechanical Reliability of Through-Silicon Vias (TSVs)

3M Pin Strip Header 2 mm and 2 mm x 2 mm Straight, Surface Mount 951 Series

Development of Anisotropic Conductive Film for Narrow Pitch Circuits

PCB Production Process HOW TO PRODUCE A PRINTED CIRCUIT BOARD

Australian Journal of Basic and Applied Sciences. Pb-Free Solder Ball Robustness Comparison under AC and TC Reliability Test

Thermal Reliability of Laser Ablated Microvias and Standard Through-Hole Technologies as a Function of Materials and Processing

Flip Chip - Integrated In A Standard SMT Process

Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes

INTERFLUX ELECTRONICS NV

Impacts of the bulk Phosphorous content of electroless Nickel layers to Solder Joint Integrity

Flexible Printed Circuits Design Guide

Simulation of Embedded Components in PCB Environment and Verification of Board Reliability

Bare Board Material Performance after Pb-Free Reflow

GRAPHIC MANUFACTURING CAPABILITY Q217-18

Bridging Supply Chain Gap for Exempt High-Reliability OEM s

Advances in Printing nano Cu and Using Existing Cu Based Manufacturing Processes. Michael J. Carmody Chief Scientist, Intrinsiq Materials

TAIYO IJR-4000 MW300

ORDERING INFORMATION: P/N K S 5 E U x CAT. 5e TOOLLESS RJ45 KEYSTONE JACKS (UNSHIELDED) P111

Design Rules & DFM for High-Speed Design

Nano- And Micro-Filled Conducting Adhesives For Z-axis Interconnects

Material Selection and Parameter Optimization for Reliable TMV Pop Assembly

3D-WLCSP Package Technology: Processing and Reliability Characterization

Datasheet RS Pro RS Series Axial Carbon Resistor 1kΩ ±5% 2W ppm/ C RS Stock No:

MCPCB Material (Heat sync)

A Roadmap to Low Cost Flip Chip Technology and Chip Size Packaging using Electroless Nickel Gold Bumping

T E C H N I C A L B U L L E T I N

Soldering Immersion Tin

Transcription:

Conductive Paste-Based Interconnection Technology for High Performance Probe Card Sang-il Kwon Eddy Kang TSE Co., Ltd.

Overview Introduction of TABP Technology Key Technology of Core to Core Interconnection Test Results & Application Examples Electrical & Thermal Reliability of Core to Core Interconnection PCB by Actual Application Probe Card Application by Design Rules Conclusions 2

Who we are TSE Co., Ltd. Probe Card Load Board Affiliated Companies Memory Test Board Test Socket 3

What is TABP? TABP = TSE Advanced Bump PCB Core to core interconnection PCB Before After Core Pad Bismuth Tin Sintered Copper/Tin Alloy Metal Network Copper Liquid Organic Formulation Core Pad <Structural Change of Conductive Paste by Sintering> Electrical Interconnection <Section View> 4

Advantages of TABP Free of Thick Board Drilling Free of High Aspect Ratio Via Hole Plating Reducing Complexity of Back Drilling Enhance Fabrication Capability for Fine Pitch HDI PCBs IST Coupon Layup Structure Cross Section L01 L09 1.5mm - Min. Pitch : 0.4mm -Layer Count: 34 - Thickness : 6.4mm - Aspect Ratio : 51.2 - Via Size : 0.125mmΦ - PCB Size : 12.7mm x 50.8mm A/R: 12 A/R: 51.2 L10 L17 L18 L25 L26 L34 6.4mm 1.5mm 1.5mm 1.5mm 5

TABP Fabrication Process Flow Prepreg Tacking Type Tacking Laser Drill Paste Filling Remove PET CORE Hot Press PET PP PET PET PP PET PET PP PP PP PET Conductive Paste Pocket Conductive Paste CORE Core & Prepreg Tacking Type Tacking Laser Drill Paste Filling Remove PET Hot Press PET PP CORE PET PP CORE Conductive Paste Pocket PET PP CORE Conductive Paste PP CORE CORE PP CORE 6

Key Technology TABP Electrical Conductivity (TSE Advanced Bump PCB) Thermal Reliability Perfect Sintered Alloy Structure Sufficient Amount of Paste Fill Optimized Forming of Conductive Paste Pocket Withstanding Thermal Stress Sintered Alloy Bonding Layer Sufficient Resin at Bonding Layer Optimized Material, Layup & Design 7

Electrical Conductivity Coupon Board - 0.5mm Pitch 12DUTs & 0.4mm Pitch 12DUTs - Each Via has 1 TABP interconnection. - BGA Count of Each DUT = 1,024 - Each Via in Same DUT connected by Daisy Chain - PCB Thickness = 1.2mm DC Interconnection Resistance Values Daisy Chained DUT Each BGA Via BGA Pitch (1,024 BGA 24DUTs) (Total Count=24,576Ea) 0.5mm Max. 6.0Ω 6.65mΩ (12DUTs) Min. 5.64Ω 4.64mΩ 0.4mm Max. 7.63Ω 7.05mΩ (12DUTs) Min. 7.25Ω 4.81mΩ Measured by DVM, Microcraft EMX6151 8

Electrical Conductivity Hole Resistance (mω) Via Holes Resistance of 1 DUT Cross Section of Test Coupon 50 40 30 20 10 0 1 4 7 10 13 16 19 22 25 28 31 1 5 9 13 17 29 25 21 - BGA Pitch : 0.4mm - 1,024 TABP Vias in 1DUT - Max Via Hole resistance : 7.05mΩ - Laser Drill Diameter : 150μm - Prepreg Thickness : 110μm <Stable Sintered Alloy Structure> 9

Thermal Reliability Cross Section Analysis after Solder Pot Floating Test - Thermal Impact Condition : 3 Times, 288 C Solder Pot Floating 10sec - BGA Count per Each DUT : 100, 600, 1024 & 1600 Ea - Each Via in Same DUT connected by Daisy Chain - All BGA Interconnection Test was passed. - TABP can withstand Thermal Impact of Solder Floating Test. After Lamination After Out Layer Formation After Printing All passed after 3X T/I All passed after 3X T/I All passed after 3X T/I 10

Thermal Reliability Resistance Changes after Solder Reflow Exposures - Reflow Condition : 6 Times Reflow @260 C - BGA Count per Each DUT : 100, 600, 1024 & 1600 Ea - Each Via in Same DUT connected by Daisy Chain - All BGA Interconnection Test was passed. - IPC Standards for DC Resistance Change after Reflow : Max 10% 10 % 5 % 0 % -5 % -10 % 10 % 5 % 0 % -5 % -10 % Resistance Change of 100BGA 2.25 4.65 4.44 reflow 6 time 5.56 Hole 100-5 Hole 100-6 Hole 100-7 Hole 100-8 Resistance Change of 1024BGA 1.99 0.90 1.69 reflow 6 time 0.36 Hole 1024-5 Hole 1024-6 Hole 1024-7 Hole 1024-8 10 % 5 % 0 % -5 % -10 % 10 % 5 % 0 % -5 % -10 % Resistance Change of 600BGA reflow 6 time -1.28-2.55-2.06-2.32 Hole 600-5 Hole 600-6 Hole 600-7 Hole 600-8 Resistance Change of 1600BGA 3.63 0.65 1.93 reflow 6 time 3.97 Hole 1600-5 Hole 1600-6 Hole 1600-7 Hole 1600-8 11

Thermal Reliability Cross Section Analysis after 6x Reflow Exposure - Board Profile : 296FBGA, 0.35mm Pitch, 4mmT, 3 TABP, 0.15mmΦ Laser Drill - Applied Thermal Impact Condition : 6 Times Reflow @260 C - TABP s Structural Stability can withstand 6 times of Reflow Condition. < Cross Section after Thermal Impact> Stable Paste Structure & Bonding Condition 12

TABP Application Examples Load Board 0.4mm Pitch, Aspect Ratio 41.3 Board Profiles - BGA Pitch : 0.4mm Pitch - Layer Count : 38L - Thickness : 6.2mm - Via Size : 0.15mmΦ - Aspect Ratio : 41.3 - PCB Size : 340mm x 520mm - Option : TABP + HPL + Back Drill Structure (BGA) 0.4mmP (BGA) 0.4mmP 6.2mm 0.125Φ 0.15Φ Cross Section Unnecessary Stubs Reduced 13

TABP Application Examples Memory Test Board 0.35mm Pitch, Aspect Ratio 28 Board Profiles Structure Cross Section - BGA Pitch : 0.35mm - Layer count : 38 - Thickness : 3.5mm - Via Size : 0.125mmΦ - Aspect Ratio : 28 - PCB Size : 59mm x 109 mm - Option : TABP + HPL + Back Drill 14

TABP Application Examples Pretest Coupon - 0.3mm Pitch, Aspect Ratio 62 Board Profiles - BGA Pitch : 0.3mm - Layer Count : 34 - Thickness : 6.2mm - Via Size : 0.1mmΦ - Aspect Ratio : 62 - PCB Size : 26mm x 26mm - Option : TABP + HPL + Back Drill Structure Cross Section L01 L09 L10 L17 6.2mm L18 L25 L26 L34 15

Challenges for Probe Card PCB High Layer Count / High Aspect Ratio SI Performance for High Speed Application Design/Fabricate PCB at Competitive Conditions TABP is a Solution for Advanced Probe Card PCB. by Eliminating of Thick Board Drilling by Eliminating of High Aspect Ratio Via Plating by Reducing Drilling Complexity & Improving Yield 16

Design Rule for 0.8mm Pitch P/C PCB 0.8P 0.8P in Double Line Array Plating Through Hole Type DRILL A LAND 6.2mm CLEAR C B 0.25Φ Drill Dia. A/R Line Width A B C Land to Line Line to Line Drill to Metal 250μmΦ 24.8 80μm 80μm 80μm 155μm 17

Design Rule for 0.8mm Pitch P/C PCB TABP Type 0.8P 0.8P 0.8P 2.06mm in Double Line Array DRILL LAND A 2.06mm 6.2mm TABP CLEAR C B 2.06mm 0.125Φ Drill Dia. A/R Line Width 125μmΦ 49.6 (16.5) A B C Land to Line Line to Line Drill to Metal 80μm 90μm 160μm 177μm 18

Conclusions Conductive Paste Based Core to Core Interconnection Technology at PCB was realized. Especially excellent core to core conductivity and thermal reliability were proved. Therefore, we hope the TABP technology would pave the way for fine pitch and high aspect ratio PCB fabrication. 0.4mm Pitch, Aspect Ratio 41.3 Load Board & 0.3mm Pitch, Aspect Ratio 62 Board were possible to fabricated with TABP Technology. Test boards for wafer test also need TABP technology to respond for the requirement of multi sites, fine pitch and high frequency performance. 19

Thank you very much. Questions? 20