Bare Die Assembly on Silicon Interposer at Room Temperature

Similar documents
Micro-tube insertion into aluminum pads: Simulation and experimental validations

3D-IC Integration using D2C or D2W Alignment Schemes together with Local Oxide Reduction

Aluminum to Aluminum Bonding at Room Temperature

Chapter 3 Silicon Device Fabrication Technology

Fraunhofer IZM Bump Bonding and Electronic Packaging

SLIM TM, High Density Wafer Level Fan-out Package Development with Submicron RDL

Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer

Molding materials performances experimental study for the 3D interposer scheme

Simulations and Characterizations for Stress Reduction Designs in Wafer Level Chip Scale Packages

Motorola MC68360EM25VC Communication Controller

Chapter 4 Fabrication Process of Silicon Carrier and. Gold-Gold Thermocompression Bonding

SET Technical Bulletin

JOINT INDUSTRY STANDARD

Challenges and Solutions for Cost Effective Next Generation Advanced Packaging. H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012

EECS130 Integrated Circuit Devices

Interconnect Structure for Room Temperature 3D-IC Stacking Employing Binary Alloying for High Temperature Stability

Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes

Characterization of 0.6mils Ag Alloy Wire in BGA Package

The Effect of Fillers in Nonconductive Adhesive on the Reliability of Chip-on-Glass Bonding with Sn/Cu Bumps

IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY

II. A. Basic Concept of Package.

Material based challenge and study of 2.1, 2.5 and 3D integration

Beam Leads. Spider bonding, a precursor of TAB with all-metal tape

Analog Devices ADSP KS-160 SHARC Digital Signal Processor

VLSI Design and Simulation

PHYS 534 (Fall 2008) Process Integration OUTLINE. Examples of PROCESS FLOW SEQUENCES. >Surface-Micromachined Beam

Silicon Interposers with Integrated Passive Devices: Ultra-Miniaturized Solution using 2.5D Packaging Platform

5. Packaging Technologies Trends

Flip Chip Bump Electromigration Reliability: A comparison of Cu Pillar, High Pb, SnAg, and SnPb Bump Structures

Reliability of RoHS-Compliant 2D and 3D 1С Interconnects

MEPTEC Semiconductor Packaging Technology Symposium

Micron Semiconductor MT4LC16M4H9 64Mbit DRAM

Intel Pentium Processor W/MMX

Failure Modes in Wire bonded and Flip Chip Packages

General Introduction to Microstructure Technology p. 1 What is Microstructure Technology? p. 1 From Microstructure Technology to Microsystems

Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications

ENHANCING MECHANICAL SHOCK PERFORMANCE USING EDGEBOND TECHNOLOGY

DEVELOPMENT DONE ON DEVICE BONDER TO ADDRESS 3D REQUIREMENTS IN A PRODUCTION ENVIRONMENT

Chemical Mechanical Planarization STACK TRECK. SPCC 2017 Viorel Balan

Microelectronics. Integrated circuits. Introduction to the IC technology M.Rencz 11 September, Expected decrease in line width

Chapter 2 Manufacturing Process

Gold Passivated Mechanically Flexible Interconnects (MFIs) with High Elastic Deformation

UMC UM F-7 2M-Bit SRAM

9 rue Alfred Kastler - BP Nantes Cedex 3 - France Phone : +33 (0) website :

Novel Technique for Flip Chip Packaging of High power Si, SiC and GaN Devices. Nahum Rapoport, Remtec, Inc.

INTERCONNECT STRUCTURE FOR ROOM TEMPERATURE 3D-IC STACKING EMPLOYING BINARY ALLOYING FOR HIGH TEMPERATURE STABILITY

Cu Pillar Interconnect and Chip-Package-Interaction (CPI) for Advanced Cu Low K chip

Effect of Process Variations on Solder Joint Reliability for Nickel-based Surface Finishes

Oki M A-60J 16Mbit DRAM (EDO)

1.1 Background Cu Dual Damascene Process and Cu-CMP

Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes. Jason Chou and Sze Pei Lim Indium Corporation

3D technologies for More Efficient Product Development

NKK NR4645LQF Bit RISC Microprocessor

Optoelectronic Chip Assembly Process of Optical MCM

Adaption to scientific and technical progress under Directive 2002/95/EC

EE C245 ME C218 Introduction to MEMS Design

Motorola PC603R Microprocessor

Regents of the University of California 1

Rockwell R RF to IF Down Converter

Adaption to scientific and technical progress under Directive 2002/95/EC

Flip Chip Joining on FR-4 Substrate Using ACFs

Micron Semiconductor MT5C64K16A1DJ 64K x 16 SRAM

Challenges for Embedded Device Technologies for Package Level Integration

SGS-Thomson M28C K EEPROM

TSV Processing and Wafer Stacking. Kathy Cook and Maggie Zoberbier, 3D Business Development

Next Gen Packaging & Integration Panel

Lecture 22: Integrated circuit fabrication

VTC VM365830VSJ Pre-Amp

Motorola MPA1016FN FPGA

The Development of a Novel Stacked Package: Package in Package

Mosel Vitelic MS62256CLL-70PC 256Kbit SRAM

3D-WLCSP Package Technology: Processing and Reliability Characterization

KGC SCIENTIFIC Making of a Chip

RELIABILITY IMPACT OF COPPER-DOPED EUTECTIC TIN-LEAD BUMP AND ITS VOIDING UPON FLIP CHIP ASSEMBLIES

TIN-BASED LEAD-FREE SOLDER BUMPS FOR FLIP-CHIP APPLICATION. S. Yaakup, H. S. Zakaria, M. A. Hashim and A. Isnin

Cu-Al intermetallic growth behaviour study under high temperature thermal aging

Design for Flip-Chip and Chip-Size Package Technology

Xilinx XC4036EX FPGA

Assembly Reliability of TSOP/DFN PoP Stack Package

Composition/wt% Bal SA2 (SABI) Bal SA3 (SABI + Cu) Bal

Chip-to-Wafer Technologies for High Density 3D Integration

3DIC Integration with TSV Current Progress and Future Outlook

Y.C. Chan *, D.Y. Luk

Regents of the University of California

Effect of Underfill Entrapment on the Reliability of Flip-Chip Solder Joint

TSV CHIP STACKING MEETS PRODUCTIVITY

1 Thin-film applications to microelectronic technology

XTSC SiCap 400µm - NiAu finishing - Assembly by soldering

Challenges in Material Applications for SiP

TGV and Integrated Electronics

Packaging Effect on Reliability for Cu/Low k Damascene Structures*

Editorial Manager(tm) for Microsystem Technologies Manuscript Draft

Lattice isplsi1032e CPLD

Three-Dimensional Molded Interconnect Devices (3D-MID)

CMOS Manufacturing process. Design rule set

Basic PCB Level Assembly Process Methodology for 3D Package-on-Package

ALTERNATIVES TO SOLDER IN INTERCONNECT, PACKAGING, AND ASSEMBLY

Plasma for Underfill Process in Flip Chip Packaging

Transcription:

Minapad 2014, May 21 22th, Grenoble; France Bare Die Assembly on Silicon Interposer at Room Temperature W. Ben Naceur, F. Marion, F. Berger, A. Gueugnot, D. Henry CEA LETI, MINATEC 17, rue des Martyrs 38054 Grenoble Cedex 9, France walim.bennaceur@cea.fr, +33 (0)4 37 78 05 41 Abstract This study focuses on an alternative technology for fine pitch 3D interconnection. Provided the silicon chips have standard bonding Aluminum pads, any bare die provided by external furnishers can be directly bonded, by compressive flip-chip at room temperature, on a silicon interposer equipped with hard Aluminum micro-tubes. The interconnection resistance appeared similar to those obtained with standard micro-bump, Transient Liquid Phase and micro-insert technologies with a given pad size of 40x40µm². Several reliability tests have been conducted and the electrical results compared with Gold coated micro-tubes and other fine pitch technologies. No failure occurred during reliability tests of Aluminum to Aluminum assemblies. Key words: silicon interposer, microtubes, aluminum, reliability Situation and Objectives The increasing demand for miniaturization of consumer products and optical and micromechanical systems drives the need for compact and ultra-flat packages that can use bare die issued from various external suppliers or foundries. The fabrication of SIP (System-In-Package) with Silicon Interposers is an important technological step for electronic miniaturization and micro-electronic systems size reduction. By shortening significantly the signalpath between flip-chipped chips, Silicon Interposers can improve device operation while managing device size and weight constraints, then reducing the global power consumption of the final assembly. The Silicon Interposer and related assembly process proposed in this work can open the way to straight integration of bare die bonded on a single silicon mother substrate (Silicon Interposer) which can be either an active integrated circuit or passive redistribution substrate (Figure 1). Figure 1: Bare die assembly on Silicon Interposer by with Aluminum micro-tubes and pads. In previous work [1], a new bonding process concept has been proposed using a room temperature Aluminum to Aluminum bonding flip-chip process: this process should reduce most of the inherent reliability concerns (aging, humidity, electromigration issues) affecting more classical flip-chip bonding techniques and related to intermetallic evolution affecting bonds (CuSn/Cu, TLP, etc ). Moreover, provided the silicon chips have standard bonding Aluminum pads, any bare die provided by external furnishers can be directly bonded, by compressive flip-chip at room temperature, on a silicon interposer equipped with hard coated Aluminum microtubes. Another advantage of micro-tube technology is that it can address 10µm pitch as well as larger pitch by performing several micro-tube connections in parallel. In this paper the Aluminum to Aluminum process concept is characterized from a connection yield standpoint, and then first reliability studies of assemblies are described. Finally, pathways toward final proof of this new assembly concept are detailed. Background on fine pitch bonding technologies Aggressive pitch is one the top requirement for 3D interconnects. In a previous paper study [2], different 3D interconnection technologies for sub- 20μm pitch have been described. These technologies were: micro-inserts (insertion of a nickel cylinder in Aluminum pad), micro-tubes (insertion of a gold metalized tube in Aluminum based pad), Transient Liquid Phase (TLP) bonding (whole solder reacts to form intermetallic compound) and Copper direct bonding. The Kelvin resistance for each technology has been reported in Table 1.

Table 1: Fine pitch technologies [2]. PAD Cu 40x40 direct TLP bump insert µm² bonding Pitch (µm) R Kelvin (mω) tube 50 50 50 50 50 7 ρ=2.1.10-2 Ω.µm 6.5 7.7? For most technologies, reliability tests showed problems of intermetallic compound formation during long term reliability tests [3]. We will switch to the 50µm pitch test vehicle and complete the missing data in the last column of Table 1. Micro-tube description and insertion process on aluminum pad Micro-tube fabrication process is here described. It starts with the deposition of an oxide on the Aluminum pads. This oxide is flattened with a chemical mechanical polishing step (CMP). A first lithography step is then realized to open the oxide above the Aluminum pads at a 10μm minimum pitch. A step and repeat photolithography equipment is used to achieve the alignment requirements. The diameter of the apertures (i.e.: access vias ) is 3μm. Then a 3μm thick sacrificial layer and a hard mask are deposited. A second lithography followed by an etch step are used to open the hard mask and etch the sacrificial layer above the previous aperture. An adhesion layer of Titanium (Ti) and Titanium nitride (TiN) is first deposited. Then a Tungsten (W) layer, that will be the core of the micro-tube, is deposited by chemical vapor deposition (CVD) at 400 C. A second CMP step is performed to remove the W and the hard mask on the surface of the sacrificial layer. The sacrificial layer is then removed. An Aluminum-Copper (AlCu 0.5 ) coating is added around the W core of the micro-tube requiring a PVD followed by lithography/etch steps. A microtube section is showed in Figure 2. the pitch between tubes were both 10µm. There were 12 micro-tubes per pad, all in parallel in order to obtain pads with 50µm pitch (Figure 3). Figure 3: Bottom die pads and microtubes insertion geometry. The top dies were then bonded on the bottom wafer using a SET FC300 flip-chip bonder as sketched in Figure 4. The alignment accuracy is close to one micrometer. Figure 4: Aluminum to Aluminum assembly schematic section. Experiments Experiments were made with two micro-tube geometries with 2µm height and 6µm diameter: smooth and corrugated (Figure 5). Compared to a smooth geometry, the corrugated one increases the lateral area of the microtube. It aims at improving electrical conductivity and releasing strain during insertion. For one die, there were 26256 assembled micro-tubes with a stain of about 4GPa per microtube. Seven bare dies were assembled. Figure 2: Top die Aluminum coated micro-tube section. There were 2188 Aluminum based pads with geometry of 40x40µm². The pitch between pads and Figure 5: 6µm diameter microtube geometries: smooth (left) and corrugated (right). For each die, two kinds of interconnections were tested: Kelvin pattern and a daisy chain of 340 contact pads (CP). The resistance was measured by a

four-point probe method. The Kelvin interconnections are located at the periphery of the assembled die while the 340CP patterns are at the center of the die. Both are representative of the tested technology. Table 2: Experiments. Number of dies tube 4 6µm smooth 3 6µm corrugated Strain/µtube 4GPa/µtube Results after assembling Histograms of the resistance distribution are presented in Figure 6 for the Kelvin patterns and in Figure 7 for the 340CP daisy chains, after assembling of aluminum coated micro-tubes on aluminum pads. For the 340CP daisy chain in Figure 7, the results after assembling showed a mean resistance of 57.5±1.3Ω, and a distribution centered at 58Ω, which means a resistance of 170mΩ for one contact. Compared to the Kelvin resistance measurements of 7.2mΩ, this high value can be explained by the presence of vias and lines between pads. After assembling, we concluded that there was no obvious effect of micro-tube geometry (smooth or corrugated). Physical analysis after assembling The first step consisted in introducing underfill by capillarity in order to hold the device during cutting. The die was then cut with a dicing saw from a corner to the opposite one as sketched in Figure 8. Figure 8: Transversal die cut. Figure 6: Kelvin resistance distribution after assembling. The second step consisted in employing a triple ion beam LEICA TIC3X for cutting perpendicularly to the die, as illustrated in Figure 9. With a high-quality surface, we can then make further observation of the connection level, which was about 3 to 5µm thick. For the Kelvin resistance in Figure 6, the results after assembling showed a mean resistance of 7.6±1.0mΩ, with a distribution centered at 7.2mΩ. Only one value of 9.8mΩ is out of the main distribution and can be ruled out from the mean resistance calculation. We finally obtained a mean resistance of 7.2±0.1mΩ for the Kelvin pattern. Figure 9: SEM image of TIC etching for microstructural analysis. Figure 7: 340CP resistance class distribution after assembling. As it can be seen in Figure 10, SEM observation revealed an insertion depth of about 1µm into the pad, observed with a point of view of about 45, from a corner to the other one. Room temperature compression leaded to a plastic deformation of the pad. The metals at the interface between microtube and pad could not be distinguished. This is a sign of a good quality interconnection.

Figure 11: Kelvin and 340CP resistance relative evolutions during tests. Figure 10: SEM images of Aluminum coated microtube insertion on Aluminum pad. In Figure 11, we can see that none of the seven bare dies failed during reliability tests. 340CP (green dotted lines) and Kelvin pattern (blue lines) exhibited a maximum variation of ±2%. These reliability results are compared to those obtained with gold coated micro-tubes in Figure 12. All the twelve dies were submitted to several standard tests in order to prove long term reliability of Aluminum to Aluminum bonding technology with micro-tubes. Reliability results Reliability tests consisted in starting by a bake at 125 C for 24 hours to drive away all the moisture within the samples. Then, according to IPC/JEDEC J-STD-020C, dies were stored 168 hours at 30 C and 60% of Relative Humidity (RH) to drive controlled amounts of moisture into the package. A thermal shock is provided by three reflows at 245-250 C in order to activate popcorn cracking of the package. The next step consisted in an industrystandard High-Temperature Storage (HTS) test. It is performed to determine the effect on devices of long-term storage at elevated temperatures (150 C) without any electrical stresses applied, and for 1000 hours. The electrical results for the two groups of dies are presented in Figure 11 for Kelvin resistance (blue continuous lines) and 340CP daisy chain (green dotted lines). An interconnection is considered as failed when the resistance drift reaches ±20%. Figure 12: Mean resistance relative evolution of micro-tubes with Au coating and AlCu 0.5 coating during tests. According to Figure 12, long term reliability was significantly improved by replacing gold coating by aluminum coating on micro-tubes. With Au coating, the mean resistance widely and rapidly passed the 20% failure criterion after 192 hours at 30 C/60%RH and the 3 reflows at 245 C. It continued to increase after high thermal storage and reached a variation of about 150%. In the meantime, with AlCu 0.5 coating, the mean resistance varied not more than ±1%. Discussion According to electrical resistance evolution during reliability tests of Aluminum to Aluminum assemblies, there are slight effects of temperature and micro-tube position. The 340CP daisy chains started to distinctly decrease of about -2% after high thermal storage at 150 C during the first 500 hours. Then it stabilized until the end of the 1000 hours. In the meantime, Kelvin patterns tended to decrease by -1% after moist storage and the 3 reflows, and

finally increased after thermal storage +1%. Indeed, Kelvin patterns are located at the periphery of the dies. They are more sensitive to the CTE mismatch effect between top and bottom dies. However, these values are not enough high to be considered as significant and can also be attributed to measurement errors. On the contrary to Gold to Aluminum bonding [2][3], high thermal storage tests of Aluminum to Aluminum assembly did not yield electrical resistance drift. In previous works, Al 2 Au intermetallic compound (IMC) growth had been observed at the contact interface during aging tests (Figure 13). Table 3: Fine pitch technologies (full data). PAD Cu 40x40 direct TLP bump insert µm² bonding Pitch (µm) R Kelvin (mω) Aging tests Al tube 50 50 50 50 50 7 ρ=2.1.10-2 Ω.µm IMC No IMC IMC 6.5 7.7 7.2 No IMC We are currently carrying on reliability tests with thermal cycling, to accelerate fatigue failures occurrence, and temperature humidity tests, to accelerate corrosion phenomena. We will then further investigate on potential microstructural evolution at the end of the whole reliability tests. Acknowledgements This work was supported by CEA-LETI. This work has been performed with the help of the Plateforme Technologique Amont of Grenoble, with the financial support of the Nanosciences aux limites de la Nanoélectronique Fundation. Figure 13: Intermetallic growth after reliability tests of dies assembled with gold coated microtubes and aluminum pads [2][3]. With the same metal for micro-tubes and pads, the electrical results revealed the relative stability of this bonding technology at this stage of the reliability tests. Conclusions and Outlooks We successfully assembled bare dies on silicon interposer by using the micro-tube insertion technique at room temperature. The mean Kelvin resistance obtained of 7.2mΩ is competitive with the other alternative techniques for 50µm pitch connection. Moreover we overcame reliability problems exhibited by the other techniques by using the same metals for micro-tubes and pads. Electrical measurements after several reliability tests showed no significant evolution of the resistance of aluminum to aluminum assembled dies. All the results are summarized in Table 3. References [1] F. Marion, et al., Aluminum to Aluminum Bonding at Room Temperature, Proceedings of the 63th Electronic Components and Technology Conference (ECTC), Las Vegas 2013, pp146-153. [2] Colonna, et al., Towards Alternative Technologies for Fine Pitch Interconnects, Proceedings of the 63th Electronic Components and Technology Conference (ECTC), Las Vegas 2013, pp872-878. [3] PhD Thesis of B. Goubault de Brugière, Interconnexions haute densité et intégration 3D: étude du contact mécanique et électrique réalisé par insertion de microtubes, University of Lorraine, France, 2012.