Patterned heteroepitaxial SiGe thin films through. UV Excimer Laser radiation

Similar documents
Micro-Electro-Mechanical Systems (MEMS) Fabrication. Special Process Modules for MEMS. Principle of Sensing and Actuation

Micro-Electro-Mechanical Systems (MEMS) Fabrication. Special Process Modules for MEMS. Principle of Sensing and Actuation

Micro-Electro-Mechanical Systems (MEMS) Fabrication. Special Process Modules for MEMS. Principle of Sensing and Actuation

EXCIMER LASER ANNEALING FOR LOW- TEMPERATURE POLYSILICON THIN FILM TRANSISTOR FABRICATION ON PLASTIC SUBSTRATES

Physics and Material Science of Semiconductor Nanostructures

Chapter 3 Silicon Device Fabrication Technology

Poly-SiGe MEMS actuators for adaptive optics

Amorphous and Polycrystalline Thin-Film Transistors

Laser Crystallization for Low- Temperature Poly-Silicon (LTPS)

EPITAXY extended single-crystal film formation on top of a crystalline substrate. Homoepitaxy (Si on Si) Heteroepitaxy (AlAs on GaAs)

MATERIALS. Silicon Wafers... J 04 J 01. MATERIALS / Inorganics & thin films guide

From sand to silicon wafer

EECS130 Integrated Circuit Devices

General Introduction to Microstructure Technology p. 1 What is Microstructure Technology? p. 1 From Microstructure Technology to Microsystems

ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline:

Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation.

SiGeC Cantilever Micro Cooler

8. Epitaxy. - Extended single-crystal film formation on top of a crystalline substrate

ATOMIC LAYER DEPOSITION OF 2D TRANSITION METAL DICHALOGENIDES

Nucleation and growth of nanostructures and films. Seongshik (Sean) Oh

Thin Film Scattering: Epitaxial Layers

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant

A Nano-thick SOI Fabrication Method

Make sure the exam paper has 9 pages total (including cover page)

Fabrication Technology

Micromachining AMT 2505

Progress in Monolithic III-V/Si and towards processing III-V Devices in Silicon Manufacturing. E.A. (Gene) Fitzgerald

3.46 OPTICAL AND OPTOELECTRONIC MATERIALS

Examples of dry etching and plasma deposition at Glasgow University

MICROCHIP MANUFACTURING by S. Wolf

EE C245 ME C218 Introduction to MEMS Design Fall 2011

COMPATIBILITY OF THE ALTERNATIVE SEED LAYER (ASL) PROCESS WITH MONO- Si AND POLY-Si SUBSTRATES PATTERNED BY LASER OR WET ETCHING

200mm Next Generation MEMS Technology update. Florent Ducrot

FABRICATION ENGINEERING MICRO- NANOSCALE ATTHE AND. Fourth Edition STEPHEN A. CAMPBELL. of Minnesota. University OXFORD UNIVERSITY PRESS

A discussion of crystal growth, lithography, etching, doping, and device structures is presented in

An advantage of thin-film silicon solar cells is that they can be deposited on glass substrates and flexible substrates.

3 Pulsed laser ablation and etching of fused silica

Lecture 22: Integrated circuit fabrication

Low Thermal Budget NiSi Films on SiGe Alloys

DEFECTS IN SILICON-GERMANIUM STRAINED EPITAXIAL LAYERS MARK DYNNA. A Thesis. Submitted to the School of Graduate Studies.

Bulk crystal growth. A reduction in Lg will increase g m and f oper but with some costs

Characterisation of Fe-Ni amorphous thin films for possible magnetostrictive sensor applications

Doping and Oxidation

Laser Machining Processes Laser heat processing divided into 3 regions Heating Melting Vaporization

Technology process. It s very small world. Electronics and Microelectronics AE4B34EM. Why is the integration so beneficial?

Chapter 3 CMOS processing technology

Thin Film Scattering: Epitaxial Layers

Thin. Smooth. Diamond.

Thin. Smooth. Diamond.

Polycrystalline Silicon Thin-Film Transistors Fabricated by Defect Reduction Methods

Near- and mid- infrared group IV photonics

Lecture contents. Heteroepitaxy Growth technologies Strain Misfit dislocations. NNSE 618 Lecture #24

Optically Assisted Metal-Induced Crystallization of Thin Si Films for Low-Cost Solar Cells

Lect. 2: Basics of Si Technology

Previous Lecture. Vacuum & Plasma systems for. Dry etching

Characterization of Rapid Melt Growth (RMG) Process for High Quality Thin Film Germanium on Insulator

Lecture 5. SOI Micromachining. SOI MUMPs. SOI Micromachining. Silicon-on-Insulator Microstructures. Agenda:

A Novel Low Temperature Self-Aligned Field Induced Drain Polycrystalline Silicon Thin Film Transistor by Using Selective Side-Etching Process

Growth and characterization of tensile strained Ge on Ge 1-x Sn x buffers for novel channel layers

Semiconductor Technology

EE 330 Lecture 8. IC Fabrication Technology Part II. - Oxidation - Epitaxy - Polysilicon - Interconnects

Crystallization of Continuing Wave Laser Applications for Low-Temperature Polycrystalline Thin Film Transistors

How to Make Micro/Nano Devices?

Feature-level Compensation & Control. Workshop April 15, 2004 A UC Discovery Project

Microelettronica. Planar Technology for Silicon Integrated Circuits Fabrication. 26/02/2017 A. Neviani - Microelettronica

Hot-wire deposited intrinsic amorphous silicon

EE 434 Lecture 9. IC Fabrication Technology

Study of a-sige:h Films and n-i-p Devices used in High Efficiency Triple Junction Solar Cells.

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing

Strain Engineering for Performance Enhancement in Advanced Nano Scaled SOI-MOSFETs

Institute of Solid State Physics. Technische Universität Graz. Deposition. Franssila: Chapters 5 & 6. Peter Hadley

Strained Silicon-On-Insulator Fabrication and Characterization

Procedia Chemistry 1 (2009) Proceedings of the Eurosensors XXIII conference

Detectors and Coatings for Efficient Systems for Future UV Astronomy

FePd (216 Å) grown on (001) MgO. 2θ(deg)

Radiation Tolerant Isolation Technology

Growth and Doping of SiC-Thin Films on Low-Stress, Amorphous Si 3 N 4 /Si Substrates for Robust Microelectromechanical Systems Applications

Czochralski Crystal Growth

Characterization of Nanoscale Electrolytes for Solid Oxide Fuel Cell Membranes

Review of CMOS Processing Technology

Isolation Technology. Dr. Lynn Fuller

Procese de depunere in sistemul Plasma Enhanced Chemical Vapor Deposition (PECVD)

Thermo-Mechanical Reliability of Through-Silicon Vias (TSVs)

Metallization deposition and etching. Material mainly taken from Campbell, UCCS

Advanced Polymers And Resists For Nanoimprint Lithography

3.2 Amorphous Ge films on Si substrates

Amorphous Silicon Solar Cells

Problem 1 Lab Questions ( 20 points total)

Lecture 1. Introduction to Microelectronic Technologies: The importance of multidisciplinary understanding. Reading: Chapters 1 and parts of 2

Chapter 2 Crystal Growth and Wafer Preparation

Supporting Information

Latching Shape Memory Alloy Microactuator

1 HRL Laboratories, LLC, Malibu, California, Baskin School of Engineering, University of California, Santa Cruz, CA *

Section 4: Thermal Oxidation. Jaeger Chapter 3. EE143 - Ali Javey

Copper Interconnect Technology

Polycrystalline and microcrystalline silicon

EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects

Fabrication Technology, Part I

Transcription:

Patterned heteroepitaxial SiGe thin films through UV Excimer Laser radiation,, F.Gontad, J.C.Conde, E.Martín 1, A.Benedetti 2, C.Serra 2, J.Serra, P.González, B.León Departamento de Física Aplicada 1 Dpto. Mecánica, Máquinas, M Motores Térmicos T y Fluido E.T.S.I.Industriales 2 C.A.C.T.I. Universidade de Vigo (Spain)

Outline Aim of this study Some basics (SiGe heterostructures & Laser processing) Obtained results: Laser assisted growth through LCVD Laser induced epitaxy though PLIE Conclusions Acknowledgements

Aim of this study Produce ultra-thin patterned heteroepitaxial SiGe alloys on Si wafers (Strained Ge rich layer buried under a Si rich cap layer) Si rich SiGe Ge rich s-sige Si (100) wafer Applications Sacrificial layers for producing monocrystalline Micro-(Nano)-Electro-Mechanical-System (MEMS, NEMS) Silicon-On-Nothing (SON) devices for IC technology Approach Use laser assisted processes for producing heteroepitaxial alloys with tailored concentration gradients on Si(100)

Laser assisted techniques: Low thermal budget techniques that avoid heating up the complete substrate to > 500ºC Allow large area as well as local processing Reduce number of processing steps (bottom-up instead of top-down) Fast, relatively cheap and compatible with IC-processes Can be simulated (FEM) for reducing optimization costs

Some basics (SiGe heterostructures & Laser processing) Based on group IV elements (cubic cell) with slightly different lattice constants a Si : 0.5431 nm, a Ge : 0.5657 nm Different micro-structures are possible E.Kasper (ed.) Silicon Germanium and SiGe:Carbon ISBN0852967837 Amorphous (a-si, a-ge, a-sige) Hydrogenated amorphous (a-si:h, a-ge:h, a-sige:h) Crystalline (c-si, c-ge, c-sige) H H 2 (dangling bonds + voids) (saturated dangling bonds + stabilised voids) (mono-, poly-, nano-) Composition and microstructure modifies optical & electrical properties, but also etching behaviour

Problems related to crystalline SiGe heterostructures Trying to match perfectly different lattice constants leads to tetragonal distortion c-si c-ge c-si depending on film composition Tensile / compressive strain depending on film thickness Defects and misfit dislocations s-ge c-si c-si Tailoring concentration profile and thickness is essential for avoiding the formation and propagation of misfit dislocations But: Hydrogen bonds might be helpful Hydrogen can saturate dangling bonds in vacancies, defects, dislocations, and grain boundaries To produce c-sige using Hydrogen containing precursors should be beneficial and avoid post annealing processes with Hydrogen

Some basics (SiGe heterostructures & Laser processing) Si(100) a-si:h a-ge:h Si(100) LCVD PLIE Si(100) c-si s-sige Laser Induced Chemical Vapour Deposition (LCVD) (in parallel configuration) 1 st step : Photolysis of GeH 4, Si 2 H 6 in He 193 nm 6.4 ev Substrate Following steps : Chemical reactions in the gas phase and on the substrate surface lead to film formation at T s > 120 ºC

Pulsed Laser Induced Epitaxy (PLIE) (in perpendicular configuration) 1. Absorption (few nm in depth and in a well defined area) 2. Fast local heating of a shallow near surface region (within few ns) a-si:h a-ge:h Si(100) 193 nm 25 ns PLIE Si(100) c-si s-sige 1.- Melting of the coating and the Si wafer surface 2.- Mixing of the elements in the molten pool (tailoring of the [Ge] gradient) 3.- Crystallisation using the substrate as seed (heteroepitaxial growth)

Obtained results: Laser assisted growth through LCVD a-si:h(6nm)/a-ge:h(3nm) bi-layers with uniform film thickness on Si(100) wafers Patterned a-si:h(40nm)/a-ge:h(20nm) bi-layers (3 µm x 5 µm) using a shadow mask

Obtained results: Laser assisted growth through PLIE Formation of an heteroepitaxial alloy (with a buried Ge rich layer in the inner part of a PLIE spot) XPS Ge3d et al. Applied Surface Science 254 (2008) 6030 6033

Numerical simulation of the Heat Conduction through Finite Element Method (FEM ) 1. Calculate the decay of Laser intensity when penetrating into the material: I(r,t) = I o [ 1 R( n, κ, θ )] Exp( αy) o 2. Consider: - initial surface Temperature of 25ºC - heat is produced by the laser beam Intensity T T ( r, 0 ) = T o - k = I(r,t) z y( s)=0 Time Penetration Depth 3. Apply the Heat Conduction Differential Equation to each consecutive cell of a grid simulating the structure T < T MP T > T MP

a Si:H a Ge:H c Si Whole bilayer melting achieved with 110 mj/cm 2 Substrate melting requires energy density above 350 mj/cm 2

Compatibility with conventional IC s fabrication technology MBE Si over-layer growth and etching of mesa structures with several lithography steps MESA STRUCTURE Epitaxial Si grown trough MBE RIE * Wet Etching SiGe Sacrificial layer grown through LCVD and PLIE Si (100) Substrate RIE * : Reactive Ion Etching

Highly selective etching at RT (indicating strong gradient and excellent epitaxy) 30 nm 1550 nm

BUT Borders of the spots are less well defined Whereas patterns apparently maintain their structure after PLIE treatment with 10 pulses of 240 mj/cm 2

Enhancement of the microstructure aspect ratio BEFORE PLIE AFTER PLIE PLIE 240 mj/cm 2

Surprising changes in composition Features are now NOT perfectly uniform 10 µm [0 %] [100 %]

a-si:h a-ge:h Si(100) a-ge:h melts earlier (965K) than a-si:h (1410K) and solidifies later Liquid Ge moves (segregates) during several tenth of ns, until solidification l-ge a-si:h l-ge Si(100) c-si Si(100) s-sige Model has been confirmed by simulation (FEM), that include thermal stress calculations Centre and edge have different melting thresholds producing thermal stress gradients, thus modification of Ge segregation Changes in etching behaviour of the pattern!!!

Melting threshold higher on the lateral edge Complex thermal gradients Thermal stress

asi Temperature profile asi Stress profile age age csi csi 301.7 T (K) 1418 120 S1 (MPa) 165 J.C.Conde et al. Thin Solid Films 518 (2010) 2431 2436 Concentration profile [0] [100] Mass fraction (%)

Conclusions LCVD on Si(100) wafers : Uniform a-si:h/a-ge:h bi-layers can be produced, both locally and in large areas PLIE of LCVD grown bi-layers : Heteroepitaxial structures with s-ge rich alloy buried under a Si rich layer Lateral Ge gradients when patterns are treated Numerical simulation of the PLIE process can predict Ge gradients both, vertical and lateral Samples have been successfully used as sacrificial layers in an IC process

Acknowledgements Financial support: Xunta de Galicia ( CESOLAS, 07REM007V11PR ) Ministerio de Educación y Ciencia ( VIRTUSLASER, MAT2008-02350, SIMBIO, EUI-2008-00177 ) Special thanks to J.Brugger, L.Doeswijk and M. van den Boogaart, EPFL Lausanne ( Nanostencils ) L.Fornarini, ENEA Frascati ( Modelling ) T.Sulima and I.Eisele, UniBW München ( IC processes )