SLIM TM, High Density Wafer Level Fan-out Package Development with Submicron RDL

2017 IEEE 67th Electronic Components and Technology Conference SLIM TM, High Density Wafer Level Fan-out Package Development with Submicron RDL YoungRae Kim 1, JaeHun Bae 1, MinHwa Chang 1, AhRa Jo 1, Ji Hyun Kim 1, SangEun Park 1, David Hiner 2, Michael Kelly 2, and WonChul Do 1 1 Amkor Technology Korea, Inc., 150, Songdomirae-ro, Yeonsu-gu, Incheon 21991, Korea 2 Amkor Technology, 2045 East Innovation Circle, Tempe, AZ 85284, USA e-mail: youngrae.kim@amkor.co.kr Abstract A novel HD-FO package platform was introduced with a hybrid RDL structure. An HD-FO package with hybrid RDL could enables higher routing density and multi die construction in a planner configuration. The 1-μm and submicron RDL wafers were fabricated at a foundry and then the essential parts of the inorganic RDL were integrated with Amkor s internal organic RDL process making a hybrid structure. Also, the vertical interconnection on a hybrid RDL made 3-dimentional package construction. Key processes including via reveal, top die attach, and vertical package stacking were successfully demonstrated. Technical challenges in HDFO package development was discussed as well as the reliability performance results both in the package and at the board level. Keywords-high density fan-out package, hybrid RDL, diereconstruction, POP I. INTRODUCTION Recently, high-density fan-out (HD-FO) wafer-level packaging has been introduced to the industry for mobile applications. HD-FO is of great interest because of its desirable characteristics of high density routing, good electrical performance, thin profile with Package-on-Package (PoP) construction, and multi die architecture. A key contributor to HD-FO technology is an ultra-thin, fine-pitch redistribution layer (RDL) at the bottom of the HD-FO package replacing traditional substrates which have limited the line and space to 15 μm/15 μm. It is expected that the HD-FO package would provide high functionality in a small form factor, superior electrical performance, and high thermal dissipation requirement to the applications [1]. In this study, a hybrid HD-FO package which uses inorganic and organic RDLs has been introduced. A distinctive characteristic of SLIM TM (Silicon-Less Integrated Module) packaging (as this design is called at Amkor Technology) is that it uses 1-μm and submicron line and space RDL design with an inorganic passivation layer including silicon oxide and silicon nitride. Since the RDL features are more aggressive than organic based RDL, SLIM TM could have much dense RDL and possibility of enabling multi die construction with serpentine structure between the dies. Detailed descriptions of top die bump array, simplified RDL construction, key processes for a hybrid HDFO and technical challenges are described. II. TEST VEHICLE INFORMATION A. Package structure The test vehicle is composed of two dies in a planar configuration with the gap of 0.1 mm. The top dies were placed on inorganic RDL directly with copper (Cu) pillar flip-chip interconnection. SLIM packaging utilizes both inorganic and organic RDL as building blocks for signal and power routing. Mold compounds cover the top die and fanned-out RDLs provide mechanical support for the package. Tall Cu pillars were embedded in mold compound so that these Cu pillars enabled vertical interconnections between RDL and top package. The ball grid array (BGA) balls were placed at the bottom of the package in 0.4-mm pitch. Optionally, four land side capacitors (LSCs) were attached in the backside of the package. The schematic of the SLIM and SLIM POP package is shown in Fig. 1. Figure 1. Schematic representation of (a) SLIM and (b) SLIM POP package structure. B. Top die design One of the primary advantages of SLIM technology is to enable a multi-die construction within a package. In such a construction, the die gap adjacent to each die is connected by serpentine structured RDLs. The 1-μm and submicron inorganic RDL provides high density routing for this requirement. Also, typical bump arrays of multi-chip module in SLIM designs were composed of at least two categories. As shown in Fig. 2, fine pitch and smaller size bumps were arranged in near the die gap and the rest of the area was composed of larger bump pitch and size. Therefore, each single die has mixed bump pitches and sizes of Cu pillar. The size of large top die was 6 x 8 mm and that of small die was 4 x 8 mm. Around 5000 and 4000 Cu pillars were formed in large and small die, respectively. 2377-5726/17 $31.00 2017 IEEE DOI 10.1109/ECTC.2017.334 8

Figure 2. Schematic representation of bump arrays in multi-chip construction. C. Inorganic and organic RDL The interposer size was 15 x 15 mm on 300-mm wafers. Single or double layers of inorganic RDLs were fabricated on a Si wafer. Dielectrics of inorganic RDLs were silicon nitride and silicon oxide materials which are commonly used in back end of line (BEOL) of wafer fabrication. In addition, one or two organic layers were added onto the inorganic layers making a hybrid RDLs. The line/space of the inorganic RDL varied from submicron to 1/1 μm and that of the organic RDL was 5/5 μm to 10/10 μm. The combination of inorganic and organic RDL is a key feature of SLIM construction. The serpentine RDL for multi die routing and the structure of hybrid RDLs are shown in Fig. 3. D. Test chain design In order to verify the reliability and the integrity of SLIM technology, the test vehicle includes hundreds of test chains throughout the BEOL of the top dies, Cu pillar solder joint, μ-bump via to inorganic RDL, inorganic to organic RDL, and BGA balls. Since SLIM technology uses ultra-thin and stiff inorganic RDL, specific test chains were placed in mechanically weak areas, such as the peripheral areas of the silicon (Si) top die, the gap between top die, and the package edge. Therefore, the chains could detect open/short and crack failure in the electrical test after reliability. Examples of test chains are depicted in Fig. 4. Other test chains including board level reliability (BLR) were connected through BGA balls but also passing into and out of the inorganic and top die BEOL lines. These BLR chains also detect inorganic RDL layer failures during BLR test. Figure 4. Examples of 0 and 45 rotated serpentine and comb structures were embedded onto die edge, die-to-die and package edge for crack and open/short failure detection. Line spacing of these structures were presented in 1/1 μm, 0.5/0.5 μm, and 0.5/1.5 μm. III. SLIM INTEGRATION AND ASSEMBLY Figure 3. (a) Serpentine structure of the inorganic RDL, (b) structure of hybrid RDL with single layer of inorganic RDL and double layers of organic RDLs. A. Organic RDL process The fabrication of organic RDL for SLIM packaging provides an advantage to multiple organic RDLs with fine line spacing. Most of routing requirement can be integrated in the inorganic layer(s), which have superior routing density, and the addition of single or double layers of organic RDL complement this high-density routing to create the final SLIM construction. Thus, the additional fabrication process of organic RDLs can be minimized in an outsourced semiconductor assembly and test (OSAT), which means the cycle time of RDL process can be shorten in a hybrid HD- FO package process. Also, the features of the organic RDL process to SLIM is not aggressive but could accept much complex design in presence of hybrid RDLs. L/S 10/10μm was sufficient so there are no concerns of making fine feature RDLs such as L/S 2/2μm or below. Therefore, the fabrication process in SLIM designs becomes simpler than multiple layers of organic RDLs and this can translate into higher yield. Examples of the fabrication processes in organic RDL which requires only three step mask process and additional under-bump metallization (UBM) pad of single mask process are presented in Fig. 5. 9

Figure 7. M1 layer to via connection after dry etching of via and bump pad plating. Figure 5. Typical organic RDL process in SLIM designs: (a) 1st passivation layer, (b) Cu RDL, (c) 2nd passivation, and (d) UBM pads. B. Si removal & via etch To use ultra-thin inorganic RDL from an interposer wafer, the bulk Si should be removed from the interposer wafer during the SLIM process. A traditional wafer back grinding (WBG) process was applied and then followed by a Si etching process to remove the final bulk silicon. Photoresist (PR) was used to define the via and then, the inorganic passivation was opened by a dry etching process resulting in the via opening. Then, the revealed M1 metal openings were connected by plating process of the bump pad materials. Via reveal processes are summarized in Fig. 6. C. Top die bonding Top dies were bonded to SLIM RDL in a chip-last approach. After fabrication of RDL and μ-bump pad, the SLIM interposer wafers were transferred to the assembly process. Only known good SLIM interposer dies were used in assembly with known good top dies attached using mass reflow. This is a key advantage of the chip-last approach, namely that only good SLIM interposer sites receive good functional die. The mass reflow in SLIM process was in Chip on Wafer (CoW) fashion. It is expected that the CoW mass reflow has lower risk of ultra-low dielectric constant (ULK) layer damage compared to laminate-based reflow. Traditional mass reflow uses Si top die bonding to a laminate substrate having a high coefficient of thermal expansion (CTE) mismatch. Thus, the ULK layer damage was often detected after mass reflow or reliability test in mass reflow process [3]. However, CoW mass reflow would have less residual stress because the CTE mismatch between top die and the wafer is minimized. A photo of the top die bonding to the RDL interposer is shown in Fig. 8. Figure 6. Via reveal process flow. Seamless contact via from M1 metal layer to the bump pad is one of the most critical process for the SLIM construction. Typical etch species for dielectric etch process could produce by-products on the wafer surface [2]. Careful selection of etch chemistry has been accomplished so that post etch residues can be adequately cleaned. Once the etching process has been optimized, the bump pad plating follows to form the connection between M1 metal and the bump pad. Fig. 7 shows contamination-free via and seamless interconnection to the bump pad. Figure 8. (a) Chip on Wafer bonding with mass reflow (b) A image of solder joint shape with mass reflow. D. Gap filling for micro solder bump joint Once the top die attached to the hybrid RDLs, the gap filling process was performed to fill the gap. 30-μm pitch Cu pillar solder bump array was successfully filled with capillary underfill (CUF) material. There was no 10

delamination between epoxy mold compound and underfill and the interface of the underfill to inorganic passivation layer. Also, the voids were not detected in gap filling process of the SLIM package after assembly and reliability test. Careful material selection was required for the capillary underfill material because of the reliability concern of SLIM. In addition to CUF, the mold underfill (MUF) was evaluated to the same test vehicle. The gap filling performance with MUF process showed good and there was no delamination and void as well. In MUF process, gap filling and wafer molding are performed in a single process so that process cost and cycle time could be reduced than CUF process. Also, MUF could have homogeneous material structure compared to CUF applied SLIM package. The SLIM package with MUF has also passed reliability requirement. Comparative gap filling images from CUF and MUF are shown in Fig. 9. The difference of the filler size distribution can be seen in CUF and MUF cases. Figure 10. (a) A photo of top package attachment at the wafer level and (b) A cross section image of SLIM PoP structure. After top package attach with mass reflow, the gap between the top package and the bottom package of the SLIM design was filled with gap filling material. Gap filling for the top package requires optimization of the gap filling process. The target application of the top package in SLIM designs is an integrated memory package that has a peripheral array with no balls in the center of the package. In these arrangement, the void could be formed in the gap because the capillary force is driven by small gaps of BGA balls resulting in faster flow rate along the peripheral lines [4]. The mechanism of void entrapment has been studied and overcome by optimizing the gap filling process. The mechanism of void entrapment and scanning acoustic tomography (SAT) images are shown in Fig. 11. Figure 9. Cross-section images of the gap filled with; (a) and (b) capillary underfill, (c) and (d) mold underfill. E. Tall pillars for vertical interconnection Tall pillar interconnection was developed for 3D integration called SLIM PoP. Cu tall pillars were plated onto a peripheral ring of SLIM package and then the wafer has been molded. By applying mold grind process to the molded wafer the package height can be controlled to specified height and all the Cu tall pillar can be exposed at the same time. In the process of the co-grinding of mold compound and Cu tall pillar, mold compound layer is remained during mold grind process and there is no direct contact of Cu contaminant to the top die having active device. Then, the exposed tall pillars were bonded with BGA balls of top package resulting in vertical interconnection. High throughput mass reflow was applied in a wafer level process for SLIM top package assembly and showed good solder joint performance. A photo of the top package mass reflow at the wafer level and the structure of SLIM PoP are shown in Fig. 10. Figure 11. Void formation in gap filling process (a) after dispense, (b) mid of the gap filling step, (c) void formation inner area of the package, (d) SAT images of void captured samples, and (e) SAT images of optimized samples. Another concern of tall pillar assembly was mechanical robustness of the Cu tall pillar in reliability test. In SLIM package structure, around 200μm tall Cu pillar is surrounded by epoxy mold compound material and the tall pillar is placed on the inorganic passivation layer directly. The CTE of Cu is known as 16 ppm and typical epoxy mold compound has ~10 ppm below glass transition temperature, T g and ~ 30ppm above the T g. It was expected that the CTE mismatch between tall Cu pillar and mold compound could result in high stress at the bottom of the tall pillar. Therefore, 11

the tall pillar bottom area was investigated after assembly and reliability testing to ensure the robustness of the SLIM PoP structure. Fig. 12 shows the cross section of tall pillar area after Temperature Cycle, Condition B (T/C B) 1000 cycles and confirmed no mechanical damage on the inorganic passivation layer. The reliability validation of tall pillar structure has been performed in two different test vehicles and passed reliability requirement in both cases. Table 1 showed the results of package and board level reliability. Hybrid HD-FO package reliability was very promising and passed moisture resistance test (MRT) level 3, temp cycle, high temperature storage (HTS), and Unbiased Highly Accelerated Stress Test (UHAST). A key contributor to the package reliability was material combinations of the HD-FO design. Also, the board level temperature cycle, and drop test were performed and showed outstanding results. Major factors to SLIM BLR performance are the solder ball composition and material combination of SLIM package. The failure mode of temp cycle test was a solder ball crack at the package corners. The failure mode of temp cycle is presented in Fig. 13. Table 1. Reliability test result from: (a) package and (b) board level tests. Figure 12. A section of tall Cu pillar SLIM interface after reliability test of TC 1000 cycles. IV. TECHNICAL CHALLENGES IN SLIM A. Package handling Since SLIM packaging is an extremely thin construction, package handling needs to be optimized. The cross section of the SLIM package s edges is ultra-thin and the package was mainly composed of epoxy molding compound (EMC) and small portion of Cu RDL and passivation material. Package edge crack was detected during unit handling like electrical test, reliability test and arranging in a tray. In an internal mechanical strength test, the thinner HDFO has the less fracture load and the fracture load was a half of that of laminate package. In case of SLIM POP, the fracture load was exceptionally higher than non-pop structure. Also, the weight of HD-FO package is very light and the packages could be lifted up during handling and transporting. The weight of the SLIM package and SLIM PoP design are only 0.2g ±0.1g and 0.46g ±1g, respectively. B. Cost of the interposer wafer SLIM utilizes interposer wafers as a building block for RDL fabrication so the cost of the interposer affects the cost of the SLIM package. In fact, the interposer cost accounts for high portion of total SLIM package. Main driver for fan-out package in the industry was low cost and HD-FO is not an exception. Thus, cost reduction activity for HD-FO is important. V. RELIABILITY PERFORMANCE The reliability performance of SLIM package was evaluated in package and board level testing. Both reliability tests were performed in accordance with JEDEC standard. Figure 13. Failure mode of temperature cycle test. VI. CONCLUSION An HD-FO package with hybrid RDLs has been evaluated and key processes for the hybrid HD-FO were reviewed. The organic RDL process in an OSAT facility requires only four photolithography steps which can provide benefits to yield management. The connections between M1 12

metal line to bump pad was well defined with via reveal process. Fine pitch Cu pillar bonding of top dies with mass reflow was also demonstrated and the underfill process with both CUF and MUF showed good gap filling performance in SLIM package. It is also proven that HD-FO with hybrid RDLs can be extended to 3D interconnection with vertical Cu pillars. The reliability of HD-FO met the industry requirement, MRT L3, T/C, UHAST and HTS, and the board level reliability of 15-mm x 15-mm sized HD-FOs showed good performance. ACKNOWLEDGMENTS The authors special thanks to the contributions of Amkor design teams, process engineering teams, material suppliers and technical advisors for SLIM development. REFERENCES [1] V. S. Rao et al., "Development of High Density Fan Out Wafer Level Package (HD FOWLP) with Multi-layer Fine Pitch RDL for Mobile Applications," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 1522-1529. [2] S. B. Kim, and H. Jeon, Characteristics of the Post-Etch Polymer Residues Formed at the Via Hole and Polymer Removal Using a Semi-Aqueous Stripper, 2006 Journal of the Korean Physical Society, 49, 5, 2006, pp. 1991-1997. [3] K. Murayama, M. Aizawa and T. Kurihara, "Low stress bonding for large size die application," 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), San Diego, CA, 2015, pp. 1846-1853. [4] K. Gilleo, The Chemistry & Physics of Underfill, Jul. 2014, [online] Available: http://www.ettrends.com/files/nepwest98_chem-uf.pdf. 2017, Amkor Technology, Inc. All rights reserved. SLIM TM is a trademark of Amkor Technology, Inc. 13