N9000 PTFE Processing Guidelines

Similar documents
RO4835T Core/RO4450T Bonding Layers Multi-Layer Board Processing Guidelines

RF-43. General Processing Guidelines

Cer-10. General Processing Guidelines

RO3000 and RO3200 Series High Frequency Laminates STRIPLINE AND MULTILAYER CIRCUITS

Corrective Action: 1. Determine type of nailhead, single sided nailheading or bidirectional

RT/duroid 5870/5880 High Frequency Laminates Fabrication Guidelines

PRELIMINARY. RO4533, RO4534, AND RO4535 Laminates. Preliminary Data Sheet Antenna Grade Laminates

RO4000 Series High Frequency Circuit Materials

RO4000 Series High Frequency Circuit Materials

How Printed Circuit Boards are Made. Todd Henninger Field Applications Engineer Midwest Region

High Frequency Circuit Materials Attributes John Coonrod, Rogers Corporation

Taconic Advanced Dielectric Division. Thomas McCarthy. Sean Reynolds. Jon Skelly

Figure 1 Introduction Figure 2 Line Land Inner copper layer Plated through hole Fig. 1

No Process Guidelines. Laminate R-1755C Prepreg R-1650C. High Reliability Glass Epoxy Multi-layer Materials

FR402 Processing Guide

I-Speed Processing Guide

No Process Guidelines. Laminate R-5775 Prepreg R High Speed, Low Loss Multi-layer Materials

No Process Guidelines. Laminate R-5785 Prepreg R High Speed, Low Loss Multi-layer Materials

No Process Guidelines. Laminate R-5725 Prepreg R High Speed, Low Loss Multi-layer Materials

FR408 Processing Guide

New Developments in PCB Laminates. Dean Hattula, John Coonrod Rogers Corporation Advanced Circuit Materials Division

I-Tera MT40 Processing Guide

FABRICATING HIGH CURRENT, HEAVY COPPER PCBS

IS410 Processing Guide

Taconic Advanced Dielectric Division. Thomas McCarthy. Sean Reynolds. Jon Skelly

How to select PCB materials for highfrequency

DE104i Processing Guide

Astra MT77 Processing Guide

FR408HR. Processing Guide. Part 1: Prepreg Storage and Handling. Part 2: Innerlayer Preparation. Dimensional Stability. Handling Suggestions

ICDs (InterConnect Defects) What are they? Where do they come from? How can we make them go away? Doug Trobough Suixin Zhang

FR408HR & FR408HRIS Processing Guide

IS620i Processing Guide

: GA-170-LE/ GA-170B-LE

: GA-HF-14/ GA-HFB-14

ALTIUMLIVE 2018: NAVIGATING THE COMPLEXITIES OF PCB MATERIAL SELECTION

The most common methods used by the electronic industry to laminate multilayer circuits:

Innovative PCB Solutions. Win time and flexibility benefit from Swiss quality. THE PCB CHALLENGE Doing it together

: GA-170-LL/ GA-170B-LL

Troubleshooting. for. Printed Board. Manufacture. and Assembly IPC PE-740. Revision A December Developed by THE INSTITUTE FOR INTERCONNECTING

Device Attachment Methods and Wirebonding Notes for RT/duroid and RO4000 Series High Frequency Laminates

Flexible PCB Plating Through Hole Considerations, Experiences and Solutions

Introduction Conductors. Supply Planes. Dielectric. Vias PCB Manufacturing Process Electronic Assembly Manufacturing Process

Welcome to Streamline Circuits Lunch & Learn. Design for Reliability & Cost Reduction of Advanced Rigid-Flex/Flex PCB Technology

Qualification and Performance Specification for High Frequency (Microwave) Printed Boards

FR406N Processing Guide

Flexible Substrates for Smart Sensor Applications

Low CTE / High Tg FR-4 with High Heat Resistance

IS620i. Part 1: Prepreg Storage and Handling. Part 2: Innerlayer Preparation. appropriate environmental control.

Thermal image of 0603 capacitor at the center of a microstrip (47pF/250V/C0G) assembled on RF-35TC under 200 watts applied power.

Basic 4-layer manufacturing process

The Anatomy of a PCB SINGLE-SIDED BOARD

Building HDI Structures using Thin Films and Low Temperature Sintering Paste

MICROWAVE & RF MATERIALS GUIDE

Yash Sutariya President

TECHNICAL DATA SHEET DESCRIPTION PHYSICAL CHARACTERISTICS PRODUCT CHARACTERISTICS ETERTEC PR8200Y1 PHOTO-IMAGEABLE COVERLAY

TECHNICAL DATA SHEET 1 P a g e Revised January 9, 2014

Via Formation Process for Smooth Copper Wiring on Insulation Layer with Adhesion Layer

CANDOR Industries Inc. High Quality PCB Manufacturing Solutions

LEAD-FREE ASSEMBLY COMPATIBLE PWB FABRICATION AND ASSEMBLY PROCESSING GUIDELINES.

Chapter 14. Designing with FineLine BGA Packages

Part One Introduction

Stackup Planning, Part 1

Thermal Reliability of Laser Ablated Microvias and Standard Through-Hole Technologies as a Function of Materials and Processing

The Optimal Passive Thermal Management Soldering and Electrically-Isolating Power Semiconductors to Within 33-micron (1.3 mil) of The Heat Sink

Sherlock 4.0 and Printed Circuit Boards

PCB Production Process HOW TO PRODUCE A PRINTED CIRCUIT BOARD

Verifying The Reliability Of Connections In HDI PWBs

Manufacturing Capacity

Low Dielectric Constant 3.9. RoHS/WEEE compliant. SMT Board Designs using LCCC s or other low expansion chip carriers (See Figure 1)

Option Technologies. Ventec International Group Offshore Masslam Solutions From Prototype To Volume. Drilled Masslam from Taiwan

Option Technologies. Ventec International Group Offshore Masslam Solutions From Prototype To Volume. Drilled Masslam from Taiwan

Flexible Printed Circuits Design Guide

Polymer Composites Incorporated

PEC (Printed Electronic Circuit) process for LED interconnection

IPC-6012DA with Amendment 1. Automotive Applications Addendum to IPC-6012D Qualification and Performance Specification for Rigid Printed Boards

Arlon. Our Suppliers. 4B Delta Drive Tewkesbury Gloucestershire GL20 8HB United Kingdom

14. Designing with FineLine BGA Packages

NP-180R NAN YA PLASTICS CORPORATION ELECTRONIC MATERIALS DIVISION. COPPER CLAD LAMINATE DEPARTMENT NO TUNG HWA N. ROAD, TAIPEI, TAIWAN.

Modeling Printed Circuit Boards with Sherlock 3.2

Scotch-Weld TM. Epoxy Adhesive/Coating Technical Data July, 2011

Beam Leads. Spider bonding, a precursor of TAB with all-metal tape

Qualification and Performance Specification for Flexible Printed Boards

Cycom Modified Cyanate Prepreg System

!"#$#%&#'(() ) **+,-./01)2-,-.3)456,1) /0! **)

Freescale Semiconductor Tape Ball Grid Array (TBGA) Overview

Interconnection Reliability of HDI Printed Wiring Boards

Designing With High-Density BGA Packages for Altera Devices. Introduction. Overview of BGA Packages

GRAPHIC MANUFACTURING CAPABILITY Q217-18

Precision Engineered Parts

Flex and Rigid-Flex Printed Circuit Design

Bending Impacts Layers

Your partner solutions

Materials for High-Reliability Applications: All IPC-4101-Grouped Materials are not Created Equal

Microwave & RF Materials Guide

APPLICATION NOTES COMBINING DIELECTRICS IN MULTILAYER MICROWAVE BOARDS.

Insulated Metal Substrates

Transcription:

N9000 PTFE Substrates The Park/Nelco (previously known as Metclad) NY, NX, and NH families of RF and Microwave materials are woven fiberglass/ptfe composites for use as printed-circuit substrates. The NY, NX, and NH materials are used in high-frequency applications where low loss and controlled dielectric constant and thickness (and thus impedance) are required. The control of these parameters is particularly important Note: The following guidelines are provided to assist Park/Nelco laminate and prepreg users with general recommendations for successful processing during PWB fabrication. The recommendations are for general review purposes only and process adjustments may be required to achieve optimum results in your specific manufacturing environment. for applications such as antennas, filters, couplers, amplifiers, power dividers, and combiners. Using precise control of the resin-to-glass Ratio, Park/Nelco is able to offer a range of materials from the lowest dielectric constant and dissipation factor (the NY family) to more highly reinforced laminate (the NX family), and finally to the low cost, woven reinforced, ceramic filled material (the NH family) with improved dimensional stability. The N9000 materials used in stripline or microstrip applications can be processed using conventional PTFE board fabrication processes and techniques. When a hybrid or mixed material build is used, the NY, NX, and NH materials can also be processed using many typical glass-epoxy or glass-thermoset (i.e., N4000-6, N4000-13, and N6000-21) process parameters with few in-line modifications. Material Handling & Storage Store laminate and bond ply material in a flat orientation and in a dry environment (<50% RH). Do not bend, scratch, or dent laminate. BONDING PTFE MULTILAYER PRINTED CIRCUITS PTFE multilayer bonding is different than FR4 multilayer bonding. FR4 multilayer bonding utilizes laminate cores, prepreg, and copper foil. PTFE multilayer bonding utilizes only laminate cores and bonding films. There is no commercially available prepreg for PTFE. There are two types of PTFE multilayer printed circuit boards: all PTFE and bonding film constructions and hybrid PTFE and FR4 constructions. Hybrid PTFE and FR4 Construction: There are two types of hybrid constructions: single layers of PTFE core bonded to one side or both sides of a FR4 printed circuit board. Hybrid constructions normally utilize a sequential lamination process. The FR4 multilayer board and the PTFE multilayer board are processed separately. Utilize the bonding process for PTFE and bonding film constructions listed below for the PTFE portion of the hybrid construction. The two assemblies are then bonded together. The copper ground plane of the PTFE board is bonded to the FR4 board with FR4 prepreg. PTFE and Bonding Film Construction: The two most popular bonding films for PTFE multilayer constructions are thermoplastic FEP, type C, films (fluorinated ethylene propylene) or thermoplastic chlorotrifluoroethylene films such as Neltec FV6700. FEP films are recommended for any PTFE multilayer board that requires high temperature post processing such as plating reflow and leveling. The melting point of FEP is higher than the tin/lead reflow or hot air leveling temperatures and therefore circuit delamination due to heat should not happen. Also, FEP is recommended when bonding to metal ground planes or layers that are mostly metal.

SURFACE PREPARATION: Copper: A light micro-etch can be used to remove any residues of etch-resist from the copper circuitry and to provide a greater surface area to which the bonding film will adhere. Mechanical cleaning should NOT be used. Alternative oxides should be used on large areas of copper, such as ground planes, to improve the bond. Brown oxide treatments can be used in lower temperature applications. Substrate: All PTFE surfaces must be clean, dry and free of residues from the chemical processes. All PTFE surfaces must be activated prior to bonding. Use the plasma or sodium etch parameters outlined in the plating section below. PTFE that has been soiled on previous runs must be chemically cleaned and re-activated. Bonding Film: This requires no preparation, but lint-free gloves must be worn when handling the film to prevent contamination. After the above preparation, the materials must be stored in a clean area and should be used within 24 hours. FV6700 BONDING: Chlorotrifluoroethylene films such as Neltec FV6700 have been used to bond PTFE laminate cores together for over 25 years. This unreinforced film melts completely during the lamination process and care should be exercised to prevent excess squeeze out due to over pressure. FV6700 would be considered a medium to high flow adhesive. Surface Preparation: The copper and dielectric surfaces being bonded must be clean and dry. Inner layers should be handled with clean gloves along the periphery and should never be scrubbed. Only chemical cleaning is recommended for inner layers. Organic cleaner is often used along with sulfuric acid and DI water rinses. All PTFE layers should be treated to enhance adhesion. Plasma or sodium etch works well. (Both processes are described below in the plating section). The copper ground planes should be oxide treated prior to bonding to increase surface roughness. As stated above, alternative oxides work well. Red or brown oxide can be used in lower temperature applications. Tooling: Standard pin or slot tooling systems may be used. Tooling holes and slots on inner layers should be surrounded by copper for strength. Stainless steel (304) caul plates are preferred to prevent distortion of circuitry during bonding. Tooling plates must be flat and parallel. FV6700 is a medium to high flow adhesive. Press platens and tooling plates must be flat and parallel to prevent excessive squeeze out and insure uniform bond strength.

FV6700 Lay Up: Lay up must be performed in a clean dust-free environment. FV6700 bond ply material is sold.0015 thick. One layer of bond ply has been found to be adequate for filling up to one-ounce copper signal layers. Use of 2 layers of FV6700 is not recommended due to squeeze out of the bond ply. FV6700 is a medium-to-high flow bond ply. FV6700 Bonding Techniques Lay the bonding film between the laminate cores to be laminated. Insert a thermocouple into the laminate at the bond line. Load into a press pre-heated to 235 C. Apply pressure: 100-200 psi. (Use the minimum pressure possible to prevent excessive adhesive flow.) Hold in the press until the laminate reaches 220 C (This may require 20-30 minutes) Hold for an additional 15 minutes after the laminate has reached 220 C. (The final temperature at the bond line will approach 235 C). Cool under pressure to less than 90 C before removing from the press. FV6700 Bonding Film Lamination Parameters FEP BONDING Few adhesives can match the broad capabilities of FEP film. Its excellent resistance to both chemicals and high temperatures makes possible bonded structures suitable for service in applications where ordinary adhesives may not be equal to the task. FEP produces strong bonds between two surfaces of PTFE or between PTFE and other substrates that can withstand temperatures greater than 332 C (630 F) above the PTFE melt temperature. FEP is highly viscous at its melting point but it is considered a medium-to-high flow adhesive. Normally, FEP Type C films are used. The type C film is primed to enhance adhesion.

Surface Preparation: The copper and dielectric surfaces being bonded must be clean and dry. Inner layers should be handled with clean gloves along the periphery and should never be scrubbed. Only chemical cleaning is recommended for inner layers. Organic cleaner is often used along with sulfuric acid and DI water rinses. All PTFE layers should be treated to enhance adhesion. Plasma or sodium etch works well. (Both processes are described below in the plating section). The copper ground planes should be oxide treated prior to bonding to increase surface roughness. Alternative oxides should be used. Red or brown oxide can be used in lower temperature applications. Tooling: Standard pin or slot tooling systems may be used. Tooling holes and slots on inner layers should be surrounded by copper for strength. Stainless steel (304) caul plates are preferred to prevent distortion of circuitry during bonding. Although FEP is a very low flow adhesive, press platens and tooling plates must be flat and parallel to prevent excessive squeeze out and insure uniform bond strength. FEP Lay-Up: A solid copper border should be utilized on inner core layers to improve handling. For high layer count applications, partial copper borders should be used and offset on adjacent layers so that total thicknesses across the panel remain uniform to minimize circuit distortion after lamination. Due to its high viscosity, the thickness of the FEP film must be adequate to fully encapsulate circuit features..002-inch FEP film is required to encapsulate 1 oz copper features and.001-inch film is required to encapsulate.5 oz copper features. During lay-up, copper foils or thin aluminum foils (less than.003 inches) should be used as release materials. FEP Bonding Techniques Lay the bonding film between the laminate cores to be laminated. Insert the thermocouple into the laminate at the bond line. Load into a press pre-heated to 296 C. Apply pressure: 100-200 psi. Hold in the press until the laminate reaches 271 C (This may require 30-40 minutes) Hold for an additional 40 minutes after the laminate has reached 271 C. (The final temperature at the bond line will approach 296 C). Cool under pressure to less than 90 C before removing from the press. The recommended bonding cycle shown in the figure below has a 40 minute soak at 296 C (565 F) with 100 psi of pressure. The critical portions of the cycle are those above 271 C (520 F), the melt point of FEP. Temperature ramp rates should be adjusted to insure good temperature uniformity at temperatures above the melt point.

FEP Bonding Film Lamination Parameters Drilling Care must be taken when drilling PTFE materials. PTFE is chemically inert. There is no material available that can chemically remove drill smear from a hole in a PTFE circuit board. The only way to remove the smear is to use a larger drill bit and cut the smear out of the hole. The Neltec NY, NX and NH PTFE materials should be drilled using highly polished carbide tools. The use of repointed tools is not recommended. Panels can be drilled in stacks based on total thickness. The total stack height, including entry and backup materials, should not exceed 70% of the effective flute length of the drill bit. The use of hard phenolic, rigid entry.020-.032 (0.5 mm - 0.8 mm) and backup.060-.080 (1.5 mm 2.0 mm) material is recommended. PTFE laminates are much softer than FR4 laminates. The edges of the holes will be distorted if entry and backup materials are not used during drilling. Aluminum or aluminum-clad materials entry and backup materials are not recommended for any PTFE materials. Aluminum burrs have a tendency to damage the soft PTFE during the machining process. The following feeds and speeds have been proven to work well in production environments and are recommended as a beginning point to develop specific process parameters. Drilling Parameters To drill clean holes that do not contain drill smear, close attention must be placed on the drill speed and rate the drill enters and exits the material. As stated above, polished carbide drill bits work best on PTFE. The following parameters are basic recommendations for drilling PTFE. All fabricators should determine the optimal parameters for their equipment and tooling. Remember: Use new, polished, carbide tooling to guarantee the highest hole quality. Chip Load: 0.001 0.003 (0.025 mm 0.076 mm) per revolution Surface Speed: 200-400 sfm (1.0 2.0 m/s) Retract Rate: 400-600 IPM (169-254 mm/s) Tool Type: Polished Carbide Tool Life: 12-15 inches of dielectric (i.e. for 0.030, approximately 400-500 hits) depending on hole quality required.

Baseline Drilling Parameters Hole Diameter Inches (mm) Surface Speed SFM (mm/s) Spindle Speed (min) (RPM) Feed Rate Inches/min (mm/s) Chip Load Inches/rev (mm/rev).020 (.50) 200 38,197 38.2 (16.2).001.030 (.75) 200 25,464 25.5 (10.8).001.040 (1.0) 200 19,098 19.1 (8.1).001.060 (1.5) 200 12,732 19.1 (8.1).0015 Hole Cleaning Deburring: Use proper entry and exit materials to minimize burr formation. Hard phenolic entry and exit materials are recommended for PTFE laminates. Aluminum or aluminum-clad materials can be used but bird nesting must be eliminated or the dielectric will be damaged. The aluminum burrs have a tendency to damage the soft PTFE during drilling. If copper burrs are observed after drilling, scrubbing with minimal force should be used to prevent deformations. Use a highpressure wash to remove debris from holes. Desmear of Through Hole For situations where FR4 or similar prepreg (i.e., N4000-6, -13, or N6000-21) is used in a hybrid PCB format, chemical desmear can be used to desmear the non-ptfe layers. Use a recipe similar to the one shown below: Typical Solvent Conditioner Type Temp Time Butyl Carbitol @ 50 wt% 130 F ± 5 (54 C ± 2.8) 3-7 min. Typical Oxidizer Parameters Alkaline Permanganate 175 F ± 5 (79 C ± 2.8) 8-15 min. Plasma For hybrid packages with thermoset bond plies, plasma desmear should be used before Sodium etch (see next section) to get maximum adhesion of plating. If plasma is used for FR4 desmear and then for PTFE surface activation, the FR4 must be desmeared prior to treating the PTFE. Desmear is not possible on PCBs using pure PTFE and thermoplastic (i.e., FV6700 or FEP) bond-ply applications. Plasma Process The process below is a good starting point for FR4 and some other thermoset resin systems in a hybrid format. Cycle A: Step 1 Step 2 O 2 50%; He 50%; power of 4300 watts RF and 250 psi for 10 Minutes He 100%; power of 2575 watts; 250 psi for 15 minutes; final temperature, 175 F (79 C). Cycle B: Step 1 O 2 90%; N 2 10%; with final temperature of 135 F (57 C) Step 2 CF 4 10-15%, O 2 balance; final temperature is 230 F (110 C) Step 3 O 2 100%; One half the power used in Step 1 Cycle C: Step 1 O 2 50%; He 50%; power of 4300 watts RF; 250 psi for 10 Minutes

Step 2 He 100%; power of 2575 watts; 250 psi for 15 minutes; final temperature, 175 F (79 C). PTFE THROUGH-HOLE PREPARATION: Plasma: Plasma processes typically used to desmear epoxy-based boards, (O 2 / CF 4 or O 2 / NF 3 ) appear to have limited effectiveness when treating PTFE surfaces. However, other gasses such as NH 3 or (70% H 2 / 30% N 2 ) blends have been found to yield very good results with conventional production plasma equipment. The process conditions outlined below have been found to increase the ability to plate as well the ability to bond as those obtained by sodium etching. All loose debris in the holes should be removed prior to treatment. Cycle 1: Step 1 NH 3 or (70% H 2 / 30% N 2 ) 100 mtorr Pump-down, 250 mtorr operating, power of 4000 watts; frequency of 40 khz; voltage of 500-600V; cycle time of 10-30 minutes Contact your local Nelco representative for additional information. Park/Nelco materials should not need any baking prior to plasma. (Ceramic loaded PTFE materials from other vendors do require a pre-bake of at least one hour). Plasma treated holes are more delicate than sodium etched holes. Panels should not be exposed to any pressure wash or scrubbing process after plasma treatment prior to metallization. Sodium-Complex Etch: Use the Sodium Etch process as an alternative to the plasma process (above). This etchant is actually Sodium Napthalate complex in a glycol solution. Several commercial Sodium etchants are available in the market and are commonly used. Contact your local Nelco representative for additional information. Metallization: Conventional plating may be used to plate PTFE. Electroless copper as well as the palladium catalyst direct plating process such as Shipley s Crimson process, work well on PTFE substrates after hole prep. All treated PTFE should be processed within 24 hours. If not, retreat the holes prior to metalization. Once the electroless copper or direct plating has been used, standard electrolytic copper can be used. Remember, the secret to good plated through holes on PTFE substrates is a strong ductile cooper. The electrolytic copper should have a tensile strength of at least 30,000 psi and copper elongation of at least 15%. Panels are often flash electroplated 0.0001-0.0003 inch (2.5-7.6 µm) after electroless copper plating to reduce the risk of voiding holes while preparing surfaces for photo resist. Soldermask PTFE and ceramic filled surfaces do not require pre-treatment or conditioning prior to solder-mask application. Baking is desirable to drive out moisture prior to solder-mask treatment. Reflow/HASL Bake prior to re-flow or hot air solder leveling. Imaging The dimensional stability of Neltec s PTFE material is excellent. The dimensional change should be <0.5 mils/inch (0.005 mm/cm), but does depend on the prepreg, construction, and process.

Developing/Etching/Stripping Due the low modulus of the PTFE materials, frames and leaders may be required when processing thin laminates through some conveyorized equipment. Standard etchants can be used. Routing Once circuits have been drilled and plated, the circuits must be removed from the master panel. Routing, steel rule die cutting, waterjet cutting, and laser cutting can be used depending on required edge quality and cutting tolerances. In the case of routing, standard carbide (helical two flute or four flute) routers are recommended. Copper foil should be etched away from the routed edge to prevent burring. Tool life is approximately 2 to 5 feet of linear travel, depending on the specifications for edge quality or edge plating. For edge plating, follow the hole plating recommendations above. All fabricators should determine the optimal parameters for their equipment and tooling. Remember: Use new, polished, carbide tooling to guarantee the highest edge quality. Typical routing parameters for stack heights of 0.250 (6.35 mm): Tool size: Feed rate: Speed: 0.093 (2.36 mm) 60 IPM 24k RPM The above processing guides are recommendations only and intended for general review. Process adjustments may be required to achieve optimum results.

Park/Nelco reserves the rights to make changes without further notice to any products herein to improve reliability, function or design. Park/Nelco does not assume any reliability arising out of the application or use of any product described herein; neither does it convey any license under its patent rights nor the rights of others. This disclaimer of warranty is in lieu of all warranties whether expressed, implied or statutory, including implied warranties of merchantability or fitness for a particular purpose. Park/Nelco is an Equal Opportunity / Affirmative Action Employer.