Hisada et al.: FEM Analysis on Warpage and Stress at the Micro Joint (1/6) [Technical Paper] FEM Analysis on Warpage and Stress at the Micro Joint of Multiple Chip Stacking Takashi Hisada*, Yasuharu Yamada*, Kazushige Toriyama**, and Toyohiro Aoki** *Integrated Supply Chain Japan, IBM Tokyo Laboratory, IBM Japan, Ltd., NANOBIC, 7-7, Shinkawasaki, Saiwai-ku, Kawasaki-shi, Kanagawa 212-32, Japan **IBM Research - Tokyo, IBM Tokyo Laboratory, IBM Japan, Ltd., NANOBIC, 7-7, Shinkawasaki, Saiwai-ku, Kawasaki-shi, Kanagawa 212-32, Japan (Received July 31, 13; accepted September, 13) Abstract Flip chip plastic ball grid array (FCPBGA) utilizing an interposer for multiple chip stacks, so called 2.D or 3D package, is gaining prominence in order to achieve the next generation high performance computing. The multi-tier stacking of Si chip, Si interposer and organic substrate induces complicated warpage behavior and stress at the micro joints during the joining process. The authors studied warpage behavior and thermo-mechanical stress of multiple chip stacks on Si interposer package with different thickness of top chip, different thickness of Si interposer, different middle chip stacks and different metallurgy of micro joints after joining of stacked chips on the interposer using finite element method (FEM). Thicker stacked Si chips and thicker Si interposer showed higher von Mises stress at chip-to-interposer joint. Comparing SnAg joint and CuSn joint, CuSn joint always shows higher stress than SnAg joint because of its higher elastic modulus. Keywords: 3D-IC, Micro Joint, Stacked Chips, Interposer, FEM Analysis 1. Introduction Integration of functionalities of semiconductor devices is becoming more and more important as the demand for fully utilizing the high performance of advanced semiconductor devices is increasing. One approach is the integration onto one chip which is called system-on-chip (SoC). SoC has a challenge in manufacturing yield due to its large chip size when large amount of memory is integrated onto one chip. Another approach of integration is 2.D or 3D chip stacking using through-silicon-vias (TSV) technology. Typical configuration of a 3D package is multiple memory chips, a logic chip, a Si interposer and an organic substrate stacked from the top. Wiring to the top memory chip comes from the substrate via micro joints and TSVs of both logic and memory chips.[1, 2] Common configuration for 2.D package is multiple chips joined on an interposer side by side, and memory chips which can be stacked on the interposer like a 3D package. Well-known technical challenges of multiple chip stacks are the warpage and the stress at the micro joints in the chip joining process. There are several prior works reporting the effects of interposer material, interposer thickness, chip thickness, and joining sequence of chip and interposer.[3 6] The authors studied the warpage behavior and the thermo-mechanical stress at the micro joints with different thickness of top chip, different middle chip stacks and different metallurgy of micro joints after joining of stacked chips on the interposer FEM. In this work, the interposer is assumed to be joined on the organic substrate first, then the stacked multiple chips are joined on the interposer. 2. FEM Models 2.1 Basic assumptions Figure 1 illustrates the schematic package configuration for this analysis. The package consists of an organic substrate, a Si interposer and stacked chips from bottom to top. The top chip of the stacked chips does not have TSVs, and the middle chips and the Si interposer have TSVs to electrically connect the stacked chip from the top to the organic substrate. The middle chip is assumed to have polyimide layers on both side of the chip. The interposer is assumed to have a re-distribution layer (RDL) on the top side and a polyimide layer on the bottom side. Copyright The Japan Institute of Electronics Packaging 1
Transactions of The Japan Institute of Electronics Packaging Vol. 6, No. 1, 13 Table 1 shows the features of the package configuration. We evaluated five different top chip thicknesses in this analysis. Middle chip thickness is fixed to μm, and the number of stack of middle chip is set as a variable. Bump pitch and TSV pitch is μm. The layouts of bumps and TSVs exactly match, so the micro joints between chips are located on TSVs. The bump is -μm-diameter Cu pillar. We assume two different metallurgies for chip joining in this analysis, one is SnAg solder and another is CuSn intermetallic (IMC). Chip and interposer joining process is assumed as follows. 1. Interposer is joined on the organic substrate. 2. Underfill resin is applied between the interposer and the organic substrate. 3. Middle chip(s) and top chip are stacked and joined. 4. Stacked middle chip(s) and top chip are joined on the interposer which was pre-stacked on the organic substrate. The FEM analysis is performed to simulate the last step of the joining process in the above. 2.2 FEM model details The FEM models were created as quarter models as shown in Fig. 2. Zero degree of freedom (ZDOF) point was set at the center of the top die on the bottom side. Homogenized material properties of Si and Cu TSV were obtained using ANSYS Multiscale. Sim and applied to the Si interposer and the middle chip. In case of the middle chip, thirty six (6 6) corner TSVs are precisely modeled instead of using homogenized material properties. Table 2 shows the material properties used in this analysis. Homogenized material properties were obtained for RDL, underfill and organic substrate as well. Material properties of CuSn IMC are referred from the prior work.[6] Table 3 shows the model matrix in this analysis. One middle chip stack, two middle chip stacks and three middle chip stacks are denoted by 1, 2 and 3 respectively. Organic substrate Underill resin Si interposer Stacked chips Fig. 1 Package configuration. Table 1 Features of chip and interposer. Chip size (top/middle) 7. mm 7. mm Interposer size 13.3 mm 13.3 mm Chip thickness (top) µm, µm, µm, 4 µm, 72 µm Chip thickness (middle) µm Polyimide thickness (middle chip, interposer) µm Interposer thickness µm, µm, µm, µm RDL thickness (interposer) µm TSV pitch (middle) µm TSV pitch (interposer) µm Bump pitch (top/middle) µm Bump diameter (top/middle) µm Bump height µm Joint height µm Package size 4 mm 4 mm Thickness of base organic substrate 76 µm (4 µm core) Top chip Middle chip 1 Middle Si interposer Middle chip chip 2 3 Underfill resin Organic substrate Fig. 2 Bird s-eye view and cross-sectional view of FEM model with 3x middle chip stacks. Table 2 Material properties used in the analysis. Material Elastic modulus (GPa) Poisson s ratio CTE (ppm/ C) Si 16.22 3.2 RDL *).24 17 Cu 117.32 18 SnAg Solder 27.3 2 CuSn IMC[6] 1.3 16 Underfill resin 9..3 2 Build-up layer **) 17.34 27 Core layer ***) 2.33 1 *) Homogenized properties with Cu. **) Homogenized properties with Cu. ***) Homogenized properties with Cu and glass fiber. 2
Hisada et al.: FEM Analysis on Warpage and Stress at the Micro Joint (3/6) Table 3 Model matrix (n=1: -µm-thick interposer, n=2: -µm-thick interposer, n=3: -µm-thick interposer and n=4: -µm-thick interposer). Model type Top chip THK (µm) Middle chip stack With regard to joint metallurgy, simple assumption was set to have SnAg solder or CuSn IMC at all chip-to-chip and chip-to-interposer joining. Four different interposer thicknesses ( μm, μm, μm and μm) are identified by the index n. 3. Analysis Results and Discussions Joint metallurgy An 1 SnAg Bn 1 SnAg Cn 1 SnAg Dn 4 1 SnAg En 72 1 SnAg Fn 1 CuSn Gn 2 SnAg Hn 2 CuSn In 3 SnAg Jn 3 CuSn Thermo-mechanical analysis was performed using ANSYS Mechanical Ver. 14. The reference temperature was set at 18 C considering undercooling effect based on the results of preliminary experiments with FCPBGA, and cooling rate was set to 2 C/s. Z-direction displacement at top chip corner in the direction from the top chip to the organic substrate and von Mises stress in volume average at chip-to-chip and chip-to-interposer joints were analyzed at 2 C. Figure 3 shows the contour of von Mises stress of model I1 in the cross section of middle chip 1, 2, and 3 at the corner. As fracture of solder joint of chip-to-chip and chip-tointerposer is of interest during joining process, von Mises stress at the solder joints is examined in the below. 3.1 Effect of top chip thickness Figure 4 shows Z-direction displacement at the top chip corner and von Mises stress at the chip corner joint with model A1, B1, C1, D1 and E1 which are varying the top chip thickness. When the pre-stacked chips are attached on the Si interposer which is already joined on the organic substrate, it is thought that the mismatch of coefficient of thermal expansion (CTE) between the organic substrate and the Si chips induces warpage. As the top chip thickness increases, Z-direction displacement at the top chip Top chip Middle chip 1 Cu pillar bump Solder joint Cu land Middle chip 2 TSV Middle chip 3 Si interposer + Fig. 3 Contour of von Mises stress at Cu pillar bump, solder joint, Cu land and TSV (model I1). 4 3 2 4. 1 1.. 4 6 7 8 Fig. 4 Z-direction displacement at the top chip corner and von Mises stress at the chip corner joint with variable top chip thickness with -µm-thick interposer (Model A1, B1, C1, D1 and E1). corner decreases because of higher stiffness of thick top chip. Accordingly von Mises stress at both top-chip-to-middle-chip joint and middle-chip-to-interposer joint increases. In the three-tier Si stacks (top chip, middle chip and interposer), extremely thick top chip compared to the middle chip and the interposer induces higher stress, and this brings a concern of joint fracture at the joining process. Comparison of Fig. 4,, 6 and 7 shows the effect of interposer thickness. As the interposer thickness increases, the displacement at the top chip corner decreases slightly. There are clear changes of von Mises stress at the middle-chip-to-interposer joint. It drastically increases from -μm-thick interposer to -μm-thick interposer and -μm-thick interposer. Effect of CTE mismatch between the organic substrate and the Si interposer appears more clearly with thicker interposer. As to von Mises stress at the top chip-to-middle chip joint, the average stress slightly decreases as the interposer thickness increases. Minimum values of von Mises 3. 2. 3
Transactions of The Japan Institute of Electronics Packaging Vol. 6, No. 1, 13 stress are observed around -μm-thick top chip to -μm-thick top chip. It is considered appropriate that the minimum von Mises stress appears around the combination of same thickness of top chip and interposer. 4 3 2 1 V.M. stress at mid-i/p joint 4. 4 6 7 8 Fig. Z-direction displacement at top chip corner and von Mises stress at chip corner joint with variable top chip thickness with -µm-thick interposer (Model A2, B2, C2, D2 and E2). 4 3 2 3. 2. 1.. 4. 1 1.. 4 6 7 8 Fig. 6 Z-direction displacement at top chip corner and von Mises stress at chip corner joint with variable top chip thickness with -µm-thick interposer (Model A3, B3, C3, D3 and E3). 4 3 2 V.M. stress at mid-i/p joint 3. 2. 4. 1 1.. 4 6 7 8 Fig. 7 Z-direction displacement at top chip corner and von Mises stress at chip corner joint with variable top chip thickness with -µm-thick interposer (Model A4, B4, C4, D4 and E4). 3. 2. The optimum combination is -μm-thick top chip and -μm-thick interposer as both von Mises stress at top chip-to-middle chip joint and the von Mises stress at middle chip-to-interposer are the lowest level among the evaluated matrices. 3.2 Effect of middle chip stack and joint metallurgy Analyses of model Bn, Fn, Gn, Hn, In and Jn indicate the effects of middle chip stack and joint metallurgy. Comparisons of Bn against Fn, Gn against Hn and In against Jn give the effect of joint metallurgy. Comparisons among Bn, Gn and In, and among Fn, Hn and Jn give the effect of the stack of middle chip. Figure 8, 9, and 11 show Z-direction displacement at top chip corner and von Mises stress at top-chip-to-middle chip joint and middle-chip-to-interposer joint with -μm-thick interposer, -μm-thick interposer, -μm-thick interposer and -μm-thick interposer respectively. Z-direction displacement at the top chip corner 3 (SnAg joint) 2 (CuSn joint) 1 (SnAg) (SnAg) 8. 7. 6. Fig. 8 Z-direction displacement at top chip corner and von stack and different solder joint metallurgy with -µm-thick interposer (Model B1, F1, G1, H1, I1 and J1). 3 (SnAg joint) 2 (CuSn joint) 1 (SnAg) (SnAg) 8. 7. 6. Fig. 9 Z-direction displacement at top chip corner and von stack and different solder joint metallurgy with -µm-thick interposer (Model B2, F2, G2, H2, I2 and J2). 4
Hisada et al.: FEM Analysis on Warpage and Stress at the Micro Joint (/6) decreases as the number of middle chip stack increases. This is considered as a result of higher stiffness of the stacked chips. As to Z-direction displacement, two plotted lines with SnAg and CuSn exactly match with -μm-thick interposer and -μm-thick interposer. In the case of -μm-thick interposer and -μm-thick interposer, the displacement with CuSn is slightly smaller than that with SnAg. However, the difference between SnAg and CuSn is less than 1 μm in all cases. Joint metallurgy does not make a big change in displacement. On the other hand, von Mises stress with CuSn is clearly higher than that with SnAg. Higher elastic modulus of CuSn induces higher von Mises stress even though Z-direction displacement is almost same between SnAg joint and CuSn joint. Comparing 1x, 2x and 3x middle chip stacks, von Mises stress at middle-chip-to-interposer increases as number of middle chip stack increases. The change is more drastic with CuSn joint. In contrast, von 3 8. 7. 2 6. (SnAg joint) 1 (SnAg) Fig. Z-direction displacement at top chip corner and von stack and different solder joint metallurgy with -µm-thick interposer (Model B3, F3, G3, H3, I3 and J3). (SnAg) (CuSn joint) 3 2 (SnAg joint) (CuSn joint) 1 (SnAg) (SnAg) 8. 7. 6. Fig. 11 Z-direction displacement at top chip corner and von stack and different solder joint metallurgy with -µm-thick interposer (Model B4, F4, G4, H4, I4 and J4). Mises stress at top-chip-to-middle-chip joint slightly decreases or stays almost the same. This implies that the influence from the organic substrate decreases at the upper joint when the number of middle chip stack increases, and also implies that the influence of stacked Si chip volume increases at the middle-chip-to-interposer joint. Effect of interposer thickness is also significant. Von Mises stress at the middle-chip-to-interposer with 3x middle chip/-μm-thick interposer/cusn joint (Model J4) is approximately 2.9 times higher than that with 3x middle chip/-μm-thick interposer/cusn joint (Model J1). Figure 12 and 13 show von Mises stress of 3x middle chip stacks at each chip joint interface with SnAg joint and CuSn joint respectively. In both joint metallurgy cases, the middle-chip-to-interposer joint shows the highest stress as compared to the upper joints. As the interposer thickness increases, von Mises stress increases especially at the middle-chip-to-interposer joint. Significant effect of joint metallurgy is observed at the middle-chip-to-interposer joint, but the difference is less significant at other joint interfaces comparing Fig. 12 and 13. 8. 7. 6. I/P = µm I/P = µm I/P = µm I/P = µm Top-M1 M1-M2 M2-M3 M3-I/P Joint interface Fig. 12 Von Mises stress at variable joining interface of 3x middle chip stacks with SnAg joint (Model I1, I2, I3 and I4). 9. 8. 7. 6. I/P = µm I/P = µm I/P = µm I/P = µm Top-M1 M1-M2 M2-M3 M3-I/P Joint interface Fig. 13 Von Mises stress at variable joining interface of 3x middle chip stacks with CuSn joint (Model J1, J2, J3 and J4).
Transactions of The Japan Institute of Electronics Packaging Vol. 6, No. 1, 13 4. Summary The authors studied the warpage behavior and thermomechanical stress of multiple chip stacks on Si interposer package after joining of stacked chips to the interposer. FEM analysis was performed with different thickness of top chip, different middle chip stack, different thickness of Si interposer and different metallurgy of micro joints. The findings are summarized as follows. 1. As the top chip thickness increases, Z-direction displacement at the top chip corner decreases. Accordingly von Mises stress at the top-chip-to-middle-chip and the middle-chip-to-si-interposer increases. Among the evaluated matrices, the combination of -μm-thick top chip/-μm-thick middle chip/-μm-thick interposer is the optimum to have the lower von Mises stress at both middlechip-to-interposer and top-chip-to-middle-chip joints. 2. CuSn joints always have higher von Mises stress than SnAg joints because of its high elastic modulus. 3. As the number of middle chip stack increases, von Mises stress at the middle-chip-to-interposer increases. 4. As the interposer thickness increases, the displacement at top chip corner decreases, but von Mises stress increases especially at the middle-chip-tointerposer joint.. Most critical joint point in joining process is the middle-chip-to-interposer interface. Si volume of the stacked chips and the interposer influences von Mises stress at the most critical joint. References [1] J. U. Knickerbocker et al., Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection, IBM J. Res. Dev., Vol. 49, No. 4/, pp. 72 73, Jul/Sep.. [2] J. U. Knickerbocker et al., 3-D silicon integration, Proceedings of the 8 Electronic Components and Technology Conference, pp. 38 43, 8. [3] A. Horibe et al., Effect of Underfill Properties on Thermomechanical Stress in Fine Pitch 3D-IC Package, Proceedings of ICEP-IAAC 12, pp. 11 16, 12. [4] T. Hisada et al., Study of Warpage and Mechanical Stress of 2.D Package Interposers during Chip and Interposer Mount Process, Proceedings of the 4th International Symposium on Microelectronics, pp. 967 974, 12. [] T. Hisada et al., FEM Analysis on Mechanical Stress of 2.D Package Interposers, Transactions of The Japan Institute of Electronics Packaging, Vol., November 1, pp. 7 114, 12. [6] S. Kohara et al., Thermal Stress and Die-Warpage Analyses of 3D Die Stacks on Organic Substrates, Proceedings of IEEE CPMT Symposium Japan 12, Dec. 12. Takashi Hisada received the B.S. degree in physics from Osaka University, Osaka, Japan, in 1992. He joined IBM Japan after graduation and has been involved in packaging development for logic and RF devices. He is currently the manager of package and test engineering department. He is a member of JIEP and Smart Processing Society for Materials, Environment & Energy. Yasuharu Yamada received the B.S. degree in electronics and information technology from Ritsumeikan University. He joined IBM Japan in 1984 and is currently the engineer for thermo-mechanical simulation of semiconductor packaging. His background includes mechanical system, Printed Circuit Board and cooling device design for computer equipment. He is a member of package thermal characteristics task force in Japan Electronics and Information Technology Industry Association. Kazushige Toriyama received the B.S. degree in mechanical engineering from Doshisha University. He joined IBM Japan after graduation and has been involved in various projects for the advanced packaging development. He is currently a staff of IBM research Tokyo, and works on the future semiconductor packaging research such as 3DIC. Toyohiro Aoki received the B.S. and M.S. degrees in material physics from Osaka University, Osaka, Japan, in 1998 and respectively. He joined IBM Japan after graduation and has been involved in various projects for packaging development including chip package interaction. He is currently a member of IBM research Tokyo, and works on 3D packaging. 6