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Development of Low Temperature Bonding Using In-Based Solders Won Kyoung Choi, Daquan Yu, Chengkuo Lee,, Liling Yan, Aibin Yu, Seung Wook Yoon and John H Lau Moon Gi Cho, Yoon Hwan Jo, and Hyuck Mo Lee. Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), Science Park II, Singapore 7685. Electrical and Computer Engineering, National University of Singapore. Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Korea choiwk@ime.a-star.edu.sg, Tel: 65-67754, Fax: 65-67745747 Abstract In-based solders were chosen for the low temperature bonding at lower than 8 o C. Three kinds of bonding types on //Ti/SiO /Si dies, which were Sn/In and /In for Type, /In and /Sn for Type, and InSn alloy and InSn alloy for Type, were studied expecting that the whole Insolder layer is converted to the mixed intermetallic compound (IMC) phases of In- and In- IMCs after bonding below 8 o C and annealing at ~ o C. The IMC in the joints were characterized in terms of the microstructure observations and the compositional analysis with Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Spectroscopy (EDX), the phase identification with X-ray Diffraction (XRD) and the re-melting temperature with Differential Scanning Calorimetry (DSC). The phase equilibriums of the joints were examined by thermodynamic calculations to understand the re-melting behavior. As a result, complete bonding consisted of only high melting temperature IMCs, In 9, In, η- 6 Sn 5, and In, was successfully made at o C followed by annealing at o C in Type, and at 6 o C with annealing for hrs or at 8 o C without annealing for Type, which was confirmed by DSC measurements and explained through thermodynamic calculations. Introduction Due to strong demands for multi-functional and high performance systems in various applications, a vertical integration technology has been getting more interesting [- ]. In the many new applications such as Bio, MEMS, Optical, RF devices, the vertical integration requires a low processing temperature below o C to bond these devices without degrading their performance. The current method uses higher temperature around higher than o C for bonding and interconnecting the different devices or wafers in the vertical fashion [-5]. A high bonding temperature degrades the performance and sensitivity of the Bio, MEMS, Optical and RF devices. Therefore, a low temperature bonding at less than o C is a must for vertically integrating the different systems such as multifunctional devices into a System in Package (SiP). To develop the low temperature bonding, Indium and Indium base alloy solders have been favored due to their low melting temperature which is lower than 56 o C [6]. In addition, the interdiffusion between In and under bump metallurgy is so fast that the interfacial reaction and the intermetallic compound formation are expected to happen in a short reflow time. Moreover, thin In-based solder bump can be completely transformed to only the intermetallic compound (IMC) which has a high melting temperature. Then the joint is consisted of IMCs and withstands during further high temperature post-processing for assembly. Recently, several studies with In-based solder bumps, such as In-, In-, and In-Ni, have been reported for the D stacking applications [7-9]. However, the detailed microstructure observation and the phase identification about the IMCs formed at the joints have been rarely studied to understand the joint characteristics, yet. Previously, the low temperature bonding using Sn/In composite solder layer on was studied at the bonding temperature of 8 o C. Since the Sn layer was on the top In, further reduction of the bonding temperature below 8 o C was not available []. In this study, In and In-Sn alloy layers were chosen for the low melting temperature solder with an aim at bonding below 8 o C, and / layers were used for the UBM metallurgy expecting the formation of mixed In- and In- IMC phases at the joint after bonding. The IMC phases and their melting temperatures could be checked in the phase diagrams in Figure. The changes in the microstructure and the phases in the joint were examined as a function of bonding temperature, time and annealing process. The IMCs at the joints were investigated in terms of phase identification and their re-melting behavior. The thermodynamic calculation was employed in this study to understand the phase equilibrium of the joint according to the processing parameters. Figure Phase Diagrams of (a) -In and (b) -In Experimental Procedure Figure shows schematic designs of bonding pairs on //Ti/SiO /Si for this study. Type is composed of /thin Sn/In and /In on /. Type is composed of /In/Su and /Sn on /. For Type, two dies of 978--444--9/8/$5. 8 IEEE 94 8 Electronic Components and Technology Conference
/InSn alloy are bonded together. The / metallization was done with sputtering and /solder layers (In, InSn and Sn) were deposited in an e-beam evaporation chamber..µm layers were purposely deposited to protect the or solder surfaces from getting oxidized. Table I lists the details of the sequential metal layer thickness and reveals the solder composition after deposition measured with Energy Dispersive X-ray Spectrometry (EDX). 8 at% and 4 at% of Sn are measured in Type and Type respectively and considerable amount of was detected in Type, which means that atoms already diffused into In due to the fast interdiffusion between In and even at room temperature. The wafers were diced into x mm and x mm dies for bonding. Si/SiO /Ti Si/SiO /Ti Si/SiO /Ti In In Sn InSn In Sn InSn Si/SiO /Ti Si/SiO /Ti Si/SiO /Ti Type Type Type Figure Schematic Designs of Each Bonding Pairs Table I List of Layer Structure and Solder Composition Thickness Composition (EDX) Type (µm) (at%) /In/Sn/ /Sn/In//.69/7.8/6.9/8.64/././.7/./.69 /In//.//./ /In//.//./ /Sn//.//./ /(InSn)//.//./ /(InSn)//.//./ /In/Sn/.67/59.4/4.74/4.6 Dies in each type were bonded using flip chip bonder (FC5, SussMicroTec). A rapid ramping rate of ~5 o C/sec was applied to avoid the additional interaction between solder and in the joints. The peak temperature was varied from o C to 8 o C and the duration time at the peak temperature was min and 5 min. High bonding pressure (~6MPa) was employed to make a tight contact between two dies with thin solder layer. The bonded samples were annealed at o C for 5hrs and o C for, 5 and hrs in a vacuum oven. To measure the sealing property with In-based solder on / for low temperature bonding, the 8 wafers consisted of 8 x 8 mm sized dies with seal ring were fabricated. The ring width was µm with /Sn/In/Sn// (./.5//.5/./ in µm) metallization. The patterning process was conducted using dry-film at room temperature to avoid any damage on the solder layer. In the cap wafer, cavity (6 x 6 mm ) with 5 um depth was formed using wet-etching process with KOH. Two wafers were bonded together at 8 o C for min. under MPa. in a controlled N atmosphere. The bonded wafers were diced into 8 x 8 mm dies and these dies were evaluated. The bonded samples were encapsulated by epoxy at room temperature and metallographically polished to a final finish using.5 µm alumina slurry. Scanning electron microscopy (SEM) and energy dispersive x-ray (EDX) analysis were employed to investigate the IMC morphology and qualitative elemental composition. To identify the crystal structure of IMCs formed at the interface, X-ray diffraction (XRD) analysis was performed on the two surfaces of the samples detached by shear tester. Thermal analysis of the IMCs was carried out with Differential Scanning Calorimetry (DSC) to measure the phase transformation temperature of solid to liquid. Table II Process Conditions at the Lowest Temperature having Void-Free Joint Microstructure Except For Type. Bonding Annealing Temp. Time Pressure Temp. Time ( o C) (min.) (MPa) ( o C) (hrs) Type 6 6 5 Type * 8 6 5 Type 6 5 ( * Void-free structure of Type could not be achieved below 8 o C) Results and Discussion Effects of Processing Conditions on Joint Microstructures The types were bonded at ~8 o C for min and 5 min. and annealed, subsequently. Figure exhibits the SEM micrographs of the joints in the cross sectional view of types after bonding at a chosen bonding condition in each type. In type, bonding at 6 o C provides a continuous contact without creating any voids at the interface. Even at o C, the joint was successfully formed, although due to the lack of the bonding temperature and time, some voids were observed. But, it was noticed that the thin Sn layer on top of In may lower the solidus temperature by alloy together with In, and enables the In layer to melt at a low temperature below 56 o C under a high pressure of 6 MPa. In the solder layer of the joint in Fig. (a), there are several layers consisting of alternative dark and bright layers. The bright layer was found to be a (In,Sn) phase by EDX and XRD analysis. While there are two kinds of compositions in dark layers, which are 55(In,Sn) close to layer and 78(In,) in the center. 95 8 Electronic Components and Technology Conference
(a) (b) (c) Figure SEM Micrographs of the joints of types using the condition described in Table II. : (a) Type, (b) Type and (c) Type 55(In,Sn) 78(In, ) (In,Sn) 7(In,Sn) 4In9Sn7 In 6~664~4(Sn,In) In (In,Sn) The effect of the bonding temperature on the joint structure was examined in Type. Figure 6(a) shows the joint microstructure of Type bonded at 4 o C and 6 o C for min. followed by annealing at o C for 5hrs. There is not much difference in the microstructure. The residual thickness and the layer composition seem to be similar, as well. However, the shear strength value dropped abruptly in the sample bonded at 6 o C as shown in Fig. 7. The IMC layers of the joint at 8 o C in Fig. 6(b) look more planar than those in joints at o C in Fig. 4(c) and at 4 o C in Fig. 6(a). In addition, it was found that the fracture in all joints happened along the In layer in the center in the joint. So, it is thought that the morphology change in the IMC layers with an increase in the bonding temperature may affect the shear strength value of the joints. (a) (b) (c) Figure 4 Magnified SEM Micrographs of Joint Microstructures of (a) Type, (b) Type, and (c) Type of which detailed process conditions are in Table II. min at 4 o C & 5hrs at o C 67(In,Sn) In min at 6 o C & 5hrs at o C In 67(In,Sn) Void-free bonding of Type was not successfully obtained even at 8 o C. Still some voids were observed as shown in Fig. (b). Moreover, the bonding strength was too weak to be carried for a long time. It tells that the peak temperature should be higher than 8 o C which is out of our targeting temperature. The interface microstructure of the Type reveals that the uniform bonding was made at as low as o C. It is attributed to the In-5at%Sn alloy which solidus temperature is o C and the liquidus temperature might be lower than pure In melting temperature (56 o C). The bright areas in Fig. 4(c) are corresponding to (In,Sn) phase and the dark area was detected as a 6~664~4(Sn,In) in at% which would be thought as a mixture of In 9 phase and the ternary η- 6 (In,Sn) 5 phase as reported in []. 6 4 (a) (b) Figure 6 SEM Microstructures of Type bonded (a) at 4 o C for min and (b) bonded at 6 o C followed by annealing at o C for 5 hrs Shear Strength [MPa] 6 4 8 6 4 4 6 Bonding Temperature [deg C] Figure 7 Shear strength Values of Joints in Type as a Function of Bonding Temperature Table III IMC Phases Identified with XRD Patterns Shear Strength [MPa] 8 6 4 Type Type Type Type IMC Phases In (*), In 9, In, In, η- 6 Sn 5 In 9, In, In, η- 6 Sn 5 In 9,, In, In, η- 6 Sn 5 Figure 5 Shear strength values of the joints in each type which were prepared using the process conditions listed in Table III Figure 5 shows the shear strength values of each Type using die shear tester (Dage 4 series). The measurement was conducted over 6 samples per each type. The strongest shear strength happens in Type which is not only due to the bonding microstructure, but due to thicker solder layer by twice than the other types. IMC Phase Formation and Re-melting Behavior The IMC phases formed at the joints were identified using XRD experiment. The bonded samples were detached to expose the bonding area to the X-ray incidence. Table III lists the IMC phases formed in each type. There were some unknown peaks in the XRD pattern of Type, which seem to correspond to In phase which does not appear in the equilibrium phase diagram. Simic and Marinkovic [] reported In phase existence and its unit cell structure for 96 8 Electronic Components and Technology Conference
the first time and Rita et. al [] reported the XRD peaks and confirmed it experimentally. Another noticeable finding is that both layers overand underneath the In layer migrated to the center of the In layer and formed a line of (In,Sn) containing almost at% Sn in Type. Since solubility in In is almost zero, atoms prefer to exist as the -In IMC for the thermodynamically stable state so that the -In IMC formation takes place quite quickly in bonding [4]. Therefore, (In,Sn) layer was created at the early stage of the bonding process and then separated from and gathered together in the middle of In layer. The spalling of In phase from Ni or layer were also observed before and affected mechanical reliability [8]. It seems that the wetting property between -In IMC and or Ni is not so good enough to stick to each other. Therefore, the week bonding strength could be related with formation and spalling of (In,Sn). On the other hand, in Type, the In layer did not move to the inside of the InSn layer. Instead, there is another layer, η- 6 (Sn,In) 5, between In and. Moreover, the amount of Sn in In was less than at% which is quite small comparing with the Sn of the (In,Sn) in In layer. The abundance of Sn in InSn alloy next to / layer could reach and react with preferably just passing through layer leaving In layer behind. As a result, the interface between InSn solder and is made up of the In phase layer contacting η- 6 (Sn,In) 5, which phases were wetted well with each other so that the spalling of In layer did not occur. Therefore, the Sn existence in In has an influence on the prevention of the spalling of the In layer on at room temperature. Table IV IMC Phase Changes in Joints According to Process Conditions Bonding temperature ( o C) Annealing condition, 4, 6 not annealed 8 not annealed, 4, 6 C for 5 hrs C for 5 hrs 6 C for hrs 8 C for 5 hrs Composition (at%) 55(In,Sn) 78(In,) 78(In,) 78(In,) 55(In,Sn) 78(In,) 655In 78(In,) 78(In,) 78(In,) The re-melting temperature of three types was measured using DSC by heating from 4 o C to 5 o C at a rate of 5 o C/min. Type generated a tiny peak around 9 o C, while type and type have re-melting temperature higher than o C. In Type, a big peak was found around 6 o C. In Type, there is a broad peak generated around 45 o C. It seems that the ternary phase of η- 6 (In,Sn) 5 melted around 45 o C, which should be checked with the phase diagram through the thermodynamic calculations. Optimizing Bonding Condition of Type for High Re- Melting Temperature The effects of the temperature and time on the joint composition in Type were investigated as a function of bonding and annealing conditions. Table IV lists the compositions of two above and below layers divided by (In,Sn) IMC in the joints. When the bonding temperature is in the range of ~6 o C, each layer has different composition, 55(In,Sn) in at% near layer and 78(In,) in at% in the center regardless of bonding time. However, at 8 o C, the composition was 78(In,) in all layers and no more change in the composition was observed after annealing at o C. Furthermore, the 55(In,Sn) layer was converted to higher -In composition of 655In not to 78(In,) layer after annealing at o C and o C for longer than 5 hrs. Figure 8 exhibits the phase changes as a function of temperature at the compositions of 55(In.5 Sn.5 ) and (In.5.5 ) which are corresponding to two kinds of IMCs in the joints. NP(*)..9.8.7.6.5.4... 5 4 5 4 5 6 7 TEMPERATURE_CELSIUS NP(*)..9.8.7.6.5.4. (a).. 4 4 4 5 5 5 4 45 5 55 6 TEMPERATURE_CELSIUS :T-7.5,NP(CUINSN_ETA) :T-7.5,NP(LIQUID) :T-7.5,NP(INSN_GAMMA) 4:T-7.5,NP(BIINPBSN_BEA) 5:T-7.5,NP(CUINSN) :T-7.5,NP(LIQUID) :T-7.5,NP(AUIN) :T-7.5,NP(CUIN_DELTA) 4:T-7.5,NP(FCC_A) (b) Figure 8 Phase changes as a function of temperature at (a) 55(In.5 Sn.5 ) and (b) 78(In.5.5 ) In Fig. 8(a), only a little fraction (~%) of liquid can be existed and transformed to solid phase around o C. This is in a good agreement with the DSC result. The tiny peak generated below o C in the DSC curve seems to be resulted from this transformation to liquid. Fig. 8(b) confirms that there are several kinds of IMCs, such as 7 In, In, and In at room temperature, which have a higher melting temperature than o C. The re-melting temperature of the 97 8 Electronic Components and Technology Conference
sample after bonding at 8 o C for min. was higher than 4 o C from the DSC measurement as shown in Fig. 9. This joint includes only 78(In,) layer in which the corresponding solidus temperature happens at (In.5.5 ) in Fig. 8(b). It clearly indicates that the joint is having only high temperature phases. Consequently, it is suggested that the bonding with Type structure should be performed at higher than 8 o C or bonding at lower than 6 o C followed by annealing for long time about hrs at o C in order to get the joint with only high temperature IMCs in In layer and / joints. with Type (4 MPa). The Helium leakage was measured as ~5x - atm cc/sec which is enough to pass MIL-STD-88E. Further study to examine the reliability of the low temperature bonding with modified type structure is being conducted on now. 4 5 Figure SEM micrograph of the joint bonded with /Sn/In/Sn on / pairs at 8 o C for min in a wafer level Table V Compositions of the solder joints (at%) In Sn Figure 9 DSC curve obtained from Type bonded at 8 o C for min Wafer Level Hermetic Sealing with Modified Type Structure of /Sn/In/Sn on / To examine sealing property with modified Type structure, the metallization of.µm/.5µmsn/µm In/.5µmSn for the sealing ring was deposited on.µm/µm/ti/sio /Si on 8 wafer. Here, the additional.5µm Sn was inserted between In and to prevent from In IMC movement to the inside of In layer. The seal width was um and the total die size was 8 x 8 mm. For the cap wafer, 6 x 6 mm sized cavity with 5 µm depth was fabricated with wet-etching process using KOH. Using two dies with cavity only on the cap wafer, the wafer to wafer bonding was performed at 8 o C in a wafer bonder (EVG) for min. applying 9kN (~MPa). Because of the restriction on applying the force in the equipment, only MPa could be employed in this case. Figure shows the crosssectional view of the solder joint of the samples prepared with wafer to wafer bonding at 8 o C for min under MPa. Uniform microstructure without any voids or cracks was observed. As expected, spalling of In was not observed. Much thicker Sn/In/Sn solder (6µm) and longer bonding time might make the In phase not to be observed clearly. η- 6 (Sn,In) 5 and (In,Sn) 9 phases were found as IMC phases by EDX analysis as listed in Table V. It indicates that the re-melting temperature should be higher than 4 o C. To investigate the quality of the /Sn/In/Sn-/ bonding, SAM was used. Figure exhibits the SAM image of the /Sn/In/Sn-/ bonding. There is no variation with the contrast or the brightness in the entire ring area, which means any disconnection in the solder joint was not generated and the die was sealed firmly. The shear strength was measure as.9 MPa of which value is much higher than that of joint Seal Ring 6. 6..67 6.4.9 4.7 59.47 5.8 5.6 4 6.5 5.5. 5 57.5 6. 6.65 8mm 8mm Figure SAM images of the die sealed with /Sn/In/Sn on / pairs at 8 o C for min in a wafer level Conclusions and Recommendations Low temperature bonding with a process temperature as low as o C with In-based solder layers on / has been developed. The re-melting temperature was higher than 4 o C confirmed by DSC experiment and thermodynamic calculation of the joint. Some important results and recommendations are summarized as following.. Joint with type structure of InSn alloy layer showed the strongest shear strength at the lowest bonding temperature ( o C). The bonding strength was as high as 4 MPa which was.5 times higher than that of Type bonded at 6 o C.. In Type with thin Sn/In solder on /, the uniform bonding was successfully achieved at 6 o C. However, 98 8 Electronic Components and Technology Conference
it was found that the liquid phase still exists and showed a peak around at o C in DSC curve. The shear strength was only 4 MPa.. It is recommended that the bonding should be performed at higher than 8 o C under 6 MPa for min. or bonding at lower than 6 o C under 6 MPa for min. followed by annealing for about hrs at o C, to make the joint with Type to have fully high temperature IMCs. The re-melting temperature of the joint bonded at 8 o C for min. under 6MPa was higher than 4 o C which was confirmed by DSC experiment and thermodynamic calculation. 4. The wafer level hermetic package with the modified Type structure of /Sn/In/Sn on / was successfully fabricated at 8 o C for min. under MPa. Helium leakage rate was as low as 5 x - atm cc/sec and the shear strength of individual chip was 7 MPa. 5. The wafer level approach for the hermetic package with Type is in process now and its results will be reported in the near future. Acknowledgments Chengkuo Lee, PI of IME Core Project 6-44, would like to thank the Institute of Microelectronics, Agency for Science, Technology and Research (A*STAR), Singapore, for supporting this research. References.. T. Mitsuhashi et al., Development of D-Packaging Process Technology for Stacked Memory Chips, Mater. Res. Soc. Symp. Proc. Vol. 97 (7), 97-Y-6.. K. Takahashi et al., rrent Status of Research and Development for Three-Dimensional Chip Stack Technology, Jpn J. Appl. Phys., Vol 4 (), pp. - 7 Part No 4B (), pp. -7.. A. Klumpp et al, Vertical System Integration by Using Inter-Chip Vias and Solid-Liquid Interdiffusion Bonding, Jpn J of Appl. Phys., Vol. 4, No. 7A (4), pp. L89 L8. 4. K.-E. Chen et al., Microstructure examination of copper wafer bonding, J. Electron. Mater., Vol., No. 4 (), pp.-5. 5. P. R. Morrow et al., Three-dimensional wafer stacking via - bonding integrated with 65-nm strained-si/low-k CMOS technology, IEEE Electron Device Letters, Vol. 7, No. 5 (6), pp. 5-7. 6. Y. M. Liu and T. H. Chuang, Interfacial Reactions between Liquid Indium and -Deposited Substrates, J. of Electron. Mater., Vol. 9, No. 4 (), pp. 45-4. 7. T. Fukushima, Self-Assembly Process for Chip-to-Wafer Three-Dimensional Integration, Proceedings of the 57th Electronic Components and Technology Conference, (7), pp. 87-84. 8. K. Sakuma et al., D Chip Stacking Technology with Low-Volume Lead-Free Interconnections, Proceedings of the 57th Electronic Components and Technology Conference, (7), pp 67-6. 9. S. Wakiyama et al., Novel Low-Temperature CoC Interconnection Technology for Multichip LSI (MCL), Proceedings of the 57th Electronic Components and Technology Conference, (7), pp. 6-65.. L. Yan et al., A Hermetic Package Bonded at Low Temperature with /In/Sn/ Joint, To be presented in the 58th Electronic Components and Technology Conference (8).. P.T. Vianco et al., Intermetallic compound layer formation between copper and hot-dipped In, 5In- 5Sn, Sn, and 6Sn-7Pb coatings, J. Electron. Mater., Vol., (994), pp. 58-594.. V. Simic and Z. Marinkovic, Room Temperature Interactions in Copper-Metal Thin Film Couples, J of the Less-Common Metals, Vol. 7 (98), pp. -4.. Rita Roy et al., Structural Characterization of the In Intermetallic Phase Produced by Interfacial Reactions in /In Bimetallic Films, Thin Solid Films, Vol. 9 (99), pp. 4-4. 4. M. M. Hou and T. W. Eaga, Low Temperature Transient Liquid Phase (LLTLP) Bonding for / and / Interconnections, J. of Electron. Pac., vol. 4, (99), pp. 44-447. 99 8 Electronic Components and Technology Conference