EM7644SU16AxP-70LFx 4Mx16 Pseudo Static RAM

Transcription

1 Document Title EM7644SU16AxP-70LFx 4M x 16 bit Pseudo SRAM Specification Revision History Revision No. History Date Remark Initial Draft Feb Preliminary Standby current(isb) updated from TBD to 150uA Oct Temperature option code is updated in the Memory function guide of the last page. => Extended is deleted, blank means wireless( ) Jul Power supply voltage changed from 2.6V3.3V to 2.6V3.6V Jul Emerging Memory & Logic Solutions Inc. 3F Korea Construction Financial Cooperative B/D, Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : Tel : Fax : / Homepage : The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1

2 4Mb x16 Pseudo Static RAM Specification EM7644SU16AxP-70LFx GENERAL DESCRIPTION The EM7644SU16AxP is 67,108,864 bits of Pseudo SRAM which uses DRAM type memory cells, but this device has refresh-free operation and extreme low power consumption technology. Furthermore the interface is compatible to a low power Asynchronous type SRAM. The EM7644SU16AxP is organized as 4,194,304 Words x 16 bit. FEATURES - Organization :4M x16 - EM7644SU16ALP support 8 page mode & DPD - Power Supply Voltage : V - EM7644SU16AMP support 8 page mode & Non-DPD - Separated I/O power(vccq) & Core power(vcc) - EM7644SU16ANP support 16 page mode & DPD - Three state outputs - EM7644SU16APP support 16 page mode & Non-DPD - Byte read/write control by UB# / LB# - EM7644SU16ARP support Non-page mode & DPD - Auto-TCSR for power saving - EM7644SU16ASP support Non-page mode & Non-DPD - Package type : 48-FPBGA 6.0x7.0 - Operating Temperature. Wireless : Industrial : PRODUCT FAMILY Power Dissipation Part Number Operating Temp. Power Supply Speed (t RC ) Standby (I SB, Max.) Operating I CC ( Max.) I CC1 ( f = 1MHz) I CC2 ( f = f max ) EM7644SU16AxP-70LF -30 to V to 3.6V 70ns 150uA 5mA 50mA EM7644SU16AxP-70LFI -40 to V to 3.6V 70ns 150uA 5mA 50mA FUNCTION BLOCK DIAGRAM ZZ# UB# LB# WE# OE# CONTROL LOGIC Self-Refresh CONTROL COLUMN SELECT A0A21 ADDRESS DECODER ROW SELECT Memory Array 4M X 16 DQ0 DQ15 Din/Dout BUFFER I/O CIRCUIT 2

3 PIN DESCRIPTION ( 48-FBGA-6.00x7.00 ) A LB# OE# A0 A1 A2 ZZ# B DQ8 UB# A3 A4 DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSSQ DQ11 A17 A7 DQ3 VCC E VCCQ DQ12 A21 A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 A20 TOP VIEW (Ball Down) Name Function Name Function Chip select input LB# Lower byte (DQ 07 ) OE# Output enable input UB# Upper byte (DQ 815 ) WE# Write enable input VCC Power supply ZZ# Low power control VCCQ I/O power supply DQ 0-15 Data in-out VSS(Q) Ground A 0-21 inputs NC No connection DNU Do not use Note: ZZ# pin is replaced to NC pin in EM7644SU16AMP, EM7644SU16APP, EM7644SU16ASP. 3

4 ABSOLUTE MAXIMUM RATINGS 1) Parameter Symbol Ratings Unit Voltage on Any Pin Relative to Vss V IN, V OUT -0.2 to V CCQ +0.3 V Voltage on Vcc supply relative to Vss V CC, V CCQ ) to 3.9 V Power Dissipation P D 1.0 W Storage Temperature T STG -65 to 150 o C Operating Temperature Wireless -30 to 85 o C T A Industrial -40 to 85 o C 1. Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Undershoot at power-off : -1.0V in case of pulse width < 20ns FUNCTIONAL DESCRIPTION ZZ# OE# WE# LB# UB# DQ 07 DQ 815 Mode Power H H X X X X High-Z High-Z Deselected Stand by X L X X X X High-Z High-Z Deselected Low Power Mode* 2) L H H H L X High-Z High-Z Output Disabled Active L H H H X L High-Z High-Z Output Disabled Active L H L H L H Data Out High-Z Lower Byte Read Active L H L H H L High-Z Data Out Upper Byte Read Active L H L H L L Data Out Data Out Word Read Active L H X L L H Data In High-Z Lower Byte Write Active L H X L H L High-Z Data In Upper Byte Write Active L H X L L L Data In Data In Word Write Active Note: 1. X means don t care. (Must be low or high state) 2. This Low Power mode is supported in EM7644SU16ALP, EM7644SU16ANP & EM7644SU16ARP. 4

5 RECOMMENDED DC OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit V CC V Supply voltage V CCQ V Ground V SS, V SSQ V Input high voltage V IH 0.8 * V CCQ - V CCQ ) V Input low voltage V IL ) * V CCQ V 1. Overshoot: VCC +1.0 V in case of pulse width < 20ns 2. Undershoot: -1.0 V in case of pulse width < 20ns 3. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE 1) (f =1MHz, T A =25 o C) Item Symbol Test Condition Min Max Unit Input capacitance C IN V IN =0V - 8 pf Input/Output capacitance C IO V IO =0V - 8 pf 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Parameter Symbol Test Conditions Min Typ Max Unit Input leakage current I LI V IN =V SS to V CCQ, V CC= V CCmax -1-1 ua Output leakage current I LO =V IH, ZZ#=V IH, OE#=V IH or WE#=V IL, V IO =V SS to V CCQ, V CC= V CCmax -1-1 ua Average operating current I CC1 Cycle time = 1us, I IO =0mA, 100% duty, <0.2V, ZZ#>V CCQ -0.2V, V IN <0.2V or V IN >V CCQ -0.2V ma I CC2 Cycle time = Min, I IO =0mA, 100% duty, =V IL, ZZ#=V IH, V IN =V IL or V IH ma Page access operating current I CCP tpc = Min,=V IL, ZZ#=V IH, I IO =0mA, Page add. cycling ma Output low voltage V OL I OL = 0.5mA, V CC= V CCmin *V CCQ V Output high voltage V OH I OH = -0.5mA, V CC= V CCmin 0.8*V CCQ - - V Standby current (CMOS) I SB (Typ. condition : V CC 25 o C),ZZ#>V CCQ -0.2V, Other inputs = 0 V CCQ (Max. condition : V CC 85 o C) ua 1. Maximum Icc specifications are tested with V CC = V CCmax. 5

6 AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.2V to V CCQ -0.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : V CCQ /2 Output Load (See right) : CL 1) = 30pF Dout CL 1) 1. Including scope and Jig capacitance AC CHARACTERISTICS Parameter List Symbol Speed Min Max Unit Read Cycle Time t RC 70 10k ns access time t AA - 70 ns Chip enable to data output t CO - 70 ns Output enable to valid output t OE - 25 ns UB#, LB# enable to data output t BA - 25 ns Read Chip enable to low-z output t LZ 10 - ns UB#, LB# enable to low-z output t BLZ 0 - ns Output enable to low-z output t OLZ 0 - ns Chip disable to high-z output t HZ 0 20 ns UB#, LB# disable to high-z output t BHZ 0 20 ns Output disable to high-z output t OHZ 0 20 ns Output hold from change t OH 5 - ns Write Cycle Time t WC 70 10k ns Chip enable to end of write t CW 60 - ns setup time t AS 0 - ns valid to end of write t AW 60 - ns UB#, LB# valid to end of write t BW 60 - ns Write Write pulse width t WP 50 - ns Write recovery time t WR 0 - ns Write to output high-z t WHZ 0 20 ns Data to write time overlap t DW 20 - ns Data hold from write time t DH 0 - ns End write to output low-z t OW 5 - ns Maximum cycle time *1) t MRC - 10k ns Page Page mode cycle time t PC *1) 25 - ns Page mode address access time t PAA *1) - 25 ns NOTES 1. These parameters are not supported in EM7644SU16ARP & EM7644SU16ASP. 6

7 TIMING DIAGRAMS READ CYCLE (1) ( controlled, =OE#=V IL, ZZ#=WE#=V IH, UB# or/and LB#=V IL ) t RC t OH t AA Data Out Previous Data Valid Data Valid READ CYCLE (2) (ZZ#=WE#=V IH ) t RC t AA t CO t OH LB#, UB# t BA t HZ t OE t BHZ OE# Data Out High-Z t OLZ Data Vaild t OHZ t BLZ t LZ NOTES (READ CYCLE) 1. t HZ, t BHZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. Do not Access device with cycle timing shorter than t RC for continuous periods > 10us. 7

8 PAGE READ CYCLE (1) (ZZ#=WE#=V IH, 8 Words access) (A21A3) t MRC (A2A0) t RC t AA t CO t PC t PC t PC t PC t OH LB#,UB# t BA t OE t HZ t BHZ OE# Data Out t OLZ High-Z Data Valid Data Valid Data Valid Data Valid Data Valid t BLZ t LZ t PAA t PAA t PAA t PAA t OHZ NOTES (READ CYCLE) 1. t HZ, t BHZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. Do not Access device with cycle timing shorter than t RC for continuous periods > 10us. 3. This page read cycle(8 page mode) is supported in EM7644SU16ALP & EM7644SU16AMP. 8

9 PAGE READ CYCLE (2) (ZZ#=WE#=V IH, 16 Words access) (A21A4) t MRC (A3A0) t RC t AA t CO t PC t PC t PC t PC t OH LB#,UB# t BA t OE t HZ t BHZ OE# Data Out t OLZ High-Z Data Valid Data Valid Data Valid Data Valid Data Valid t BLZ t LZ t PAA t PAA t PAA t PAA t OHZ NOTES (READ CYCLE) 1. t HZ, t BHZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. Do not Access device with cycle timing shorter than t RC for continuous periods > 10us. 3. This page read cycle(16 page mode) is supported in EM7644SU16ANP & EM7644SU16APP. 9

10 WRITE CYCLE (1) (WE# controlled, ZZ#=V IH ) t WC t AW t CW EM7644SU16AxP-70LFx LB#,UB# t BW WE# t WP t AS t DW t DH t WR Data In High-Z Data Valid t WHZ t OW Data Out Data Undefined WRITE CYCLE (2) ( controlled, ZZ#=V IH ) t WC t CW t WR t AS LB#,UB# t AW tbw WE# t WP t DW t DH Data In Data Valid Data Out High-Z WRITE CYCLE (3) (UB#/LB# controlled, ZZ#=V IH ) t WC t CW t WR LB#,UB# t AS t AW tbw WE# t WP t DW t DH Data In Data Valid Data Out High-Z 10

11 NOTES (WRITE CYCLE) 1. A write occurs during the overlap(t WP ) of low, low WE# and low UB# or LB#. A write begins at the last transition among low and low WE# with asserting UB# or LB# low for single byte operation or simultaneously asserting UB# and LB# low for word operation. A write ends at the earliest transition among high and high WE#. The t WP is measured from the beginning of write to the end of write. 2. t CW is measured from going low to end of write. 3. t AS is measured from the address valid to the beginning of write. 4. t WR is measured from the end of write to the address change. t WR applied in case a write ends as or WE# going high. 5. Do not access device with cycle timing shorter than t WC for continuous periods > 10us. LOW POWER MODES Deep Power Down Mode Entry/Exit t ZZCS t ZZP t CSZZ ZZ# t R Normal operation Deep Power Down Entry Deep Power Down Exit NOTES ( DEEP POWER DOWN ) 1. During Deep Power Down mode, all referesh related activity are disabled. 2. This DPD mode is supported in EM7644SU16ALP, EM7644SU16ANP & EM7644SU16ARP. Parameter Description Min. Max. Units t ZZCS ZZ# low to low 0 - ns t CSZZ high to ZZ# high 0 - ns t R Operation Recovery Time us t ZZP ZZ# pulse width 20 - ns Low Power Mode Characteristics Parameter Symbol Test Conditions Min Typ Max Unit Deep Power Down Current I ZZ ZZ# < 0.2V, Other inputs = 0 V CCQ (Max. condition : V CC 85 o C) ua 11

12 TIMING WAVEFORM OF POWER UP V CC (Min.) 200us V CC Power Up Mode Normal Operation ZZ# NOTE ( POWER UP ) 1. After Vcc reaches Vcc(Min.), wait 200us with high. Then you get into the normal operation. 2. ZZ# pin is replaced to NC pin in EM7644SU16AMP, EM7644SU16APP, EM7644SU16ASP. 12

13 PACKAGE DIMENSION Unit: millimeters 48 Ball Fine Pitch BGA (0.75mm ball pitch) Top View D Bottom View D D1 A1 index Mark A #A1 B C ee E D E E1 E E1/2 F G H Side View ed D/2 A2 A1 b Detail A A A3 D Min Typ Max A A A A b D E D E ee ed ccc A2+A Typ. A1 NOTES. ed ccc 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75x0.75) (typ.) 3. All tolerance are +/ unless otherwise specified. 4. Typ : Typical 5. ccc is coplanarity : 0.08(Max) 13

14 MEMORY FUNCTION GUIDE EMX XX XXX XX XXX -XXXX X EM7644SU16AxP-70LFx 13. Temperature 1. EMLSI Memory 12. Power 2. Device Type 11. Speed 3. Density 10. Package 4. Function 9. Option 5. Technology 8. Version 6. Operating Voltage 7. Organization 1. Memory Component 9. Option Blank No optional mode 2. Device Type J Non-RBC Low Power SRAM K RBC STRAM L page mode / DPD C CellularRAM M page mode / Non-DPD N page mode / DPD 3. Density P page mode / Non-DPD M R Non-page mode / DPD M S Non-page mode / Non-DPD M M 10. Package M Blank Wafer M S stsop1 T TSOP1 4. Function U TSOP Multiplexed async. P FPBGA Multiplexed sync. Z FPBGA Demultiplexed async. Y FPBGA Multiplexed sync. W FPBGA Demultiplexed sync. V FPBGA 5. Technology 11. Speed(@async.) S Single Transistor ns ns 6. Operating Voltage ns U V 3.6V ns P V 1.95V ns ns 7. Organization ns X8 bit ns X16 bit X32 bit 12. Power LL Low Low Power 8. Version LF Low Low Power(Pb-free & Green) Blank Mother die L Low Power A nd generation S Standard Power B rd generation C th generation 13. Temperature D th generation Blank Wireless ( ) I Industrial ( ) 14