ICEP-IAAC 2012 Proceedings

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1 Thin SiP and 3D ewlb (embedded Wafer Level BGA) Technology for Advanced Packaging S.W. Yoon, Yaojian Lin and Pandi C. Marimuthu STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore Seungwook.yoon@statschppac.com Abstract Current and future demands of mobile/portable electronic systems in terms of performance, power consumption, reliable system at a reasonable price are met by developing advanced/appropriate silicon process technology, innovative packaging solutions with use of chip-package-system co-design, low cost materials, advanced assembly and reliable interconnect technologies. In this article packaging evolution for hand held application is discussed with special focus on next generation chip embedding technology called ewlb in detail. To meet the above said challenges ewlb was developed which offers additional space for routing higher I/O chips on top of Silicon chip area which is not possible in conventional WLP or WLB. It also offers comparatively better electrical, thermal and reliability performance at reduced cost with possibility to address more Moore [advanced technology nodes with low-k dielectric materials in SoC] and more than Moore [heterogeneous integration of chips with different wafer technology as SiP solution in multi die or 3D ewlb approaches]. Currently 1st generation ewlb technology is available in the industry with 200mm and 300mm carrier size. This paper highlights some of the recent advancements in progress development and mechanical characterization in component level and board level reliability of next generation ewlb technologies of MCP and double-side 3D ewlb. Standard JEDEC tests were carried out to investigate component level reliability and both destructive/non-destructive analysis was performed to investigate potential structural defects. Daisychain Test vehicles were prepared and also tested for drop and TCoB (Temperature Cycle on Board) reliability in industry standard test conditions. There was significant improvement of characteristic lifetime with thinned ewlb in TCoB performance because of its enhanced flexibility of package. Introduction Integrated Circuits fabricated on silicon is assembled in different forms of electronic packages and are used extensively in electronic products such as personal, portable, healthcare, entertainment, industrial, automotive, environmental and security systems. Current and future demands of these electronic systems in terms of performance, power consumption, reliable system at a reasonable cost are met by developing advanced/appropriate silicon process technology, innovative packaging solutions with use of chip-package-system co-design, low cost materials, advanced assembly and reliable interconnect technologies. In this article packaging evolution for hand held application is discussed with special focus on next generation chip embedding technology called ewlb in detail. In just one decade hand phone has transformed from a simple communication device into more complex system integrating features that allow customers to use it as a multipurpose gadget. The carrier technology has jumped from 1G to 3G, changing at the rate of every two years and with room for potential growth with global adoption. Moving forward with this trend, packaging semiconductor devices for handheld electronics has become more challenging than ever before. Growing mismatch in interconnect gap, adding different functional chips for different features and application in similar system footprint and package size reduction to increase battery size for extended usage has opened the window for innovative embedding packaging technology. To meet the above said challenges ewlb was developed [1] which offers additional space for routing higher I/O chips on top of Silicon chip area which is not possible in conventional WLP or WLB. It also offers comparatively better electrical, thermal and reliability performance at reduced cost with possibility to address more Moore [decreasing technology nodes with low-k dielectrics in SoC] and more than Moore [heterogeneous integration of chips with different wafer technology as SiP solution in multi die or 3D ewlb approaches]. WLP applications are expanding into new areas and are segmenting based on I/O count and device. The foundation of passive, discrete, RF and memory device is expanding to logic ICs and MEMS. The WLP segment has matured over the past decade, with numerous sources delivering high-volume applications across multiple wafer diameters and expanding into various end-market products. With infrastructure and high volumes in place, a major focus area is cost reduction. One of the most well known examples of a fan-out 427

2 WLP structure is ewlb technology by Infineon Technologies AG. This technology uses a combination of front- and back-end manufacturing techniques with parallel processing of all the chips on a wafer, which can greatly reduce manufacturing costs. Its benefits include a smaller package footprint compared to conventional leadframe or laminate packages, medium to high I/O count, maximum connection density, as well as desirable electrical and thermal performance. It also offers a high-performance, power-efficient solution for the wireless market.[2] I. ewlb Technology ewlb technology is addressing a wide range of factors. At one end of the spectrum is the packaging cost along with testing costs. Alongside, there are physical constraints such as its footprint and height. Other parameters that were considered during the development phase included I/O density, a particular challenge for small chips with a high pin count; the need to accommodate SiP approaches, thermal issues related to power consumption and the device's electrical performance (including electrical parasitic and operating frequency) [3]. The obvious solution to the challenges was some form of WLP. But two choices presented themselves: Fanout or Fan-in. FO-WLP is an interconnection system processed directly on the wafer and compatible with motherboard technology pitch requirements. It combines conventional front- and back-end manufacturing techniques, with parallel processing of all chips. There are three stages in the process. Additional fab steps create an interconnection system on each die, with a footprint smaller than the die. Solder balls are then applied and parallel testing is performed on the wafer. Finally, wafers are sawn into individual units, which are used directly on the motherboard without the need for interposers or underfill. Figure 1. (a) ewlb packages and (b) schematics of ewlb products portfolio. Advantage of ewlb Technology The current BGA package technology is limited by the organic substrate capability. Moving to ewlb helps overcome such limitations and also simplifies the supply chain. Building the substrate on the package itself, allows for higher integration and routing density in less metal layers. ewlb is a next generation platform that will support future integration, particularly for wireless devices and this packaging technology has a number of important features. Transition to ewlb packaging technology enables a significant reduction in recurring costs by eliminating the need for expensive substrates. The advantage of ewlb packaging can be summarized in Table 1. Table 1. Advantage of ewlb packaging. 1.The smallest and thinnest package other than fan-in WLCSP 2.Excellent electrical and thermal performance -.Great for high frequency application -.Excellent for RF and mixed signal due to low parasitics compared to any laminate-based packages -.The lowest thermal resistance -.High density routing is easily implemented in RDL 3.No ELK damage issues for advanced Si nodes devices 4.Proven low cost path using a batch process & simple supply chain 5.Path to the flexible 3D packages any array patterns on the top 6.Scalable technology to a larger panel production Lower cost (a) Advanced flip chip nodes drive fine pitch combined with weaker low-k dielectric structures resulting in flip chip becoming narrower in terms of packaging process margin,. In addition, there is a big trend in being environmentally friendly, driving lead free and halogen free, or green, material sets. With ultra low-k and (b) 428

3 step ps. There wass found signifficant increasse in TCoB (Tem mperature Cy ycle on Boardd) reliability performance p with h thinner ew WLB. Drop reeliability also o improved sign nificantly. interconnects pitch becooming smaller and smallerr and with the shift to lead free materiaals, the technnical limitationss faced by the packagiing industry are becoming more challlenging. ew WLB technoology provides a window foor packaging next generaation devices inn a generic, lead-free/halogen free, ggreen packaging scheme. II. Thin SiP/Multi--Die ewlb Packagingg Side-byy-side SiP/muultichip packaaging can proovide more desiggn flexibility for SiP appliications becauuse a chip designner has more freedom in paad location as well as circuit block allocation. 3D ew WLB technoology w and spacce as utilizes very fine pitch metal line width L process, so it provides bbetter well as muulti-layer RDL technical ssolutions for multi-chip m pacckaging. It caan be used for vaarious combinnations such as, RF receiverr and digital deevice, PA (power ( amplifier) and IPD (integratedd passive devices) d and d memory and controller. ewlb uses fine f pitch metaallization and well controlled interconnectiion with wafeer fab lithograaphy process thuus it has great advantage to provide bbetter electrical pperformance compared c to wire-bondingg and organic subbstrate technoology. (a) ure 3. Comp parison of ppackage body y thickness Figu betw ween standard d and thin ewl LB. (b) ure 4. SEM micrographs of cross-secttion of thin Figu ewl LB. (total pacckage body thhickness 250um m) (c) R Reesults Pacckage Level Reliability Table T 2 showss the package level reliabiliity result of each h next generattion 3D ewlb B packages. They T passed JED DEC (Joint Electron Devicce Engineerin ng Council) stan ndard packag ge reliabilityy test such as MSL (Mo oisture Sensittivity Level) 1 with Pb-free solder conditions. Test vehicles v has 112x12mm bod dy size with All ewlb packages 0.4, 0.5mm baall pitch. ry standard paackage level succcessfully passed all industry reliaability with baall shear test aand OS(open-sshort) test. (d) Figure 2. SiP/Multi-diee ewlbs able 2. Packa age Level Relliability Resu ults of thin Ta ewlb packkages. Condition For mobbile and handdheld applicatiions, portabiliity is a critical factor for product p selecttion. The thiinner package caan provide better b board leevel reliabilitty as well as lighter and thinner profile in system leevel. gies, ewlb was Using advvanced thinniing technolog thinned doown to less thhan 250 um th hickness as shhown in Figure 3. The crittical technicall challenges w were g and removinng of handling thhe thin wafer and grinding Si/epoxy m material togeether using the t same proocess 429 Status MSL1 JE EDEC-J-STD-020 0D MSL1, 2260C Reflow (3x) - Tem mperature Cycliing (TC) after Precon n JESD22-A104 HA AST (w/o bias) affter Precon JESD22-A118-40C to 1125C 1000x 130C / 85% % RH 96hrs

4 High Temperature 150C Storage (HTS) JESD22-A103 BST after Multiple 260C Reflow Reflow * Tested by ball shear test and O/S test 1000h 20x will have isolation and metal layers, connected using conductive vias. It enables PoP (Package-on-Package), 3D SiP or 3D micro module. Key to the miniaturization of 3D SiP is the integration of the packaging steps as a functional part of the die and system solution. The PBGA replaced the lead frame by a printed circuit board (PCB) substrate, to which the die was electrically connected by wire bonding or flip chip technology, before covering with molding compound. ewlb takes the next step, eliminating the PCB, as well as the need to use wire-bonding or flipchip bumps to establish electrical contacts. Without a PCB, the package is inherently thinner, without thinning the die when lower profiles are required. PoP and SOW (System-on-Wafer) takes this integration a step further, placing one package on top of another for greater integration complexity and interconnect density. ewlb makes it a very flexible choice. ewlb technology also offers procurement flexibility, lower cost of ownership, better total system and solution costs and faster time to market. Each step along the path from SiP to PoP (Package on package) to ewlb represents improvements in these two areas. Each of these packages fit unique niches. For example, if size is most important, then stacked die will yield smaller packages. Moving into PoP increases board space, but improves cost structure. ewlb, with its potential to dramatically improve cost effectiveness and reduce entire systems to the size of a postage stamp, represents the best of both worlds. SiP, as the name implies, is a technology that allows the placement of several integrated circuits in one package, providing a complete set of device electronics in a small area. This technique saves board space by integrating devices that were once spread farther apart on the circuit board. Figure 6 showed standard thickness and thinned double-side 3D ewlb. Thin 3D ewlb has less than 0.5mm package height. Fig 7 showed the cross-section of 3D ewlb PoP after top package assembly, It has less than 1.0mm total package thickness with 5 dies in stacked package including solderballs. Board Level Reliability Results Fig. 5 shows Weibull plot of 12x12mm multi-die SiP ewlb TCoB reliability and it shows improvement of TCoB performance, 50% compared to standard ewlb. Fig. 6 shows Weibull plot of drop reliability of standard and thin ewlbs. It also shows significant improvement. Figure 5. Weibull Plot of TCoB reliability of 12x12mm standard (0.7mm) and thin (0.5mm) ewlb Packages.(-40/125C, 2cycle/hr) Figure 6. Weibull Plot of drop reliability of 12x12mm standard (0.7mm) and thin (0.5mm) ewlb Packages. Figure 7. Comparison of package height between thin and standard thickness 3D ewlb bottom. (a) III. Thin 3D SiP ewlb packaging [4,5] There is 3D ewlb approach with vertical interconnection; both sides of the reconstituted wafer 430

5 reliability of 3D SiP ewlb. (b) Figure 8. Micrographs of 3D SiP ewlb PoP (5-die SiP, 12x12mm) with (a) 1.2 mm package height and (b) less than 1.0 mm thickness including solder balls. Package Level Reliability Results Table 3 shows the package level reliability result of each next generation 3D SiP ewlb packages. They passed JEDEC (Joint Electron Device Engineering Council) standard package reliability test such as MSL (Moisture Sensitivity Level) 1 with Pb-free solder conditions. 3D SiP ewlb test vehicles has 12x12mm body size with 0.5mm ball pitch. All ewlb packages successfully passed all industry standard package level reliability with ball shear test and OS(open-short) test. Figure 9. Weibull Plot of TCoB reliability of 12x12mm standard (0.7mm) and thin (0.5mm) ewlb Packages.(-40/125C, 2cycle/hr) Table 3. Package Level Reliability Results of thin ewlb packages. Condition MSL1 JEDEC-J-STD-020D MSL1, 260C Reflow (3x) Temperature Cycling -40C to 125C (TC) after Precon JESD22-A104 HAST (w/o bias) after 130C / 85% RH Precon JESD22-A118 High Temperature 150C Storage (HTS) JESD22-A103 BST after Multiple 260C Reflow Reflow * Tested by ball shear test and O/S test Status x 96hrs 1000h 20x Figure 10. Warpage Behavior of PoP bottom; doubleside 3D SiP ewlb (450um, 250um) and fcbga-popbottom. Warpage Behavior with Reflow Profile As shown in Figure 10, 3D SiP ewlb PoPb also results in a much better warpage control over the entire reflow profile temperature range when compared to same size 12x12mm, 0.4mm pitch fcpopb. This is due to much lesser CTE mismatch between the mold compound and embedded silicon as well as 3dimensional well balanced structure of ewlb package. Better warpage control would result in improvement of PoP assembly and SMT yield of ewlb PoP when compared to conventional fcpop [6]. It also contribute for higher yield of SMT for fine pitch solder ball in Board Level Reliability Results Fig. 8 shows TCoB Weibull plot of 3D SiP ewlb test vehicles of 12x12mm body size with 0.5mm ball pitch without board level underfill. It shows improvement of TCoB performance, 40% compared to standard ewlb. For drop tests, standard Fig. 9 shows Weibull plot of drop reliability of standard ewlb of 12x12mm 3D SiP ewlb. Standard ewlb passed drop tests successfully so there was no further test for thin 3D ewlb samples. With board level underfill for thinned 3D SiP ewlb, TCoB first failure was reported after 3000cycles. So all results showed robust board 431

6 advance applications. CONCLUSION ewlb technology is an enhancement to standard WLPs, allowing the next generation of a WLP platform due to its fan-out capability. The benefits of standard fan-in WLPs such as low packaging/assembly cost, minimum dimensions and height as well as excellent electrical and thermal performance are true for ewlb as well. The ability to integrate passives like inductors, resistors and capacitors into the various thin film layers, active/passive devices into the mold compound and 3D vertical interconnection opens additional design possibilities for new Systems-in-Package (SiP) and 3D stacked packaging. Moreover, thin ewlb and 3D ewlb technology provides more value-add in performance and promises to be a new packaging platform that can expand its application range to various types of mobile/portable devices as well as 3D TSV integration for true 3D SiP systems. As the world demand for portable and mobile electronics like as smartphone and tablet has accelerated, the need to make semiconductors smaller, faster, lighter and cheaper has never been greater. As witnessed by the dramatic evolution of cellular phones, product differentiation today is driven by everexpanding functionality, feature sets, multifunctionality and faster communications. At the same time, consumers have made clear their desires for feature-rich products in compact form factors to enable maximum portability. Thin and 3D ewlb technology is successfully enabling semiconductor manufacturers to provide the smallest possible, highest-performing semiconductors. Marimuthu, Advanced Packaging Solutions of Next Generation ewlb Technology, Proceedings of 13 th Electronic Packaging Technology Conference 2011, 9-11 Dec 2011, Singapore (2011) [5]Seung Wook Yoon, Yaojian Lin, Yonggang Jin, Jerome Teysseyre, Xavier Baraton and Pandi C. Marimuthu, Advanced 3D SiP Packaging Solution, Device Packaging Conferences 2012, Pheonix, Arizona (2012) [6]Carson, F., Kim, Y. C. and Yoon, I. S., 3-D stacked package technology and trends, Proc. of the IEEE, Vol. 97, No. 1, Jan. 2009, pp REFERENCE [1]M. Brunnbauer, et al., Embedded Wafer Level Ball Grid Array (ewlb), Proceedings of 8th Electronic Packaging Technology Conference, Dec 2009, Singapore (2006) [2]Graham pitcher, Good things in small packages, Newelectronics, 23 June 2009, p18-19 ( 2009) [3] M. Brunnbauer, et al., Embedded Wafer Level Ball Grid Array (ewlb), Proceedings of 8th Electronic Packaging Technology Conference, Dec 2009, Singapore (2006) [3]Seung Wook YOON, Meenakshi PADMANATHAN, Andreas BAHR, Xavier BARATON and Flynn CARSON, 3D ewlb (embedded wafer level BGA) Technology: Next Generation 3D Packaging solutions, San Francisco, IWLPC 2009 (2009) [4]Yonggang Jin, Jerome Teysseyrex, Xavier Baraton, S. W. Yoon, Yaojian Lin and Pandi C. 432